Increasing PV Inverters Reliability Through Dynamic Hardware Allocation
In recent years, there has been a significant focus on driving down the price of power electronics for photovoltaic (PV) applications, most commercial systems today are replaced, rather than repaired when they fail. This paradigm increases waste generation, disposing of the complete system when potentially only a single element is nonfunctional. Through dynamic hardware allocation (DHA), a range of identical modules and control scheme are used to dispatch hardware resources within the inverter to perform varying functions according to the needs of the converter. The DHA system facilitates module-level replacement during lifetime, minimizing waste generation and repair/replacement costs. This allows gradual updating of technologies, and eases manufacturing costs associated with service and replacement, eliminating the need to maintain stock of antiquated designs through the entire product lifetime.
Proposed dual current programmed mode (DCPM) control loop network.
This research focusses on building a 2 kW residential photovoltaic single-phase string inverter that is reliable, robust, efficient, and low cost. Traditional PV converter topologies are implemented using single-purpose power stages and passives. A conceptual DHA system is implemented with a common set of hardware resources that shift operation between active power filtering (APF: double-line-frequency decoupling) and line frequency inverter operation. A plurality of identical modules comprise the shared hardware resources. According to a dispatch controller, each module in the DHA system is either a bucktype APF (with embedded energy storage) or a zero voltage switching (ZVS) inverter phase leg, in each case controlled through a low frequency current reference. The system uses a dual-current programmed mode (DCPM) to achieve ZVS of all transistor while regulating peak and valley currents in each period. This modulation results in large ripple, particularly at high output current, which is mitigated simply by the multiphase nature of the DHA, allowing reduced EMI filtering. The modular DHA structure also allows ripple energy storage capacitors to be embedded at the module level, breaking the energy storage into smaller and therefore more reliable banks, and allowing the system to be devoid of a single point of failure.
The ongoing research is also looking at optimally sizing the APF energy storage capacitors and the optimal operation of each modules between APF and inverter operation. With separate inverter and APF operation, power stages of each must be sized according to the individual maximum instantaneous power of each. When completed, the proposed research will demonstrate a paradigm-altering approach to power electronics design, applied to PV inverters.
How WBG Can Help
High switching speed is one of the main advantages of GaN transistors. With the fast dv/dt and di/dt transitions, converters can be operated at significant switching frequencies with minimal losses in comparison to Silicon devices. However, the effect of parasitic inductance and capacitances become more critical. Faster edge transitions contain more high-frequency harmonic content that causes anomalous switching behavior in traditional current programmed mode control used to realize ZVS in the GaN based-inverter. To overcome these challenges in our research, we have developed a simple and low cost dual-current programmed mode (DCPM) control circuit that achieves better noise immunity and low propagation delay at high switching frequency . Fig. 3 shows the proposed DCPM control loop which uses a combination of Oneshots and AND gates logic to create a controllable blanking time following each switching action to reject ensuing noise. This implementation significantly improves switching noise immunity in high frequency in DCPM control GaN based inverter.
- Kamal Sabi
 K. Sabi, D. Costinett, "Noise Mitigation and Delay Compensation in High Frequency Dual Current Programmed Mode Control," in 2018 IEEE Applied Power Electronics Conference and Exposition (APEC), March 2018