Resistor divider implementation of a DC-DC converter

At left, a resistor divider is used to implement a step-down conversion of the input voltage. If \(R_{var}=R_{load}\), then \(V_{out}=V_{in}/2\). If \(R_{load}\) models, e.g. a microprocessor, the power consumption of the load will fluctuate as the processor workload changes. In this case, \(R_{load}\) may change over time, requiring \(R_{var}\) to also change to match it, or else \(V_{out}\) will vary.

One possible implementation of the variable resistor \(R_{var}\) is shown at right. An op-amp is used in negative feedback configuration to drive the base of a transistor. Using negative feedback, the base is driven with only as much current as is necessary to force \(V_{out} = v_{ref}\). Because \(v_{ce} = V_{in}-V_{out}\), the transistor will be in the active region with high gain for most operating conditions. If the transistor has a large \(\beta\), then \(i_{out}\approx{i_{in}}\).

If the converter is designed with \(v_{ref} = V_{in}/2\), the efficiency of the linear regulator will be, at maximum $$\eta = \frac{V_{out}I_{out}}{V_{in}I_{in}} = \frac{V_{out}I_{in}}{V_{in}I_{in}} = \frac{V_{out}}{V_{in}} = \frac{1}{2}$$

Linear regulator circuit

This is the same efficiency that would be achieved in the original resistor divider. Therefore, linear regulators are not good candidates for power conversion at high efficiency, except when \(V_{in}\approx V_{out}\). Further, one can conclude that when high efficiency is a goal, circuit elements such as resistors and linear-mode transistors should be avoided in the main power path of the converter.

Switched capacitor voltage divider

A switched capacitor converter, such as the one at left, is an alternative to the linear regulator discussed previously. Note first that only ideal switches and capacitors are used to implement the converter; lossy resistors and linear-mode transistors are eliminated.

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Switched capacitor converter equivalent circuit with switches in position 1 (a) and in position 2 (b)

The converter operates by rapidly switching both single-pole dual-throw switches, synchronously, between positions 1 and 2. The equivalent circuits with the switches in either position are shown at right. In position 1, both capacitors \(C_1\) and \(C_2\) are in series. Initially, the input voltage will be shared equally on each. If the converter remains in this state, however, \(R_{load}\) will drain \(C_2\) and \(V_{out}\) will go to zero. Instead, the switches are rapidly commutated to position 2, in which \(C_1\) and \(C_2\) are in parallel.

By switching rapidly between positions 1 and 2, the converter will produce an output voltage \(V_{out}=V_{in}/2\). The output voltage will not be purely DC. In position 1, \(R_{load}\) will drain \(C_2\) slightly, and \(C_1\) will be slightly charged. Then in position 2, \(C_1\) will transfer some of its energy to \(C_2\). If the switching happens rapidly enough, the resulting variation in \(v_{out}\) can be made sufficiently small as to be negligible.

Because only ideal capacitors and switches have been used, this converter is ideally lossless, \(\eta\rightarrow{1}\). Small parasitics of the switches and capacitors will always result in some, non-zero power loss, but implementations with \(\eta\gt{95\%}\) are possible.

One drawback of the switched capacitor converter is that, for this circuit operation, the output voltage cannot be changed. It will always remain true that \(V_{out}=V_{in}/2\). Different ratios can be achieved using additional capacitors and switches, but for all converters of this type, the conversion ratio, \(M=V_{out}/V_{in}\) is a constant value.

Buck Converter

The buck converter, shown at left, provides an alternate means of stepping down voltage. Note that, like the switched capacitor converter, only ideal switches and energy storage elements are used. Therefore, it remains feasible that the converter can achieve very high efficiency. In comparison to the switched capacitor converter, one inductor is now used, and one SPDT switch and one capacitor have been eliminated.

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Buck converter equivalent circuit with switches in position 1 (a) and in position 2 (b)

Similar to the switched capacitor implementation, the SDPT switch is again commutated rapidly between positions 1 and 2. the equivalent circuit during either of the two switching states are shown at right.

Buck Converter switched node voltage

To analyze the converter, consider that the SPDT switch commutates between positions with some constant period, \(T_s\) (in seconds) and frequency \(f_s=1/T_s\). Within one period, the switch stays in position 1 for some percentage of the period, \(0\lt{D}\lt{1}\), known as the duty cycle.

Operation of the buck converter is most easily understood by examining the waveform of the switching node voltage, \(v_s\), shown at right. When the switch is in position 1, \(v_s=V_{in}\). When the switch is in position 2, \(v_s=0\). When the switching actions are timed as stated previously, the average value of \(v_s\) is $$\langle{v_s}\rangle = \int_0^{T_s}v_s(t)=DV_{in}$$

This shows that the average value of \(v_s\) is the duty cycle \(D\) multiplied by the input voltage. This has two interesting implications: first, if \(D\) can be controlled, the converter can now create an average voltage at \(v_s\) anywhere in the range \(0\lt\langle{v_s}\rangle\lt{V_{in}}\); second, if a circuit can be used to extract this average value at the output, \(V_{out}=\langle{v_s}\rangle\), the converter will generate an output voltage which is controlled by \(D\).

To the latter point, the \(L\)-\(C\) filter of the buck converter operates as a low-pass filter that can extract the average (DC) value of \(v_s\) while attenuating the high frequency harmonics of the square wave \(v_s\).

Compared to the switched capacitor converter, the buck converter gives more flexibility by allowing the converter to achieve any step-down conversion ratio \(M=V_{out}/V_{in} \), \(0\lt{M}\lt1\). This is accomplished by varying the duty cycle \(D\), which dictates the width of the "pulse" in \(v_s\). The technique is known as Pulse Width Modulation (PWM), and is widely used in power converters.

Boost Converter

The boost converter, shown at left, is functionally very similar to the buck, but instead steps up the output voltage, relative to the input, \(1\lt{M}\lt\infty\). This is again accomplished by energy buffering: energy from the input is transferred to the inductor \(L\), then delivered to the output in the following switching state.

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Boost converter equivalent circuit with switches in position 1 (a) and in position 2 (b)

This behavior, and the individual switching states, are shown at right. In the first switching state, \(V_{in}\) is applied across the inductor, causing a gradual increase in its current, and therefore its stored energy. In the second state, the inductor is connected to the output. Because inductor current must be continuous, the inductor will begin to transfer energy to the output resistor and capacitor, gradually decreasing its current. Before the current can reverse direction, the boost converter will switch again, and repeat the process.

It is beneficial to have large inductance \(L\) and capacitance \(C\). In switching interval 1, only the capacitor supplies the output; a large value will allow it to do so for all of \(DT_s\) with relatively small drop in voltage.

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Boost converter inductor current(a) and capacitor voltage (b) waveforms

Waveforms of the inductor current \(I_{in}\) and capacitor voltage \(v_{out}\) are shown at right. The ripple on each is magnified, but can be reduced to negligible amplitude by making \(L\) and \(C\) large values.

The conversion ratio, \(M\) can be solved by combining two characteristics of the circuit: the inductor current flows to the output only during the second switching state; and because no lossy elements have been used, the output power is equal to the input power. Expressed as equations, these statements are $$(1-D)I_{in}=\frac{V_{out}}{R}$$ and $$I_{in}V_{in} = \frac{{V_{out}}^2}{R}$$ Combining them together, and rearranging, the conversion ratio of the converter is $$M=\frac{V_{out}}{V_{in}}=\frac{1}{1-D}$$

Thus, for \(0\lt{D}\lt{1}\), the output voltage \(V_{out}\gt{V_{in}}\)

Cross-section of a vertical power MOSFET.

Each of the ideal switches used in the converter topology are implemented with a solid-state power device. Though true mechanical switches, such as relays, could be used, they generally large, switch too slowly, and exhibit too high power loss to be of use in high-performance conversion. Instead, transistors, diodes, and occasionally thyristors are used.

However, unlike signal-level devices used in analog or digital microelectronics, power semiconductors are required to block voltages and conduct currents which may be orders of magnitude larger. Taking the MOSFET as an example, a cross-section of a power semiconductor device is shown at right. The main current path through the device is vertical, rather than horizontal, allowing the power current when the device is conducting to flow more evenly throughout the die area. In devices rated for high voltage, a tall, lightly doped \(n^-\) epitaxial layer is used to ensure the device is able to avoid breakdown with large electric field stress. However, this region also contributes a significant resistance in the current conduction path, resulting in conduction losses. Parasitic resistances when the device is in the saturation region are shown at left. \(R_{epi}\), also known as the drift region resistance, is often dominant in high voltage devices.

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MOSFET cross-section showing parasitic resistances (a) and capacitances (b)

In order to make this resistance smaller, many unit cells are placed in parallel on a single die to form a power MOSFET. While this decreases the effective resistance of the device, it also increases the parasitic capacitance present between each of its terminals. These capacitances play a large part in determining the switching energy loss of the device. The capacitances store energy which may be dissipated each time the device turns on, but also slow down the switching transition itself. Whereas an ideal switch is always either a zero-resistance short or an ideal open, a power transistor spends some time transitioning in between theses states. During this time, the device may behave as a larger resistance, or as a fixed current with large drain-to-source voltage. In either case, the device will exhibit larger losses during its switching transition. In general, switching power losses are a function of the voltage and current applied to the device, the switching frequency, and the amount of time it takes to fully switch the device from cutoff to ohmic regions and back.

Smaller devices will have lower capacitance, reducing the switching power loss, but higher resistance, increasing the conduction loss. This tradeoff means that the selection of a power MOSFET is dependant upon the relative magnitude of each. Different device sizes may be optimal for alternate designs in terms of voltages, currents, and switching frequencies. A more detailed discussion of power semiconductor operation is given on the About Power Semiconductors page.

The achievable performance of a device at any size depends heavily on the materials, and the geometric design of all semiconductor, metal, and insulator regions in the device cross-section. Wide bandgap semiconductors have superior material properties that allow this tradeoff to result in overall better devices for power electronics applications.

When implementing a converter, further characteristics of a semiconductor device may also be important in addition to switching and conduction losses. Characteristics relating to robustness, reliability, noise immunity, performance over temperature, thermal resistance, and available packages all must be considered in a successful design.

Geometric and magnetic parameters of an example inductor

Though capacitors may generally be purchased, inductors for power electronics often need to be constructed custom for the design. An example inductor, made of a ferromagnetic material with permeability \(\mu\) and wrapped with \(n\) turns of a conducting wire is shown at right. In this arrangement, the inductance seen at the terminal defined by \(v_l\left({t}\right)\) is $$L=\frac{\mu{n^2}A_c}{l_m}$$

Depending on the application, the core may be made of many different materials. Some example core materials and their applications are given in the table below.

Example \(B\)-\(H\) curve for a core material

Core materials themselves are used to present a low-reluctance path for the flux generated from the winding to flow. The materials exhibit \(B\)-\(H\) curves, as shown at right, which define how magnetic field strength and flux density interact in the core. The slope of this curve is the material permeability \(\mu\). Note that, as the flux density in the core increases, approaching \(B_{sat}\), the slope of the curve decreases. This drop in permeability will cause a corresponding decrease in inductance: a phenomenon known as saturation. For a typical inductor, the flux density in the core can be approximated using Maxwell's equations to give $$ B(t) = \frac{\mu {n}}{l_m}i_l(t) = \frac{L}{nA_c}i_l(t) $$ Because \(B\) is directly proportional to \(i_L\), there is a limit on the current the inductor can conduct before it experiences saturation.

Design goals for fabricating an inductor may include items such as minimizing size and power losses. Any inductor exhibits to primary forms of power loss.

Plot of core and copper losses in a magnetic component

The interplay of these two loss mechanisms leads to an optimization problem for the total losses of the inductor. Under certain assumptions, a larger number of turns can be used to decrease core losses, by reducing the flux density in the core. However, a larger number of turns will result in a longer, and therefore more resistive winding, increasing copper losses. The tradeoff is shown at left, where the minimum total power loss \(P_{tot}\) occurs at an optimized number of turns \(n_{opt}\) for a given design. As the core material or converter design changes, the optimal design vary accordingly.

Examining the operation of the ideal power converter, there are nodes at which the voltage is a square wave, and loops through which the current is a square wave. To construct these square waves, near-instantaneous jumps in voltage/current are required. These jumps indicate, respectively, a very high \(dv/dt\) node or a large \(di/dt\) loop. Both cases present serious problems for circuits in the real-world, which exhibit parasitic capacitances and inductances between all nodes and through all conductors in the layout, in addition to the minimum parasitics of the devices themselves, and their packaging.

Real switching waveform of a buck converter

If ignored, these high \(dv/dt\) and \(di/dt\) transitions can cause significant issues in converter operation, including additional switching losses, increased electromagnetic interference, overvoltage or overcurrent, or loss of control. At left, the ideal switching waveforms of a buck converter are compared discussed previously, along with real switching waveforms seen when parasitic inductances in the circuit are considered.

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Buck converter switch implementation with gate driver shown (a) with high \(dv/dt\) nodes and \(di/dt\) loops (b)

The figures at right show a buck converter, where the ideal SPDT switch has been implemented using one MOSFET and one diode. To turn the MOSFET on and off, a gate driver, which acts as a high current buffer, is used to drive a square wave gate-to-source. During operation, the voltage \(v_s\) is as shown previously, and both the gate driver current and switch current have very high \(di/dt\). In layout, one goal is to minimize any parasitic inductance in a high \(di/dt\) loop, and reduce parasitic capacitance between any high \(dv/dt\) node and any other node. This is accomplished by carefully routing connections and selecting component placement. The figure below, borrowed from EPC shows the difference in waveforms a buck converter can exhibit with just a few millimetres of additional space in one of these loops.

Buck converter \(v_s\) with 1.6nH (left) or 0.5nH (right) of power loop inductance ^[1]

Previously, it was shown that it is possible to derive an ideal conversion ratio for a power converter, where the ratio between input and output voltage depended only on the converter duty cycle. In practice, the conversion ratio also has some dependence on the converter efficiency and the precise details of the PWM waveform. Further, these details will in turn vary with the output power, with variations in initial or lifetime degradation of component values, and with operating environment. To maintain a constant, precise output voltage, some form of closed-loop control is needed.

Because of the switching actions, power converters are inherently highly nonlinear, time-varying systems. Though possible, the control of nonlinear systems is quite difficult. In order to make the control problem tractable, control is often designed under two simplifying approximations.

These steps allow a switched mode power supply to be modeled as a linear equivalent circuit, for which traditional Laplace-domain analysis of transfer functions can be applied. However, at the same time, this model will be invalid in its prediction of dynamics at frequencies approaching \(f_s\). Alternate approaches to modeling using discrete time analysis, sampled data modeling, or multi-frequency averaging are more accurate under these conditions, but also more complex to employ. In most cases, a simpler approach is to ensure that the bandwidth of the control system is much slower than the switching frequency, so that the modeling remains accurate over the range of frequencies controlled in closed-loop.