High-power inductive wireless power transfer (WPT) systems for EVs are designed to meet specifications such as stray field, power level, efficiency, misalignment tolerance, and ground clearance. These metrics are all heavily influenced by the coil geometry. This paper proposes a coil design method based on the Fourier Analysis Method (FAM) which is an analytical method for directly designing coil geometries to meet stray field and power level requirements through an optimization of Fourier basis function coefficients. In this work, two 120 kW WPT proof-of-concept demonstrators with low stray field and high efficiency are built from FAM optimization results to validate the models and show the impact of the FAM design process. Experimental validation of the Gen. 2 demonstrator at 120 kW output power resulted in a measured DC/DC efficiency of 97.2% at alignment with a 125 mm airgap. At the 120 kW test point, the stray fields 80 cm away from the center of the airgap between the coil assemblies were 3.4 µT(rms) on the X-axis and 3.5 µT(rms) on the Y-axis, much lower than the 27 µT(rms) ICNIRP limit.

With the growth of electric vehicle (EV) popularity, different charging options to increase user convenience and reduce charging times are being considered and researched. Among these, inductive wireless power transfer (WPT) systems for EVs are being designed to meet specifications such as stray field, power level, efficiency, misalignment tolerance, and ground clearance, which are all heavily influenced by the coil geometry. The proposed Fourier Analysis Method (FAM) is an analytical method to directly design coil geometries to meet stray field and power level requirements through an optimization of Fourier basis function coefficients. The outputs of the optimization are complex, planar coil geometries that meet the power level and stray field constraints with minimized loss factors. Contours of these potentials determine the coil conductor paths and loss models predict the system efficiency and performance over misalignment. The Fourier representation of the geometry is used to conveniently calculate the coupling over misalignment, external proximity effect loss, and ferrite loss. A 6.6 kW prototype WPT system with low stray field and high efficiency is built from the optimization results to validate the models and showcase the usefulness of the FAM design approach.

To further improve the system integration and convenience of the battery charging system for electric vehicles, this letter proposed a multipurpose magnetic coupler-based charging solution that integrates bidirectional on-board charger (OBC), wireless power transfer (WPT), and an auxiliary power module (APM). The proposed solution presents multiple highlights: 1) the first exhibited solution to integrate OBC, WPT, and APM in one unit; 2) magnetic integration that uses a multiwinding WPT pad to eliminate the main transformer of OBC and APM; and 3) topological integration that saves multiple active and passive devices. This letter includes a description of the system topology, operation principles of individual charging modes, a novel magnetic coupler, and the design methodology. Finally, a prototype was constructed and different charging modes were tested to validate the proposed design.

This paper provides a complete coil and shielding design solution for a 6.6 kW electric vehicle wireless power transfer system based on compact self-resonant (SR) coils. Due to the presence of a conductive vehicle body above the receiver coil, vertical fringing flux must be shielded in any electric vehicle wireless charger. Using high-frequency SR coils, parasitic capacitance introduced by standard shielding design approaches degrades the quality factor of the coils. In this work, the high-frequency parasitic capacitance introduced by the magnetic and conductive shielding materials is analyzed in detail, and a shielding geometry optimization method is proposed. Using ferrite and an additional dielectric spacer, prototype aluminum-backed SR coils are fabricated to validate the modeling. The total thicknesses of the transmitter and receiver coils are only 11.4 mm and 7.4 mm, respectively. The prototype coils achieve 92.3% DC-DC efficiency and 7.1 kW/dm3 volumetric power density. This paper demonstrates the first 6.6 kW WPT system for EV charging using compact megahertz-self-resonant coils including a complete magnetic and conductive shielding implementation.

This article proposes a high-efficiency single-phase GaN-based rectifier with reactive power transfer for use in front-end power supplies as an efficient alternative to centralized reactive power compensation. A full-range zero-voltage switching (ZVS) modulation for both unity power factor (PF) operation and nonunity PF operation is proposed for the GaN-based rectifier in critical conduction mode (CRM) operation. A frequency limitation method is also developed to limit the peak frequency during the ac current zero-crossing. Also, a GaN-based T-type totem-pole rectifier is proposed to overcome the control challenge in CRM during the ac voltage zero-crossing. Meanwhile, a digital-based control scheme is developed to implement ZVS operation and reactive power regulation. The proposed rectifier and ZVS control have the advantages of simple topology, high efficiency, straightforward control implementation, and capability of flexible reactive power regulation. A 1.6-kVA prototype of the GaN-based CRM T-type totem-pole rectifier is built and demonstrated with full-range ZVS operation, 98.9% full-load efficiency, and flexible reactive power regulation with smooth dynamic response.

A high-power, high-frequency wireless power transfer system for electric vehicles (EVs) is proposed in this article with lightweight and compact coil design. Leveraging a multilayer nonuniform self-resonant coil, no external capacitor is needed for compensation and the high-frequency conduction loss is mitigated by sharing current between multiple copper layers. The analytical model for the proposed coil is provided, and prototype coils with 200-mm radius are fabricated and tested, achieving a quality factor over 450 at 3 MHz. The optimized design for both coils and a GaN-based power stage are detailed and validated experimentally. Experimental tests show 95.2% dc–dc efficiency with 6.6-kW power transferred across a 100-mm coil-to-coil distance with 52.5 kW/m² power density. The system demonstrates the first 6.6-kW wireless power transfer system for EV charging using compact self-resonant coils at MHz.

In this article, a wireless charging architecture employing a multilevel switched-capacitor (MSC) ac–dc rectifier is investigated. The proposed MSC rectifier features a multilevel design that is scalable to accommodate different power ratings and load ranges. The topology showcases advantages for wireless power transfer (WPT) systems in terms of compactness, efficiency, impedance tunability, and harmonic attenuation. The single-stage active topology is capable of varying its low-distortion staircase input voltage to tune the WPT system for high system-wide efficiency. A seven-level, 20-W prototype is used to verify the WPT loading and loss analysis. The prototype operates at 150 kHz with up to 3:1 step-down conversion ratio to an output voltage of 5.0 V. The experimental peak dc-to-dc efficiency is 93.8% and the rectifier peak efficiency is 98.3%. The rectifier demonstrates low waveform distortion and high efficiency across many WPT loading conditions, solidifying its place as a strong candidate for wireless power applications.

This article details the systematic design of a 100-W multiload wireless charging station. The station provides positional flexibility for the receivers, exhibits limited cross-channel disturbance, and has high efficiency. The positional flexibility is achieved using a transmitter coil design approach, which uses interleaved windings and controlled coil geometry to shape the magnetic field. The limited cross-channel disturbance is realized with an immittance network, which maintains a constant transmitter coil current. A holistic system-level modeling and design method is proposed to design the entire system for maximum efficiency. The first step is decoupling each stages using parameterized source and/or load of adjacent stages, and optimize internally for minimum loss, which leads to a reduced design space. The second step is system-wide optimization, which addresses power loss interdependence. A 100-W, 6.78-MHz experimental system with a 0.5 × 0.5 m$^2$ transmitter coil is demonstrated. The measured magnetic field variation on the charging surface is 15.9%. And the system shows no cross-channel disturbance when charging two 50-W receivers. The measured dc-to-dc efficiency is 92.8%.

The GaN-based critical conduction mode (CRM) totem-pole power factor correction (PFC) converter with full-line-cycle zero voltage switching (ZVS) is a promising candidate for high-efficiency front-end rectifiers. However, the input current can be degraded by line-cycle current distortion and ac line zero-crossing current spikes, and maintaining reliable ZVS control is difficult in noise-susceptible high-frequency environments. In this paper, a detailed analysis of the current distortion issues in a GaN-based CRM totem-pole PFC with digital ZVS control is provided, and effective approaches are proposed to mitigate different kinds of current distortion and ensure stable ZVS control under high-frequency operation. The proposed solutions have the advantages of straightforward implementation and do not increase the control complexity. The current distortion issues are demonstrated in two GaN-based CRM totem-pole PFC prototypes, a 1.5 kW PFC for data centers and a 100 W PFC in a 6.78 MHz wireless charging power supply for consumer electronics. The proposed methods are experimentally verified with effective mitigation of the current distortion and improvement of the converter power efficiency.

This article establishes an analytical model for the device drain-source overvoltage related to the two loops in three-level active neutral point clamped (3L-ANPC) converters. Taking into account the nonlinear device output capacitance, two common modulation methods are investigated in detail. The results show that the line switching frequency device usually has higher overvoltage, and the switching speed of the high switching frequency device is not strongly influenced by the multiple loops. By keeping the nonactive clamping switch off, the effect of the nonlinear device output capacitance can be significantly mitigated, which helps reduce the overvoltage. Moreover, the loop inductance can be reduced with vertical loop layout and magnetic cancellation in the printed circuit board and busbar design. A 500-kVA 3L-ANPC converter using silicon carbide mosfets was built and tested. The experimental results validate the overvoltage model of the two modulation methods as well as the busbar design. With the nonactive clamping switch off, the overvoltage of both the high and line switching frequency devices is significantly reduced, which helps achieve higher switching speed.

In order to evaluate the feasibility of newly developed gallium nitride (GaN) devices in a cryogenically cooled converter, this article characterizes a 650-V enhancement-mode GaN high-electron mobility transistor (GaN HEMT) at cryogenic temperatures. The characterization includes both static and dynamic behaviors. The results show that this GaN HEMT is an excellent device candidate to be applied in cryogenic-cooled applications. For example, transconductance at cryogenic temperature (93 K) is 2.5 times higher than one at room temperature (298 K), and accordingly, peak di/dt during turn-on transients at cryogenic temperature is around 2 times of that at room temperature. Moreover, the ON-resistance of the channel at the cryogenic temperature is only one-fifth of that at room temperature. The corresponding explanations of performance trends at cryogenic temperatures are also given from the view of semiconductor physics. In addition, several device failures were observed during the dynamic characterization of GaN HEMTs at cryogenic temperatures. The ultrafast switching speed-induced high di/dt and dv/dt at cryogenic temperatures amplify the negative effects of parasitics inside the switching loop. Based on failure waveforms, two failure modes were classified, and detailed failure mechanisms caused by ultrafast switching speed are given in this article.

To better support the superconducting propulsion system in the future aircraft applications, the technologies of high-power high switching frequency power electronics systems at cryogenic temperatures should be investigated. This article presents the development of a 40-kW cryogenically cooled three-level active neutral point clamped inverter with 3 kHz output line frequency and 140 kHz switching frequency. Si mosfets are characterized at cryogenic temperatures, and the results show that they have promising performance such as lower on-resistance and switching loss. The design of the inverter is presented in detail with the special consideration of the cryogenic temperature operation. Moreover, a packaging and integration architecture is designed and fabricated to demonstrate the feasibility and performance of the inverter in the lab. It is able to achieve no leakage with good thermal and air insulation. With the inverter and packaging, the experimental results show that the inverter operates properly at cryogenic temperatures. The loss is measured at different load conditions, and the loss analysis is given, which shows that the cryogenically cooled inverter has 30% less loss than operating at room temperature.

Paralleling three phase three-level inverters is gaining popularity in industrial applications. However, analytical models for the harmonics calculation of a three-level neutral point clamped (NPC) inverter with popular space vector modulation (SVM) are not found in the literature. Moreover, how interleaving angle impacts the dc- and ac-side harmonics and electromagnetic interference (EMI) harmonics in parallel interleaved three-level inverters and how to optimize interleaving angle to reduce these harmonics have not been discussed in the literature. Furthering previous study, this article presents the modeling, analysis, and reduction of harmonics in paralleled and interleaved three-level NPC inverters with SVM. Analytical models for harmonic calculation are developed, and the dc-side harmonics characteristics of an NPC inverter are identified. The impact of interleaving angle on the ac-side voltage and dc-link current harmonics of parallel interleaved three-level NPC inverters is comprehensively studied. The impact of switching frequency and interleaving angle on EMI harmonics is also illustrated. Optimal interleaving angle ranges to reduce these harmonics are derived analytically. The developed models and harmonic reduction analysis are verified experimentally with two paralleled and interleaved three-level NPC inverters.

The attenuation performance of an electromagnetic interference filter can be significantly degraded by coupling, parasitics, and frequency-dependent nonlinearity, especially in high frequency (HF) range. This article reveals and investigates a mutual capacitive coupling effect in the popular filter structures with T-shaped joint. The mechanism is explained and the impact on filter attenuation is analyzed, which show this coupling is the dominant cause of performance degradation of T-shaped filters and a major cause for other T-shape-related filters. The effect patterns for both common-mode (CM) and differential-mode (DM) filters are analytically derived and further examined in multistage filter structures. Mitigation solutions using PCB slits and grounded shielding are proposed to improve filter transfer gain up to 30 dB in the HF range. A topological strategy is also presented, further enhancing filter attenuation. In addition, the impact of relative positions of the inductors on the coupling capacitance is discussed, and five positions are experimentally studied and compared. Experimental results obtained from three-phase LCL and LCLC filters verify the significance of this coupling and the effectiveness of the mitigation methods.

In order to apply power electronics systems to applications such as superconducting systems under cryogenic temperatures, it is necessary to investigate the characteristics of different parts in the power electronics system. This article reviews the influence of cryogenic temperature on power semiconductor devices including Si and wide bandgap switches, integrated circuits, passive components, interconnection and dielectric materials, and some typical cryogenic converter systems. Also, the basic theories and principles are given to explain the trends for different aspects of cryogenically cooled converters. Based on the review, Si active power devices, bulk Complementary metal-oxide-semiconductor (CMOS) based integrated circuits, nanocrystalline and amorphous magnetic cores, NP0 ceramic and film capacitors, thin/metal film and wirewound resistors are the components suitable for cryogenic operation. Pb-rich PbSn solder or In solder, classic printed circuit boards material, most insulation papers and epoxy encapsulant are good interconnection and dielectric parts for cryogenic temperatures.

This paper studies how an outer fractional winding can impact the equivalent parallel capacitance (EPC) of a differential-mode inductor, which is a critical passive component in a power electronic converter to combat with electromagnetic noises, and proposes a winding scheme that can reduce EPC and increase inductance, achieving both high-frequency filtering performance and high density. To perform these studies, a comprehensive layer capacitance model based on energy equivalence principle is established, which decouples EPC contribution among three elements, i.e., outer fraction layer, layer-to-layer, and layer-to-core, thus enabling the impact evaluation of different winding elements and schemes. Experimental comparison results have validated the accuracy of this EPC model and excellent performance of the proposed winding scheme with EPC reduction by 4×. It reveals that contrary to previous understanding, the inverse winding, in fact, is more effective for EPC reduction than the direct winding in most of the partial layer scenarios, and that by using this scheme with the outer fraction layer, 45% higher inductance and slightly less EPC can be achieved, compared to the single-layer winding design.

Three-level converters are more susceptible to parasitics compared with two-level converters because of their complicated structure with multiple switching loops. This paper presents the methodology of busbar layout design for three-level converters based on magnetic cancellation effect. The methodology can fit for 3L converters with symmetric and asymmetric configurations. A detailed design example is provided for a high power three-level active neutral point clamped (ANPC) converter, which includes the module selection, busbar layout, and DC-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. The results match with each other, and the inductances of short and long loops are 6.5 nH and 17.5 nH respectively, which are significantly lower than the busbars of NPC type converters in other references.

Series-series compensated inductive power transfer (SSIPT) systems have been widely studied and characterized for constant resistance loads (CRLs) and constant voltage loads (CVLs), but much less so for constant power loads (CPLs), although CPLs have numerous applications. In this work, we address some of the fundamental knowledge gaps for SSIPT/CPL systems that we believe have not been fully explored in the literature. First, we apply Middlebrook's stability criterion to derive a closed-form impedance-based stability condition for SSIPT/CPL systems. The derivation of the equilibrium solution is based on small-signal analysis and we show its consistency with intuitive results from perturbation-based arguments. Second, we show that the power transfer efficiency is minimum at the resonant frequency of the primary resonator. Third, the stability criterion is used to develop a straightforward approach for finding the operating frequency and input voltage that achieves near-maximum power transfer efficiency. This solution is useful as a starting point for a more meticulous parameter sweep to find the optimum input voltage and frequency values. Our analytical results are validated by performing frequency sweep measurements with two SSIPT experimental setups - one tuned to 165 kHz and the other to 6.78 MHz. We also provide an intuitive description and comparison of voltage-driven and current-driven CPLs. This topic is rarely treated in an intuitive manner and largely ignored, but we believe a solid conceptual understanding of voltage-driven and current-driven CPLs is beneficial for designers.

To understand the limitation of maximizing the switching speed of SiC low current discrete devices and high current power modules in hard switching applications, double pulse tests are conducted and the testing results are analyzed. For power modules, the switching speed is generally limited by the parasitics rather than the gate drive capability. For discrete SiC devices, the conventional voltage source gate drive (VSG) is not sufficient to maximize the switching speed even if the external gate resistance is minimized. The limitation of existing current source gate drives (CSG) are analyzed, and a CSG dedicated for SiC discrete devices is proposed, which can provide constant current during the switching transient regardless of the high Miller voltage and large internal gate resistance. Compared with the conventional VSG, the proposed CSG achieves 67% faster turnon time and 50% turn-off time, and 68% reduction in switching loss at full load condition.

This paper identifies extra junction capacitances and switching commutation loops introduced by line-frequency devices (i.e., non-active every other half line cycle) in three-level ac/dc converters and investigates the corresponding effects. Junction capacitances and power loops are well known as the key factors that impact converter switching loss and device stress, thus influence device selection, power stage layout, and thermal design. By examining switching transients of the commonly used T-shaped and I-shaped three-level converters, the cause and mechanism of the extra junction capacitances and power loops are presented. The impacts on switching loss, device voltage stress, and ac-side voltage/current distortion are respectively reported and analyzed. A loss calculation scheme for the three-level converter to include that extra loss is proposed. A power layout scheme to mitigate the device voltage stress is provided. Compensation and modeling of the voltage and current distortion are also proposed. Experimental results conducted on several types of three-level converter prototypes including a gallium nitride based 115 Vac/650 Vdc/1.5-kW/450-kHz Vienna-type rectifier and a SiC MOSFET based 1-kV/10-kW/ 280-kHz three-level active neutral-point-clamped inverter confirm the presented effects and verify the associated analysis and solutions.

A single-stage 6.78 MHz transmitter is proposed, which directly converts a utility ac input to a regulated, high-frequency (6.78 MHz) ac output for wireless power transmission. The topology integrates a totem-pole rectifier operating in a discontinuous conduction mode and an asymmetrical voltage cancellation controlled full-bridge inverter. Compared with the traditional cascaded multistage transmitters, this single-stage approach achieves high power efficiency over the full load range, utilizes fewer fast-switching devices, and shrinks the size of the converter. Constant current behavior at the output of the transmitter enables a fast response to a sudden load change. The operation and theoretical analysis of the single-stage transmitter is verified using a 100 W, GaN-based prototype. Experimental results demonstrate the capability of the converter to provide high power factor, low total harmonic distortion of the input current, and high conversion efficiency over the whole power range. The resulting prototype is suitable for implementation in wireless power systems where multiple consumer electronics loads are charged from a single transmitter.

Junction temperature is an important design/operation parameter, as well as, a significant indicator of device's health condition for power electronics converters. Compared to its silicon (Si) counterparts, it is more critical for silicon carbide (SiC) devices due to the reliability concern introduced by the immaturity of new material and packaging. This paper proposes a practical implementation using an intelligent gate drive for online junction temperature monitoring of SiC devices based on turn-off delay time as the thermo-sensitive electrical parameter. First, the sensitivity of turn-off delay time on the junction temperature for fast switching SiC devices is analyzed. A gate impedance regulation assist circuit is proposed to enhance the sensitivity by a factor of 60 and approach 736 ps/°C tested in the case study with little penalty on the power conversion performance. Next, an online monitoring unit based on gate assist circuits is developed to monitor the turn-off delay time in real time with the resolution less than 104 ps. As a result, the micro-controller is capable of “reading” junction temperature during the converter operation. Finally, a SiC-based half-bridge inverter is constructed with an intelligent gate drive consisting of the gate impedance regulation circuit and online turn-off delay time monitoring unit. Experimental results demonstrate the feasibility and accuracy of the proposed approach.

As wide-bandgap (WBG) devices and applications move from niche to mainstream, a new generation of engineers trained in this area is critical to continue the development of the field. This paper introduces a new hands-on course in characterization of WBG devices, which is an emerging and fundamental topic in WBG-based techniques. First, the lecture-simulation-experiment format based course structure and design considerations, such as safety, are presented. Then, the necessary facilities to support this hands-on course are summarized, including classroom preparation, software tools, and laboratory equipment. Afterward, the detailed course implementation flow is presented to illustrate the approach of close interaction among lecture, simulation, and experiment to maximize students' learning outcomes. Finally, grading for students and course evaluation by students are discussed, highlighting the findings and potential improvements. Detailed course materials are provided via potenntial.eecs.utk.edu/WBGLab for educational use.

A systematic study on a gallium nitride (GaN) high-electron-mobility transistor (HEMT) based battery charger, consisting of a Vienna-type rectifier plus a dc-dc converter, reveals a common phenomenon. That is, the high switching frequency, and high di/dt and dv/dt noise inside GaN converters may induce a dc drift or low frequency distortion on sensing signals. The distortion mechanisms for different types of sensing errors are identified and practical minimization techniques are developed. Experimental results on the charger system have validated these mechanisms and corresponding approaches, showing an overall reduction of input current total harmonic distortion (THD) by up to 5 percentage points and improved dc-dc output voltage regulation accuracy. The knowledge helps engineers tackle the troublesome issues related to noise.

Wide bandgap semiconductors are gradually being adopted in high power-density high efficiency applications, providing faster switching and lower loss, and at the same time imposing new challenges in control and hardware design. In this paper, a gallium nitride-based Vienna-type rectifier with SiC diodes is proposed to serve as the power factor correction stage in a high-density battery charger system targeting for aircraft applications with 800 Hz ac system and 600 V level dc link, where power quality is required according to DO160E standard. To meet the current harmonic requirement, PWM voltage distortion during the turn-off transient, is studied as the main harmonics contributor. The distortion mechanism caused by different junction capacitances of the switching devices is presented. A mitigation scheme considering the nonlinear voltage-dependent characteristics of these capacitances is proposed and then simplified from a pulse-based turn-off compensation method to a general modulation scheme. Simulation and experimental results with a 450 kHz Vienna-type rectifier demonstrate the performance of the proposed approach, showing a THD reduction from 10% to 3% with a relatively low-speed controller.

Newly emerged gallium nitride (GaN) devices feature ultrafast switching speed and low on-state resistance that potentially provide significant improvements for power converters. This paper investigates the benefits of GaN devices in an LLC resonant converter and quantitatively evaluates GaN devices' capabilities to improve converter efficiency. First, the relationship of device and converter design parameters to the device loss is established based on an analytical model of LLC resonant converter operating at the resonance. Due to the low effective output capacitance of GaN devices, the GaN-based design demonstrates about 50% device loss reduction compared with the Si-based design. Second, a new perspective on the extra transformer winding loss due to the asymmetrical primary-side and secondary-side current is proposed. The device and design parameters are tied to the winding loss based on the winding loss model in the finite element analysis (FEA) simulation. Compared with the Si-based design, the winding loss is reduced by 18% in the GaN-based design. Finally, in order to verify the GaN device benefits experimentally, 400- to 12-V, 300-W, 1-MHz GaN-based and Si-based LLC resonant converter prototypes are built and tested. One percent efficiency improvement, which is 24.8% loss reduction, is achieved in the GaN-based converter.

This paper presents an intelligent gate drive for silicon carbide (SiC) devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control gate voltages and gate loop impedances of both devices in a phase-leg configuration during different switching transients. Compared to conventional gate drives, the proposed circuit has the capability of accelerating the switching speed of the phase-leg power devices and suppressing the crosstalk to below device limits. Based on Wolfspeed 1200-V SiC MOSFETs, the test results demonstrate the effectiveness of this intelligent gate drive under varying operating conditions. More importantly, the proposed intelligent gate assist circuitry is embedded into a gate drive integrated circuit, offering a simple, compact, and reliable solution for end-users to maximize benefits of SiC devices in actual power electronics applications.

With the increased cloud computing and digital information storage, the energy requirement of data centers keeps increasing. A high-voltage point of load (HV POL) with an input series output parallel structure is proposed to convert 400 to 1 VDC within a single stage to increase the power conversion efficiency. The symmetrical controlled half-bridge current doubler is selected as the converter topology in the HV POL. A load-dependent soft-switching method has been proposed with an auxiliary circuit that includes inductor, diode, and MOSFETs so that the hard-switching issue of typical symmetrical controlled half-bridge converters is resolved. The operation principles of the proposed soft-switching half-bridge current doubler have been analyzed in detail. Then, the necessity of adjusting the timing with the loading in the proposed method is analyzed based on losses, and a controller is designed to realize the load-dependent operation. A lossless RCD current sensing method is used to sense the output inductor current value in the proposed load-dependent operation. Experimental efficiency of a hardware prototype is provided to show that the proposed method can increase the converter's efficiency in both heavy- and light-load conditions.

Dead time significantly affects the reliability, power quality, and efficiency of voltage-source converters. For silicon carbide (SiC) devices, considering the high sensitivity of turn-off time to the operating conditions (> 5× difference between light load and full load) and characteristics of inductive loads (> 2× difference between motor load and inductor), as well as large additional energy loss induced by the freewheeling diode conduction during the superfluous dead time (~15% of the switching loss), then the traditional fixed dead time setting becomes inappropriate. This paper introduces an approach to adaptively regulate the dead time considering the current operating condition and load characteristics via synthesizing online monitored turn-off switching parameters in the microcontroller with an embedded preset optimization model. Based on a buck converter built with 1200-V SiC MOSFETs, the experimental results show that the proposed method is able to ensure reliability and reduce power loss by 12% at full load and 18.2% at light load (8% of the full load in this case study).

Multifrequency wireless power transfer (WPT) is advantageous in facilitating compatibility with different WPT standards. However, implementing a multifrequency transmitter often requires compromises in system size, complexity, power transfer capability, or output regulation. In this paper, a single-inverter-based dual-mode WPT system is proposed. The system employs a multifrequency programmed pulse width modulation scheme. This multifrequency modulated inverter can simultaneously generate and regulate 100-kHz and 6.78-MHz outputs, or multiple frequencies within ranges of 87-300 kHz, which facilitates the development of multistandard WPT technology for consumer electronics. The principle of the proposed modulation is illustrated, where two different frequencies are concurrently modulated using a programmed pulse train of square waveforms for power delivery, while eliminating certain harmonics. Design tradeoffs and constraints are examined through analytical circuit models. Finally, experimental results are provided to verify the method on a gallium-nitride-based WPT prototype.

Electric-drive vehicles, including hybrid, plug-in hybrid, and electric vehicles, require a high-voltage (HV) battery pack for propulsion and a low-voltage (LV) dc bus for auxiliary loads. This paper presents an architecture that uses modular dc-dc bypass converters to perform active battery cell balancing and to supply current to auxiliary loads, eliminating the need for a separate HV-to-LV high step-down dc-dc converter. The modular architecture, which achieves continuous balancing of all cells, can be used with an arbitrary number of cells in series, requires no control communication between converters, and naturally shares the auxiliary load current according to the relative state-of-charge (SOC) and capacities of the battery cells. Design and control details are provided for LV low-power dual active bridge (DAB) power converters serving as the bypass converter modules. Furthermore, current sharing is examined and worst-case SOC and current deviations are derived for mismatches in cell capacities, SOCs, and parasitic resistances. Experimental results are presented for a system consisting of 21 series 25 Ah Panasonic lithium-ion NMC battery cells and 21 DAB bypass converters, with combined outputs rated to supply a 650-W auxiliary load.

This paper presents a comprehensive short-circuit ruggedness evaluation and numerical investigation of up-to-date commercial silicon carbide (SiC) MOSFETs. The short-circuit capability of three types of commercial 1200-V SiC MOSFETs is tested under various conditions, with case temperatures from 25 to 200 °C and dc bus voltages from 400 to 750 V. It is found that the commercial SiC MOSFETs can withstand short-circuit current for only several microseconds with a dc bus voltage of 750 V and case temperature of 200 °C. The experimental short-circuit behaviors are compared, and analyzed through numerical thermal dynamic simulation. Specifically, an electrothermal model is built to estimate the device internal temperature distribution, considering the temperature-dependent thermal properties of SiC material. Based on the temperature information, a leakage current model is derived to calculate the main leakage current components (i.e., thermal, diffusion, and avalanche generation currents). Numerical results show that the short-circuit failure mechanisms of SiC MOSFETs can be thermal generation current induced thermal runaway or high-temperature-related gate oxide damage.

Gallium nitride (GaN) power devices are an emerging technology that have only recently become available commercially. This new technology enables the design of converters at higher frequencies and efficiencies than those achievable with conventional Si devices. This paper reviews the characteristics and commercial status of both vertical and lateral GaN power devices, providing the background necessary to understand the significance of these recent developments. In addition, the challenges encountered in GaN-based converter design are considered, such as the consequences of faster switching on gate driver design and board layout. Other issues include the unique reverse conduction behavior, dynamic Rds,on, breakdown mechanisms, thermal design, device availability, and reliability qualification. This review will help prepare the reader to effectively design GaN-based converters, as these devices become increasingly available on a commercial scale.

Gallium nitride (GaN) heterojunction field-effect transistors are an enabling technology for high-density converter design. This paper proposes a three-level dc-dc converter with dual outputs based on enhancement-mode GaN devices, intended for use as a battery charger in aircraft applications. The charger can output either 28 or 270 V, selected with a jumper, to satisfy the two most common dc bus voltage requirements in airplanes. It operates as an LLC converter in the 28 V mode and as a buck converter in the 270 V mode. In both operation modes, the devices can realize zero voltage switching (ZVS). With the chosen modulation method, the converter can realize automatic voltage balancing of the flying capacitor and the frequency doubling function to act as an interleaved converter. For the LLC mode, the resonant frequency is twice the switching frequency of primary-side switches, and for the buck mode, the frequency of the output inductor current is also twice the switching frequency. This helps to reduce the size of magnetics while maintaining a low switching loss. Also, the converter utilizes a matrix transformer, with resonant parameters designed to reduce conduction loss and avoid ZVS failure. The operating principle of the converter is analyzed and then experimentally verified on a 1.5-kW prototype with 1 MHz resonant frequency.

High power density is a desirable feature of power electronics design, which prompts economic incentives for industrial applications. In this paper, a gallium nitride (GaN)-based 2-kVA single-phase inverter design was developed for the Google Little Box Challenge, which achieves a 102-W/in3 power density. First, the static and dynamic temperature-dependent characteristics of multiple SiC and enhancement-mode GaN FETs are investigated and compared. Based on the device testing results, several topologies of the inverter stage and different power decoupling solutions are compared with respect to the device volume, efficiency, and thermal requirements. Moreover, some design approaches for magnetic devices and the implementation of gate drives for GaN devices are discussed in this paper, which enable a compact and robust system. Finally, a dc notch filter and a hard switching full-bridge converter are combined as the proposed design for the prototype. A 2-kVA prototype is demonstrated, which meets the volume, efficiency, and thermal requirements. The performance of the prototype is verified by the experimental results.

Nonlinear, voltage-dependent capacitances of power semiconductor devices are capable of having significant impact on the operation of switched-mode power converters. Particularly at high switching frequency, these nonlinearities play a significant role in determining switching times, losses, and converter dynamics during switching transitions. In order to accommodate the well-established design and analysis techniques commonly used for linear circuits, this paper examines the nonlinear voltage-dependence of switching device capacitances and proposes a circuit-oriented analysis technique that allows the parasitic capacitances to be replaced with linear equivalents. The multitude of developed equivalents are verified through full nonlinear simulation in both MATLAB/Simulink and SPICE, as well as through experimental results.

Double pulse test (DPT) is a widely accepted method to evaluate the switching characteristics of semiconductor switches, including SiC devices. However, the observed switching performance of SiC devices in a PWM inverter for induction motor drives is almost always worse than the DPT characterization, with slower switching speed, more switching losses, and more serious parasitic ringing. This paper systematically investigates the factors that limit the SiC switching performance from both the motor side and inverter side, including the load characteristics of induction motor and power cable, two more phase legs for the three-phase PWM inverter in comparison with the DPT, and the parasitic capacitive coupling effect between power devices and heat sink. Based on a three-phase PWM inverter with 1200 V SiC MOSFETs, test results show that the induction motor, especially with a relatively long power cable, will significantly impact the switching performance, leading to a switching time increase by a factor of 2, switching loss increase up to 30% in comparison with that yielded from DPT, and serious parasitic ringing with 1.5 μs duration, which is more than 50 times of the corresponding switching time. In addition, the interactions among the three phase legs cannot be ignored unless the decoupling capacitors are mounted close to each phase leg to support the dc bus voltage during switching transients. Also, the coupling capacitance due to the heat sink equivalently increases the junction capacitance of power devices; however, its influence on the switching behavior in the motor drives is small considering the relatively large capacitance of the motor load.

This paper presents a board-level integrated silicon carbide (SiC) mosfet power module for high temperature and high power density application. Specifically, a silicon-on-insulator (SOI)-based gate driver capable of operating at 200 °C ambient temperature is designed and fabricated. The sourcing and sinking current capability of the gate driver are tested under various ambient temperatures. Also, a 1200 V/100 A SiC mosfet phase-leg power module is developed utilizing high temperature packaging technologies. The static characteristics, switching performance, and short-circuit behavior of the fabricated power module are fully evaluated at different temperatures. Moreover, a buck converter prototype composed of the SOI gate driver and SiC power module is built for high temperature continuous operation. The converter is operated at different switching frequencies up to 100 kHz, with its junction temperature monitored by a thermosensitive electrical parameter and compared with thermal simulation results. The experimental results from the continuous operation demonstrate the high temperature capability of the power module at a junction temperature greater than 225 °C.

This letter describes a very simple implementation of a digital pulse width modulator (DPWM) under 100 ps resolution in low-cost field-programmable gate arrays (FPGAs). The implementation is based on internal carry chains and logic resources which are present in most FPGA families. The proposed approach does not require manual routing or placement, consumes few hardware resources, and does not rely heavily on specialized phase-locked loop or clock management resources. A 50-MHz switching frequency DPWM with 60-ps resolution and a 1-MHz switching frequency DPWM with 90-ps resolution are experimentally demonstrated, with monotonicity and excellent linearity.

A control scheme is developed to maximize efficiency over a wide range of loads for a dual active bridge converter. A simple control circuit using only phase-shift modulation is proposed which considers both the converter conversion ratio and switching dead times in order to maintain high efficiency in the presence of varying loads. To demonstrate feasibility of the proposed control method, experimental results are presented for a 150-to-12 V, 120-W, 1-MHz prototype converter which has 97.4% peak efficiency and maintains greater than 90% efficiency over a load range between 20 and 120 W.

This paper discusses far-field wireless powering for low-power wireless sensors, with applications to sensing in environments where it is difficult or impossible to change batteries and where the exact position of the sensors might not be known. With expected radio-frequency (RF) power densities in the 20-200- μW/cm2 range, and desired small sensor overall size, low-power nondirective wireless powering is appropriate for sensors that transmit data at low duty cycles. The sensor platform is powered through an antenna which receives incident electromagnetic waves in the gigahertz frequency range, couples the energy to a rectifier circuit which charges a storage device (e.g., thin-film battery) through an efficient power management circuit, and the entire platform, including sensors and a low-power wireless transmitter, and is controlled through a low-power microcontroller. For low incident power density levels, codesign of the RF powering and the power management circuits is required for optimal performance. Results for hybrid and monolithic implementations of the power management circuitry are presented with integrated antenna rectifiers operating in the 1.96-GHz cellular and in 2.4-GHz industrial-scientific-medical (ISM) bands.

This brief discusses a low-power wireless sensor based on commercial components for sensing and data transmission. The sensor is wirelessly powered from the far field through an integrated single or dual-polarization antenna, rectifier, and power management module. Since the unit is intended for mobile use, the variable available power is monitored, and the duty cycle for wireless data transmission adaptively adjusted through the use of a low-power microcontroller and a custom power management circuit. In sleep mode, the circuit consumes 1 μA at 2.5 V.

Quantum engineering of electronic energy states using nanoscale layers of semiconductor compounds allows the design and the observation of quantum phenomena which are typically observed in atomic structures. Furthermore, semiconductors are present in nearly all modern electronic devices and are a crucial component of integrated circuits. Due to the relatively high rate of manufacturing defects, it is crucial to have a method for testing new semiconductor formations without requiring a sample to be fabricated. A simple, fast and very accurate numerical technique is presented to calculate the eigenstates of such arbitrary quantum structures. The method is based on a high-order finite difference scheme which allows the use of sparse matrix algebra, thus, significantly reducing computational time and allowing for high precision results even for the high energy states.

Nonlinear magnetic properties in power electronics applications, such as permeability and core loss cause significant discrepancies between magnetic designs and prototype measurements, leading to iterative prototyping efforts. To address this issue, a bottom-up approach that is based on the physics of magnetic material is proposed to unveil the fundamental origin of nonlinearity. The physical parameters such as magnetization, gyromagnetic ratio, damping factor, etc., are translated to equivalent circuit parameters. The nonlinear magnetization dynamics of a single magnetic domain are described by an equivalent circuit model derived from the Landau-Lifshitz-Gilbert (LLG) equation. A fictitious magnetic domain is used to demonstrate the developed model’s capability on predicting the nonlinearity that includes magnetization dynamics and hysteresis. Then, the model is further validated by a commercial material, TDK N87 toroidal core. The results such as B-H loop and permeability simulated from the circuit model are in close agreement with the datasheet, validating the feasibility of predicting magnetic material’s nonlinear performance from physics perspective rather than empirical approaches.

Broad-scale modeling and optimization play a vital role in the design of advanced power converters. Optimization is normally implemented via brute force iterations of design variables or utilizing metaheuristic techniques which are time consuming for a wide range of potential topologies, device implementations, and operating points. Recently, discrete time state-space modeling has shown merits in rapid analysis and generality to arbitrary circuit topologies but has not yet been utilized under rapid optimization techniques across multiple converter parameters. In this work, we investigate methods to incorporate rapid gradient-based optimization techniques to leverage discrete time state-space modeling and showcase the approach in the power converter design process. The method is validated on a 48-to-1V converter designed using the proposed techniques.

This paper details a fully compensated self-resonant coil (FSRC) with series LC resonance and reduced surface electric field for application in wireless power transfer for consumer electronics. By having a repeated series LC connection along the entire coil trace, the proposed series resonant structure achieves high-Q, low E-field, and thin profile simultaneously. The impact of ferrite shielding is also studied. Different E-field compensation coil geometries are studied, and a systematic design method is presented for optimal coil performance. Experimental tests verify the coil function, modeling, and design.

This article presents the weight optimization of a receiver for wireless drone charging applications. There is need for comprehensive modeling to minimize the onboard weight on the flying drone platform. A systematic approach that codesigns all stages of the wireless charger, based on comprehensive loss, weight, and thermal modeling, is put forward to minimize the onboard weight for drone wireless charging applications. A 200 W, GaN-based prototype is implemented to validate the modeling. The prototype has been tested up to 204 W without any active cooling. The receiver achieves a gravimetric power density of 8.3 W/g excluding the weight of connectors, sensing, and control. Index Terms-Wireless power transfer (WPT), power density, synchronous rectifier.

Integrated chargers have gained an increasing interest in the electric vehicle (EV) industry. Existing solutions such as the integrated onboard charger (OBC) and auxiliary power module (APM) save the cost and the size, however, it only provides limited functions and hard to be integrated with the future wireless power transfer (WPT) technology. This paper proposed a multi-function magnetic coupler-based integrated charger that provides bidirectional OBC, WPT charging, and APM functions in a single system. In addition to the multi-port converter topology, a multi-winding WPT charging pad is repurposed serving as the main transformer in the OBC and APM modes as well. The paper briefs the system topology, explains various charging modes, and details the magnetic coupler design. Furthermore, a prototype was constructed and successfully delivered 6.6kW in OBC mode, 3.3kW in V2L mode, 6.6kW in WPT mode, and 800W in APM mode, which validates the proposed design.

This paper, to the best knowledge of the authors, for the first time reports the packaging of a 100kW three-level active neutral point clamped (3L-ANPC) phase leg power module for electric vehicle (EV) traction inverter applications using 650V/150A e-mode gallium nitride high-electron-mobility transistors (GaN HEMTs). Compared with two-level (2L) half bridge power module, the main challenges of packaging a 3L-ANPC phase leg power module are high number of switches (6 switches vs 2 switches) and multiple commutation loops (1 commutation loop vs 4 commutation loops). In addition, there are four switches involved in the two long commutation loops. Those parasitic loop inductances must be minimized simultaneously. Those challenges are addressed by meticulous packaging of the power module, featuring low power loop inductances, double-sided cooled power module, low junction-to-coolant thermal resistance, symmetrical layout for the two parallel dies of each switch and mechanical robustness, etc. The simulated loop inductances are 1.92nH for the short loops and 5.21nH for the long loops, respectively; resulting in a 471V and 540V of turn-off voltage spikes in a double pulse test simulation at 400V/200A. The simulated junction-to-coolant thermal resistances are 0.37°C/W and 0.53°C/W for different switches, respectively.

To build an integrated battery charger with multiple functions for electric vehicles (EVs), the system normally has several stages, such as AC/DC power factor conversion (PFC) converter, isolated and/or non-isolated DC/DC converters. Therefore, it is important to implement the start-up and shutdown procedure by coordinating multi-stage converters to avoid potential large inrush current or over voltage. This paper firstly proposed a highly integrated multi-stage battery charger for electric vehicles that offers multiple functions, including on-board charger (OBC), vehicle-to-load (V2L), wireless power transfer (WPT), all using a 400V battery, and auxiliary power module (APM) for a 12V battery. The control methods for each function are introduced. Based on the system configuration and characteristics of different functions, comprehensive system-level start-up and shut-down schemes are proposed for practical operation scenarios of OBC, WPT and V2L. Finally, a 400VAC/800VDC/22kW prototype is built and the effectiveness of the proposed start-up and shut-down schemes is verified by experiments.

As inductive wireless charging reaches higher power levels, thermal management and mechanical durability become more critical. To address these concerns, past works have demonstrated the benefit of encapsulating coil assemblies in thermally conductive materials. However, due to the sensitivity of the MnZn ferrites commonly used in coil assemblies to mechanical stress, care must be taken to avoid creating large stresses in the ferrite that cause higher hysteresis loss. The stress formation in the encapsulant curing process is overviewed and modeled and an experiment is performed to demonstrate the effect in a small-scale coil assembly. Finally, the effect is shown in the reduced coil-coil efficiency of a first generation high power inductive power transfer prototype using a stiff epoxy compared to better performance in a second prototype using a softer thermally-conductive silicone encapsulant.

This paper proposes a high-efficiency single-phase GaN-based T-type totem-pole front-end rectifier with reactive power transfer. A full-range zero voltage switching (ZVS) modulation approach for both unity power factor (PF) operation and non-unity PF operation is proposed for the GaN-based rectifier in critical conduction mode (CRM) operation. T-type mode operation and switching frequency limitation are proposed to overcome the ac-line zero-crossing challenges. A digital-based control strategy is also proposed to regulate the active power and reactive power simultaneously. A 1.6 kVA prototype of the T-type totem-pole rectifier is built and demonstrated with full-range ZVS operation, 98.9% full-load efficiency, and flexible reactive power regulation.

Schematic-level optimization and steady-state loss modeling play a vital role in the design of advanced power converters. Recently, discrete time state-space modeling has shown merits in rapid analysis and generality to arbitrary circuit topologies but has not yet been utilized under rapid optimization techniques. In this work, we investigate methods for the incorporation of rapid gradient-based optimization techniques leveraging discrete time state-space modeling and showcase the utility of the approach for use in the converter design process.

An investigation of a resonant reactive shielding coil for wireless power transfer (WPT) systems is presented in this work. The shielding coil attenuates the magnetic field above and to the side of air-core WPT coils. A parameterized coil model is used to allow arbitrary circular winding geometry and current direction. Detailed modeling and mathematical calculations are provided, and an optimized design algorithm is proposed. The design method is validated using an experimental prototype shielding coil applied to a 3.03 MHz electric vehicle (EV) WPT system operating at 500 W output power. Experimental results show that the peak flux density on the top-center area of the coil is suppressed from 105 μT to 50 μT, and the magnetic field to the side of the vehicle is maintained well below the safety standard. In addition, effect of the shielding coil in WPT systems with metal and ferrite plates is investigated.

Active rectifiers enhance WPT systems via tunability, high efficiency, and low waveform distortion. However, utilizing these benefits requires that two circuit characteristics are managed simultaneously: the switching frequency must be synchronized to the transmitter and the output must be regulated. Furthermore, the fundamental benefit of impedance tunability inherent to the active rectifier necessitates that this dual-objective control problem remains stable over a wide range of operating points. Either control loop can be designed in isolation, and under this premise, this work contributes a closed form derivation for the cross-coupling behaviors in the control architecture for a 7-level switched capacitor WPT system. Finally, regions of attenuated cross-coupling effects are identified and used to experimentally demonstrate wide-range control with stable output regulation and frequency synchronization.

Power electronic inverters for photovoltaic (PV) systems over the years have trended towards high efficiency and power density. However, reliability improvements of inverters have received less attention. Inverters are one of the lifetime-limiting elements in most PV systems. Their failures increase system operation and maintenance costs, contributing to an increased lifetime energy cost of the PV system. Opportunities exist to increase inverter reliability through design for reliability techniques and the use of new modular topologies, semiconductor devices, and energy buffering schemes. This paper presents the implementation and design for reliability for a GaN-based single-phase residential string inverter using a new topological and control scheme that allows dynamic hardware allocation (DHA). In the proposed inverter architecture, a range of identical modules and control schemes are used to dispatch hardware resources within the inverter to variably deliver power to the load or filter the second harmonic current on the DC side. This new approach more than triples the lifetime of GaN-based inverters, reducing system repair/replacement costs, and increasing the PV system lifetime energy production.

In paralleled three-phase three-level voltage source inverters, sometimes the currents of paralleled inverters need to be separately adjusted to control power sharing, and the reference vectors will differ in phase and amplitude. In other cases, although the current references of the paralleled inverters are set to be the same, the d-axis and q-axis current closed-loop control outputs of each converter cannot be exactly the same due to the asymmetry in hardware or software. As a result, the reference vector of each inverter may also be different in terms of phase and amplitude. When conventional three-level space vector pulse width modulation (SVPWM) is applied, periodical jump can be observed in the phase current of each inverter and the zero sequence circulating current (ZSCC). This paper investigates the current jump phenomenon in paralleled three-level inverters with space vector modulation (SVM). The mechanism that causes the current jump is illustrated. A modulation method to eliminate this current jump is proposed. Simulation and experimental results are presented to verify the effectiveness of the proposed method and conducted analysis.

This paper presents the modeling and analysis of zero common-mode voltage (ZCMV) pulse width modulation with dead-time for three-level voltage source inverters. Analytical model to calculate phase output voltage harmonic of three-level inverter with ZCMV modulation is developed. With ZCMV modulation, the common-mode voltage (CMV) of a three-level inverter can be eliminated in theory. However, CMV reduction performance is limited by dead-time in practical applications. Hence, the harmonic characteristics of CMV is modeled and analyzed considering dead-time. Experiments are conducted on a three-level neutral point clamped inverter with ZCMV modulation, and verify the accuracy of developed models.

This paper presents the design of a transmitter coil with an interleaved structure for multi-load wireless power transfer (WPT) applications covering a large charging area. The proposed coil achieves receiver positional flexibility, low electric field generation, and high efficiency. Analytical modeling of the coil magnetic field distribution, electric field generation, and power loss is presented and utilized in the coil design process. A prototype 0.5 m x 0.5 m transmitter coil is built and tested in a 6.78 MHz WPT system. The magnetic field is uniform across the entire charging are with less than 8% variation in amplitude. The overall system efficiency is 92.8% when loaded with two 50 W diode rectifiers.

Steady-state modeling plays an important role in the design of advanced power converters. Typically, steady-state modeling is completed by time-stepping simulators, which may be slow to converge to steady-state, or by dedicated analysis, which is time-consuming to develop across multiple topologies. Discrete time state-space modeling is a uniform approach to rapidly simulate arbitrary power converter designs. However, the approach requires modification to capture state-dependent switching, such as diode switching or current programmed modulation. This work provides a framework to identify and correct state-dependent switching within discrete time state-space modeling and shows the utility of the proposed method within the power converter design process.

Wireless power transfer (WPT) systems for Electric Vehicles (EVs) are designed to meet specifications such as stray field, power transfer, efficiency, and ground clearance. Typical design approaches include iterative analysis of predetermined coil geometries to identify candidates that meet these constraints. This work instead directly generates WPT coil shapes and magnetic fields to meet specifications and constraints through the optimization of Fourier basis function coefficients. The proposed Fourier Analysis Method (FAM) applies to arbitrary planar coil geometries and does not rely on iterative finite-element analysis (FEA) simulations. This flexibility allows for rapid design evaluation across a larger range of coil geometries and design specifications. A prototype coil is built to compare FAM outputs to experimental measurements and FEA simulations. The FAM is then used to illustrate the tradeoff of coil current and stray field for a given power level showing that the method is capable of generating optimized coil shapes to meet arbitrary field constraints.

In wireless power transfer (WPT) applications, the multi-level switched capacitor topology achieves significant advantages in terms of efficiency, system loading, THD, and output regulation. The topology requires dual-loop control in order to harness these benefits. First, a small signal discrete time model for the 7-level rectifier WPT system is developed. Then, a control loop is designed that enables the rectifier to regulate DC load voltage by varying its modulation scheme. Next, the WPT carrier frequency is sensed and a phase-locked loop is used in combination with the small signal power stage model to design a closed-loop controller that synchronizes frequency and regulates control phase through adjustments of the switching period. Finally, cross-coupling interactions between the two control loops are modeled, and stable dual-loop operation is shown.

In this paper, an automated controller for an integrated, reconfigurable dc-dc converter for plugin electric vehicles (EVs) is presented. The integrated converter combines both an interleaved boost converter and dual active bridge (DAB) converter, sharing magnetics and switching devices. The converter switches between operating modes using the existing battery management system (BMS) contactors. The integrated converter operates in isolated DAB mode during battery charging operation. During traction operation, the integrated converter is operated in interleaved boost mode for heavy load and DAB mode during light load, high voltage operation. An online transition algorithm is used to transition from interleaved boost mode to DAB mode with minimal bus distortion. The automated controller selects the operating mode and inverter bus voltage at different torque-speed conditions to get maximum overall traction drive efficiency. An experimental prototype of the integrated converter demonstrates the automated controller functionality.

In wireless power transfer systems, active rectifiers demonstrate improved efficiency and regulation capability. To enable impedance or output regulation, ensure stable operation, and maximize the efficiency, switching actions of the rectifier have to be synchronized with the magnetic field generated from the transmitter coil. This work presents an implementation of a phase- locked-loop synchronization controller using commercial components, including a low-cost microcontroller. A discrete-time small-signal model is used to derive the transfer function of the inherent feedback and design a compensator stabilizing the synchronization loop. Large-signal state-space modeling is used to design a high-efficiency, soft-switching, 6.78MHz power stage. A low-profile, 40W, GaN-based rectifier prototype is designed and built to experimentally verify the ability to synchronize and achieve high efficiency due to soft-switching.

A high power, high frequency wireless power transfer system for EV applications is proposed in this paper with lightweight and compact coil design. Leveraging a multi-layer non-uniform self-resonant coil, no external capacitor is needed for compensation and the high frequency conduction loss is mitigated by sharing current between multiple copper layers. Prototype coils with 200 mm radius are fabricated and tested, achieving quality factor over 450 at 3 MHz. The optimized design for both coils and a GaN-based power stage are detailed and validated experimentally. Experimental tests show 93.2% dc-dc efficiency with 2.4kW transferred across a 100 mm air gap.

The soft-switching gallium-nitride (GaN) based critical conduction mode (CRM) totem-pole power factor correction (PFC) converter is a good candidate for the front-end rectifier in wireless power transfer (WPT) applications. In multi-receiver MHz WPT systems, the PFC converter is required to have fast dynamic response and noise immunity. In this work, a GaN-based CRM totem-pole PFC converter is designed for a multi-receiver wireless charging power supply. Digital-based variable on-time control is used to achieve the zero voltage switching (ZVS) within the whole line cycle, and a voltage-loop controller with notch filters is designed to improve the transient response. The impact of high-frequency noise on the sensing signals and ZVS control are analyzed, and implementation methods are proposed to mitigate the disturbances. A GaN-based CRM totem-pole PFC that is demonstrated with 98.5% full-load efficiency is built as the first stage in the transmitter of a 100 W 6.78 MHz multi-receiver WPT system. The noise immunity of the CRM PFC is verified by testing the whole WPT system. Experimental results show that the system end-to-end efficiency at full load is 90.16%, and fast dynamic response is achieved during load variation.

Modeling plays a vital role in the design of advanced power converters. Commonly, modeling is completed using either dedicated hand analysis, which must be completed individually for each topology, or time-stepping circuit simulations, which are insufficiently rapid for broad analysis considering a wide range of potential designs or operating points. Discrete time state-space modeling of switching converters has shown merits in rapid analysis and generality to arbitrary circuit topologies but is hampered by difficulty incorporating nonlinear elements. In this work, we investigate methods for the incorporation of nonlinear elements into a generalized discrete time state-space modeling framework and showcase the utility of the approach for use in the converter design process.

Zero voltage switching (ZVS) has been widely implemented to improve the efficiency and robustness of high switching frequency converters. However, once the converter loses ZVS, the abrupt increase in switching loss decreases efficiency and may damage the converter. In this paper, a voltage slope-based detection method is proposed to detect ZVS status and prevent the converter from continuously hard switching. This detection circuit converts the voltage slope of the switching node to a dc voltage, which is compared with a reference voltage for the ZVS criterion. When hard switching occurs, two actions can be chosen: either shutting down the converter or adjusting the dead time to regain ZVS. The detection is achieved with simple circuitry and little control effort. A 6.78 MHz inverter for WPT application is used to verify this detection method. Experimental results show that ZVS status is detected effectively.

Active rectifiers in wireless power transfer systems exhibit many benefits compared to diode rectifiers, including increased efficiency, controllable impedance, and regulation capability. To achieve these benefits, the receivers must synchronize their switching frequency to the transmitter to avoid sub-fundamental beat frequency oscillations. Without additional communication, the receiver must synchronize to locally-sensed signals, such as voltages and currents induced in the power stage by the transmitter. However, the waveforms in the receiver are dependent on both the transmitter and receiver operation, resulting in an internal feedback between sensing and synchronization which prohibits the use of traditional phase-locked-loop design techniques. In this digest, a discrete time state space model is developed and used to derive a small signal model of these interactions for the purpose of designing stable closed-loop synchronization control. A prototype 150 kHz wireless power transfer converter is used to experimentally validate the modeling, showcasing stable synchronization.

A multi-layer non-uniform self-resonant coil is proposed in this paper for wireless power transfer applications. Multiple layers of spiral coils are stacked up, and the capacitance between them is controlled by a dielectric material between the copper layers. The coil current is shared among all layers, and the current sharing ratio is determined by the variable-width spiral tracks. Compared with a two-layer self-resonant coil, current sharing across the multi-layer structure reduces total copper loss. The analytical model for the proposed coil is provided and used to optimize the design of the coil. Both finite-element simulation and prototype testing of a three-layer design are used to validate the model. The results confirm the predicted high quality factor series resonant behavior.

Data center energy usage is expected to grow in the coming years with the proliferation of cloud services on daily life. The increasing energy demands that data centers will place upon the power grid necessitate the development high efficiency, high power density power supplies. The LLC resonant converter has long been utilized for data center power supplies as the dc-dc transformer to step down the voltage rectified from the ac transmission system to the rack level. As more is demanded of the data center and more information must be processed, space becomes more valuable. The use of wide bandgap materials such as Gallium Nitride (GaN) allows for much faster switching which can lead to higher power density by reducing the size of passive components. However, a higher frequency can lead to much greater switching loss. Zero-voltage switching (ZVS) can be utilized in primary side devices to greatly reduce losses. The achievement of ZVS is dependent on the magnetic design of the LLC transformer. By considering the effects of device capacitance and transformer parasitic capacitance and inductance, ZVS can be achieved to negate the turn-on losses and ensure high efficiency. This paper details the analysis of ZVS for a GaN-based LLC resonant converter with two series-parallel connected transformers.

In this paper, a variable frequency soft-switching control for a three-level half bridge (TLHB) buck converter is proposed to achieve wide-range output battery charging function without losing zero voltage switching (ZVS) or high efficiency. The adopted variable frequency triangle-current-modulation (TCM) is based on dc measurement and average-model calculation, thus able to realize ZVS operation fully digitally without current zero-crossing-detection (ZCD) circuits. A top-level average current or output voltage feedback controller further ensures the desired power or output voltage regulation. Experimental results from a GaN based TLHB prototype have shown the reliable TCM control and smooth transition of ZVS operation through the charging procedure.

An analytical model for the device drain-source turn-on overvoltage in three-level active neutral point clamped (3L-ANPC) converters is established in this paper. Considering the two commutation loops in the converter, the relationship between the turn-on overvoltage and the loop inductances is evaluated. The line switching frequency device usually exhibits higher overvoltage, while the high switching frequency device is not strongly influenced by the multiple loops. A 500 kVA 3L-ANPC converter using SiC MOSFETs is tested, and the model is verified with the experimental results.

In order to enable wireless charging of mobile electronics to compete with wired alternatives, wireless receivers need to operate at power levels sufficient to accommodate fast-charging standards. The receiver efficiency, harmonic content and total volume are key design metrics for wireless receivers. In this paper, four candidate topologies are compared, under 20 W fast-changing conditions, with respect to power loss, harmonic distortion, and power density. Each of the metrics are analyzed and verified experimentally. In coordination with the transmitter, a system-level approach to minimizing distortion is presented. Finally, the multilevel switched-capacitor rectifier is demonstrated to be a good candidate for wireless fast charging of mobile devices with high efficiency, small size, and suitable structure for future integration.

In paralleled voltage source inverters (VSI), circulating current has both high frequency and low frequency components, and its spectrum highly depends on the modulation scheme. Previous research has mostly focused on the circulating current suppression for paralleled two-level VSIs. Little literature exists on similar analysis for paralleled three-level VSIs using space vector modulation. A detailed circulating current spectrum on full frequency range has not been well developed. This paper presents an improved analytical model for three-level space vector modulation (SVM), considering the impacts of regularly sampled reference and dead time. Then, circulating harmonic currents are determined across the full frequency range for various interleaving angles of two three-level ANPC inverters. The calculated harmonics are also verified by experimental results.

Control based modulation techniques such as Boundary Current Mode (BCM) modulation are used to achieve zero voltage switching (ZVS) and overcome the increased switching losses in power electronics operating at high frequency. A simple control approach to implementing BCM uses dual current programmed mode (DCPM) control, but this approach is highly susceptible to noise and propagation delays at high switching frequency. Propagation delays in the control network cause the inductor current to overshoot its reference by a margin which varies with the instantaneous inductor current slope. This overshoot results in increased losses and introduces low-frequency inductor current distortion, particularly in high switching frequency converters. This work addresses propagation delay challenges by tuning the current sensing circuitry to mitigate impact of sensing delay, resulting in an inherent cancellation of sensing delay without additional control complexity. This approach is simple to implement and offers a flexible current control design for BCM modulation. The operation of this proposed compensation technique is demonstrated experimentally in a GaN-based full bridge inverter.

With conventional voltage source gate drives (VSG), the switching speed of SiC MOSFETs is difficult to increase due to large internal gate resistance, high Miller voltage, and limited gate voltage rating. This paper analyzes the requirement of current source gate drive (CSG) for SiC MOSFETs and proposes a CSG that can improve the switching speed and reduce switching loss. With the introduction of bi-directional switches, the influence of the large internal gate resistance of the SiC MOSFET can be mitigated, and sufficient gate current can be guaranteed throughout the switching transient. Therefore, the switching time and loss is reduced. The CSG can be controlled to be a VSG during steady state so the current of the gate drive is discontinuous and the stored energy of the inductor can be returned to the power supply to reduce gate drive loss. Double pulse tests are conducted for a SiC MOSFET with both conventional VSG and the proposed CSG. Testing results show that the switching loss of the proposed CSG is less than one third of the conventional VSG at full load condition.

High power inverters will be a key enabler for future aircraft based on hybrid electric or turbo-electric propulsion as envisioned by NASA and Boeing. Cooling a power electronics converter to low temperature, e.g. using cryogenic cooling, can significantly improve the efficiency and power density of a power conversion system. This paper presents the design of a MW cryogenically-cooled power inverter for electric aircraft applications. The power semiconductor and magnetic component characterization, inverter topology and power stage design, modulation and control, EMI noise reduction and filters design, and cooling system design are illustrated. A MW-level inverter prototype has been assembled and tested. The experimental results verify the functionality of the inverter.

Paralleling power electronics inverters is an effective way to increase dc-ac system power level. Accurately synchronized switching action and independent closed-loop regulator are necessary to prevent circulating current in paralleled inverters. There are many challenges for the controller design, when the number of paralleled inverters is large, and control period gets short for high switching frequency applications. This paper presents a single controller design based on DSP + FPGA that is suitable for paralleling multiple inverters. A simple synchronization scheme between DSP and FPGA based on universal parallel port (UPP) is proposed to eliminate the synchronization delay among inverters, and independent control of each converter can also be implemented. The controller is built for a system consisting of 4 paralleled three-level, three-phase high frequency ANPC inverters using space vector modulation, and it can be easily adopted to other topologies and modulations. Experimental results have demonstrated the effectiveness of this controller.

The adoption of SiC devices in high power applications enables higher switching speed, which requires lower circuit parasitic inductance to reduce the voltage overshoot. This paper presents the design of a busbar for a 500 kVA three-level active neutral point clamped (ANPC) converter. The layout of the busbar is discussed in detail based on the analysis of the multiple commutation loops, magnetic canceling effect, and DC-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. The results match with each other, and the inductances of small and large loop are 6.5 nH and 17.5 nH respectively, which is significantly lower than the busbars of NPC type converters in other references.

High-frequency soft-switched gallium-nitride (GaN) based critical conduction mode (CRM) totem-pole power factor correction (PFC) converter is one of the most potential candidates in data center power supplies. However, the high-speed cycle-by-cycle zero current detection (ZCD) brings challenges to zero-voltage-switching (ZVS) control. Current sensing delay (CSD) exists, and the ZCD circuit is sensitive to high di/dt switching noise. In this paper, mechanisms of the ZCD time error are elaborated, and impacts of the current sensing delay on converter switching frequency, inductor current, input current third harmonic distortion (THD), and power loss are analyzed. Qualification time is added within the controller for immunity to the swiching noise, and a CSD embedded converter model is proposed to compensate the ZCD time delay. Also, loss modeling of the CRM totem-pole PFC is conducted to aid in analysis of the proposed theory. A 1.5 kW single-phase CRM totem-pole PFC prototype is tested. Experimental results validiate the analysis, modeling, and the proposed compensation method for current sensing delay.

The four-leg topology has been applied to two-level inverters for common-mode (CM) noise elimination. To achieve zero common-mode voltage (CMV), the zero vector typically used in the two-level inverter is not allowed. As a result, the reference cannot be synthesized by nearest three vectors, which introduces a penalty in dc voltage utilization and current THD. This paper applies the fourth-leg to three-level neutral point clamped (NPC) inverter fed motor drives. Unlike the case in the two-level inverter, the reference can be synthesized by the nearest three vectors while zero CMV can be achieved at the same time in a three-level inverter with the fourth-leg. The topology and modulation are presented. The fourth-leg filter structures are investigated, and a fourth-leg filter structure which decouples the fourth-leg from the main circuit power level is proposed for high power applications. The experiment results on a three-level NPC inverter show that with the fourth-leg and presented modulation applied, the CM noise has been significantly reduced, and around 25 dB attenuation can be observed at the first noise peak in the electromagnetic interference (EMI) frequency range.

This paper presents the design and implementation of a boundary current mode (BCM) modulated GaN-based single phase inverter using a combination of bipolar and unipolar switching. Both unipolar and bipolar BCM-switched full bridge inverters are explored in detail in the context of efficiency, output current distortion and leakage current. Although the unipolar switched BCM inverter results in a higher efficiency in comparison to the bipolar switched inverter, it leads to a higher output current distortion at the low frequency zero crossing. On the other hand, the bipolar switched BCM inverter yields a low leakage current and reduced output current distortion, but exhibits lower efficiency. To overcome the low frequency zero crossing current distortion while maintaining a high efficiency, a combination of bipolar and unipolar switching in a BCM inverter is proposed. An experimental prototype has been built to validate the proposed control technique and modulation scheme. The proposed approach achieves a 2% efficiency improvement in comparison to the standard bipolar switched BCM inverter and a THD of 1.15%.

This paper details the inductor design and zero-voltage-switching (ZVS) control of a single-phase GaN-based critical-conduction-mode (CRM) totem-pole rectifier with power factor correction (PFC). A full-line-cycle ZVS strategy is derived, and an analytical converter model with ZVS margin is proposed. The boost inductor design is critical for the operation performance of the CRM totem-pole PFC. Based on analytical loss models, the inductor is designed and implemented using a toroidal powder core and litz wire to minimize converter loss and inductor size. Digital on-time control with real-time calculation and zero current detection (ZCD) is used to implement CRM. A 1.5 kW single-phase GaN-based CRM totem-pole PFC prototype is built and tested. With the on-time control, both the inductor current and the output voltage are well regulated. ZVS is realized for the whole line cycle, and the tested efficiency is 98.8% at full load.

This paper presents a comprehensive analytical analysis of the ac and dc side harmonics of the three-level active neutral point clamped (ANPC) inverter with space vector modulation (SVM) scheme. An analytical model to calculate the harmonics of a three-level converter with SVM is developed. The ac side output voltage harmonics and dc side current harmonics characteristics are calculated and analyzed. With the developed models, the impact of interleaving on both sides harmonics are studied which considers the modulation index, interleaving angle, and power factor. The analysis provides guideline for interleaving angle optimization to reduce the ac side power filter and dc side dc-link capacitor. The relationship between electromagnetic interference (EMI) filter corner frequency and switching frequency is also analytically derived which provides guideline for switching frequency and EMI filter design optimization. Two paralleled three-level ANPC inverters are constructed and experimental results are presented to verify the analytical analysis.

With the development of wide band-gap (WBG) technology, the switching speed of power semiconductor devices increases, which makes circuits more sensitive to parasitics. For three-level active neutral point clamped (3L-ANPC) converters, the over-voltage caused by additional non-active switch loop can be an issue. This paper analyzes the multiple commutation loops in 3L-ANPC converter and summarizes the impact factors of the device over-voltage. The nonlinearity of the output capacitance of the device can significantly influence the over-voltage. A simple control without introducing additional hardware circuit or complex software algorithm is proposed to attenuate the effect of the nonlinear output capacitance. Multi-pulse test is conducted for a 3L-ANPC converter built with silicon carbide (SiC) MOSFETs. With the proposed control, the testing results show that the peak drain-source voltage of both active and non-active switches is reduced by more than 20% compared to the conventional control.

This paper presents the coupled inductor design for interleaved three-level active neutral point clamped (ANPC) inverter considering electromagnetic interference (EMI) noise reduction. Compared to two-level case, the scenarios involved in the three-level space vector modulation (SVM) are more complicated when analyzing the volt-seconds of the coupled inductor for paralleled three-level inverter. At system level, the purpose of converter interleaving is to reduce EMI noise and ripple current in most applications, and coupled inductor design should consider the needs of EMI noise reduction and EMI filter design. These issues are discussed in this paper. The relationship between circulating current and EMI noise is illustrated. EMI filter corner frequency as a function of interleaving angle is analytically derived, and optimal interleaving angle for maximum common-mode (CM) filter and differential-mode (DM) filter corner frequencies is discussed. Coupled inductor design methodology for interleaved three-level inverters with SVM is then presented. Experiments on two interleaved ANPC inverters are conducted. The results verify the coupled inductor design. With the derived optimal interleaving angle, the CM and DM EMI noise are significantly reduced.

This paper presents harmonic analysis of common-mode reduction (CMR) modulation for three-level voltage source inverters. The analytical model to calculate the harmonics of CMR modulation with arbitrary PWM sequence is developed. The impact of alternative PWM sequences of CMR modulation on harmonics is investigated. New three-state and four-state PWM sequences of CMR are proposed which spread the energy centered in the carrier frequency in the conventional CMR, and thus reduce the voltage peaks in frequency domain. Experiments are conducted on a three-level neutral point clamped inverter. Experiment results verify the developed analytical model and harmonic analysis.

Wide bandgap (WBG) semiconductor devices and cryogenic cooling are key enablers for highly-efficient ultra-dense power electronics converters, which are critical for future more electric aircraft applications. For the development and optimization of a cryogenically-cooled converter, an understanding of power semiconductor characteristics, especially for emerging WBG devices, is critical. This paper focuses on WBG device characterization at cryogenic temperatures. First, the testing setup for cryogenic temperature characterization is introduced. Then several WBG device candidates (e.g., 1200-V SiC MOSFETs and 650-V GaN HEMTs) are characterized from room to cryogenic temperatures. The test results are presented with trends summarized and analyzed, including on-state resistance, breakdown voltage, and switching performance.

Automated vehicles require sensors and computer processing that can perceive the surrounding environment and make real time decisions. These additional electrical loads expand the auxiliary load profile, therefore reducing the range of an automated electric vehicle compared to a standard electric vehicle. Furthermore, a fully automated vehicle must be fail-safe from sensor to vehicle control, thus demanding additional electrical loads due to redundancies in hardware throughout the vehicle. This paper presents a review of the sensors needed to make a vehicle automated, the power required for these additional auxiliary loads, and the necessary electrical architectures for increasing levels of robustness.

A planar coil structure that exhibits a series self-resonant behavior is developed for wireless power transfer systems which use magnetic resonant coupling. The proposed structure uses two thin, planar, spiral tracks separated by one layer of dielectric. By connecting to alternate ends of each track, the coil shows a series LC impedance, which is often necessary for voltage source inverters. An analytical model for the inductance, capacitance and resistance is used to develop a geometric design method that minimizes resistance given a set of application constraints. Experimental coils made with an FR4 PCB and an Teflon-ceramic PCB verify the proposed structure and modeling.

Switching transient overvoltage is inevitable in hard switching applications, and the faster switching speed of SiC MOSFETs suggests even worse overvoltage. This paper focuses on the turn-on overvoltage. To understand its nature, the switching transient is analyzed, and it shows the turn-on overvoltage is largely independent of load current condition. This phenomenon is verified by characterizing the turn-on overvoltage of a SiC MOFET and a SiC Schottky diode. Finally, a SPICE-based model is also built to understand the switching transient more accurately, and the modeling method can accurately predict the turn-on overvoltage and help select device voltage rating.

In this work, a hybrid switched-capacitor/PWM converter is analyzed and designed for battery charging in mobile electronics. Operation of the converter is reviewed to construct a complete analytical loss model based on FET extracted parameters for an integrated circuit implementation. The model is validated with experimental results and compared with other converter topologies in the same application. The loss modeling is used to optimize the physical scaling of the power transistors to minimize total losses.

Dead-time, device output capacitance, and other non-ideal characteristics cause voltage error for the midpoint PWM voltage of the semiconductor phase-leg employed in a voltage-source inverter (VSI). Voltage-second balancing is a well-known concept to mitigate this distortion and improve converter power quality. This paper proposes a unique voltage-second balancing scheme for a SiC based voltage source inverter using online condition monitoring of turn-off delay time and drain-source voltage rise/fall time. This data is sent to the micro-controller to be used in an algorithm to actively adjust the duty cycle of the input PWM gate signals to match the voltage-second of the non-ideal output voltage with an ideal output voltage-second. The monitoring system also allows for this implementation to eliminate the need for precise current sensing and allows for the implementation to be load independent. Dynamic current sensing is still a developing technology, and each load has a unique effect on the output voltage distortion. Test results for a 1 kW half-bridge inverter implementing this monitoring system and voltage-second balancing scheme show a 70% enhancement on the error against the ideal fundamental current value of the output current and a 2% THD improvement on the output current low frequency harmonics.

This work examines the application of GaN within Class D audio by providing a side-by-side comparison of enhancement-mode GaN devices with currently available silicon MOSFETs with 60 V drain-to-source voltage ratings. GaN in Class D audio will allow for lower heat radiation, smaller circuit footprints, and longer battery life as compared to Si MOSFETs with a negligible trade-off for quality of sound.

In this paper, an extra junction capacitance and its associated switching commutation path are identified in three-level ac/dc converters, which were previously overlooked due to the off-state of the related device in half line cycle. The impact of this effect on power loss is analyzed, showing an underestimated switching loss in the traditional loss calculation of three-level converters. Through a proposed loss re-evaluation approach based on energy data of conventional double pulse tester (DPT), the corrected loss matches experimental results obtained from a 450kHz 650 V Gallium Nitride (GaN) based Vienna-type rectifier, showing 17.4% additional switching loss due to this effect. And the dominant extra switching loss is found to be Coss loss instead of overlap loss in WBG converters. Thefore, the effect is severe in high swtiching frequency high-speed wideband gap (WBG) based three-level converters.

A single-stage transmitter is reviewed which directly converts a utility ac input to high frequency (6.78 MHz) ac output for wireless power transfer applications. Compared with a two-stage transmitter implementation, this single-stage transmitter obtains high power efficiency with reduced component-count. In this paper, a method is proposed to enable constant current at the output of the single-stage transmitter to accommodate multiple receivers. First, the constant output voltage transmitter is obtained by implementing closed-loop control and a model-based modulation scheme. Then, an impedance matching network is implemented at the output of transmitter to convert the constant voltage to constant current. This feature allows a single transmitter to charge multiple receivers simultaneously. The control methodology is verified using both simulation and a laboratory prototype.

As wide bandgap (WBG) semiconductors are gradually adopted for high switching frequency high power-density power converter, new challenges arise from control to hardware design. In this paper, an improved input current sampling method is proposed for three-phase rectifiers to avoid sampling noises when rectifiers are operated at high speed and high switching frequency. Experimental results obtained from a 450-kHz enhancement-mode Gallium Nitride (GaN) high-electron-mobility transistor (HEMT) based three-phase three-level Vienna-type rectifier demonstrate the good performance of the sampling method.

Data centers consume an ever-increasing amount of electricity because of the rapid growth of cloud computing and digital information storage. A high voltage point of load (HV POL) converter is proposed to convert the 400-VDC distribution voltage to 1-VDC within a single stage to increase the power conversion efficiency. A six-phase input series output parallel (ISOP) connected structure is implemented for the HV POL. The symmetrical controlled half bridge current doubler is selected as the converter topology in the ISOP structure. The full load efficiency is improved by 4% points compared with state of the art products. A voltage compensator has been designed in order to meet the strict dynamic voltage regulation requirement. A laboratory prototype has been built, and experimental results have been provided to verify the proposed HV POL with a single power conversion stage can meet the dynamic voltage regulation requirement for an on-board power supply with higher efficiency compared to the conventional architecture.

A single-stage transmitter is reviewed, which directly converts a utility ac input to high frequency (6.78 MHz) ac output for wireless power transmission. By integrating two stages (totem-pole PFC rectifier and full bridge inverter) into a single stage, the topology achieves high efficiency and reduced component count. In this paper, a simple auxiliary circuit is added to allow the single-stage transmitter to operate in two modes. At heavy load, the transmitter operates as a totem-pole rectifier with PFC and achieves low distortion of the input current. At light load, the circuit operates as a voltage-doubler rectifier (VDR), extending the ZVS range of the transmitter. As a result, hard switching is avoided and efficiency is improved at light load. This improved single-stage transmitter is verified by a 100 W, GaN-based laboratory prototype.

The call for higher power and larger spatial freedom has driven the operating frequency of wireless power transfer (WPT) systems into the MHz range. Previous system design methods focus on designing the coils to attain high quality factor while remaining resonant around the working frequency and subsequently designing switching circuit hardware and operating point to minimize the system power loss. This sequential design method over-simplifies the system, neglecting inter-dependencies between system components, which leads to suboptimal designs. This paper presents a system design method that co-optimizes coils, power stages, and circuit operation for maximum overall efficiency, based on accurate models of converters and WPT system. The system model and the importance of co-design are verified by a 6.78 MHz WPT prototype.

In mobile electronics applications, the high conduction loss on the ac-dc rectifier and the coil is a barrier to the application of wireless charging. In this paper, a wireless charging architecture employing a 7-level switched-capacitor (SC) ac-dc rectifier is investigated, showing a substantial reduction of the conduction losses on the transmitter, the coil and the receiver. The proposed SC rectifier also features a multilevel design with good scalability to accommodate different power ratings, and potentially reduce the harmonic contents of the input voltage. The principle and operation are verified using a 7-level, 20 W, 5-9 Vdc output, 150 kHz prototype. The measured peak dc-to-load system efficiency is above 90%. The high-power density design without bulky magnetic components is suitable for the implementation in low-profile mobile electronics.

Resonant magnetic wireless power transfer (WPT) has potential to improve spatial freedom, allow simultaneous charging of multiple devices, and increase circuit power density. However, many obstacles must first be overcome before the benefits of this technology are fully realized. Due to the high frequency of the WPT carrier, autonomous receiver-side synchronization and control presents significant difficulties. This work addresses the control strategy of a 6.78 MHz GaN-based synchronous WPT rectifier. A zero-crossing current sensing scheme is used to both synchronize the receiver switching frequency and to enable control of its input phase. The rectifier is shown to be capable of regulating its output voltage by changing its input phase, highlighting the value of a circuit that has real-time control over the reactive part of its input impedance. The current sensing, frequency synchronization, and input phase control capabilities of the circuit are demonstrated experimentally and discussed in detail.

Although SiC MOSFETs show superior switching performance compared to Si IGBTs, it is unknown whether SiC MOSFETs have the same advantage over Si super junction (SJ) MOSFETs such as CoolMOS. This paper analyzes the switching performance in different switching cell configurations and summarizes the impact factors that influence switching loss. A double pulse test is conducted for a SiC MOSFET and a CoolMOS with the same voltage and current rating. In the FET/diode cell structure, a SiC Schottky diode is used as the upper device to eliminate the reverse recovery, and the testing results show that the SiC MOSFET has 2.4 times higher switching loss than the Si CoolMOS. This can be explained by the smaller transconductance and the higher Miller voltage of the SiC MOSFET. On the other hand, the Si CooMOS has 10 times higher switching loss than the SiC MOSFET in the FET/FET cell structure because of the significant turn-on loss caused by the poor reverse recovery of its body diode.

Due to the low availability, high cost, and limited performance of high voltage power devices in high voltage high power applications, series-connection of low voltage switches is commonly considered. Practically, because of the dynamic voltage unbalance and the resultant reliability issue, switches in series-connection are not popular, especially for fast switching field-effect transistors such as silicon (Si) super junction MOSFETs, silicon carbide (SiC) JFETs, SiC MOSFETs, and gallium nitride (GaN) HEMTs, since their switching performance is highly sensitive to gate control, circuit parasitics, and device parameters. In the end, slight mismatch can introduce severe unbalanced voltage. This paper proposes an active voltage balancing scheme, including 1) tunable gate signal timing unit between series-connected switches with <; 1 ns precision resolution by utilizing a high resolution pulse-width modulator (HRPWM) which has existed in micro-controllers; and 2) online voltage unbalance monitor unit integrated with the gate drive as the feedback. Based on the latest generation 600-V Si CoolMOS, experimental results show that the dynamic voltage can be automatically well balanced in a wide range of operating conditions, and more importantly, the proposed scheme has no penalty for high-speed switching.

To overcome the increased switching losses in high frequency power electronics, control-based modulation techniques such as boundary current mode (BCM) are commonly used in full bridge inverter and rectifier topologies to guarantee zero voltage switching (ZVS). Traditionally, in order to implement BCM modulation, a combination of current programmed mode (CPM) control and model-based techniques are used. The former is highly susceptible to noise and sensing delay, while the latter is subject to modeling error. In this work, a dual-current programmed mode (DCPM) control circuit for BCM operation is designed and implemented. The proposed control network achieves better noise immunity and low propagation delay at high frequency while regulating peak and valley currents in each period. The operation of this control scheme is demonstrated experimentally using a GaN-based half bridge inverter prototype.

Understanding the CM inductor core saturation mechanism and reducing core flux density is critical for CM inductor design optimization. Instead of a time domain method, this paper introduces frequency domain spectrum concept for CM inductor core saturation analysis and design optimization, which will provide designers a better understanding of CM inductor design. First, both core permeability and converter modulation index's opposite influence on DM flux density and CM flux density are identified. Then, CM flux density is further investigated based on the spectrum concept. Three components in the CM inductor which may cause large CM flux density and core saturation are summarized: (1) switching frequency related components, (2) impedance resonance frequency related components, and (3) modulation frequency related components. Each component is investigated for CM flux density reduction and filter design optimization. A connecting AC and DC side midpoint with notch filter structure is proposed to reduce modulation frequency related components. Experiment results are presented to verify the proposed concept and method.

Attenuation performance of an EMI filter can be significantly degraded by coupling, parasitics, and frequency-dependent nonlinearity of magnetic cores. In this paper, the effect due to mutual capacitive coupling in filter structures with T-shape joint is identified and investigated. Its mechanism indicates that this coupling is the dominant cause of performance degradation in T-shape filters. PCB slits and grounded shielding are proposed as two effective mitigation solutions, respectively, and are further combined to improve filter transfer gain up to 40 dB along the high frequency range. Experimental results obtained from a three-phase LCL common-mode (CM) filter verify the significant impact of this coupling and the effectiveness of the proposed mitigation methods.

This paper presents a modeling approach for dual active bridge (DAB) converter in electric vehicle (EV) applications which considers the magnetizing inductance effect of the high-frequency transformer. A Typical DAB transformer has very high magnetizing inductance compared to the leakage inductance. As a result, the magnetizing current can be neglected. However, for integrated and hybrid converters, where the same core is used for both DC excitation and AC excitation, an air gap is used to prevent core saturation. In such applications, the effect of magnetizing inductance needs to be considered for DAB converter modeling. For accurate estimation of the DAB converter, a loss model considering magnetizing inductance is developed in this paper. Finite element analysis (FEA) is performed to model the transformer to evaluate the proximity loss and fringe induced eddy current loss mechanisms. An experimental prototype of the DAB converter is developed to verify the proposed model. Experimental waveforms are presented and compared for different power level and switching frequency.

Superconducting technologies such as motors together with the supporting cryogenic power electronic system are growing in importance in aircraft applications. It is critical to understand the influence of low temperature on filters of the power converter system in these applications. Also, it is worthwhile to investigate whether the converter system can achieve higher efficiency and high power density by utilizing the provided low temperature cooling environment. This paper conducted a comprehensive magnetic core characterization at low temperature to understand the core properties and support filter design at low temperature. The ferrite and nanocrystalline material are characterized from room temperature to cryogenic temperature in a wide range of operating frequencies. The results show that the permeability of ferrite material decreases by a factor of 7~8 and the core loss increases more than 10 times when operating at very low temperature. The permeability of nanocrystalline material decreases to 60% and the core loss increases 1.5~2.5 times when operating at very low temperature. The saturation flux density of both materials has slight increase at low temperature. Based on tested data, a case study of inductor design considering the low temperature cooling environment is presented to illustrate the influence of low temperature on inductor design.

To operate a converter at cryogenic temperatures, understanding the characteristics of power semiconductor devices is critical. This paper presents the characterization of state-of-the-art 1.2 kV SiC MOSFETs from leading manufacturers at cryogenic temperatures. The testing setup consisting of a cryogenic chamber, and a liquid nitrogen Dewar is introduced. With a curve tracer and double pulse test, comprehensive characterization of the SiC MOSFETs including both static and switching performance is conducted and evaluated. Test results indicate the on-resistance increases while the breakdown voltage remains relatively constant at cryogenic temperatures. Other characteristics like threshold voltage and switching loss vary significantly at cryogenic temperatures among devices from different manufacturers.

Zero sequence circulating current (ZSCC) exists when paralleled inverters have common dc and ac sides without isolation. Most of the prior work on the ZSCC analysis and suppression depended on paralleled two-level inverters. The scenarios involved in the three-level converters are more complicated. This paper investigates the ZSCC in paralleled three-level active neutral point clamped (ANPC) inverters. The mechanisms causing potential ZSCC jump in three-level paralleled ANPC inverters are analyzed. The ZSCC patterns of different interleaved modulation schemes for three-level converters are illustrated. Then, the active vector dividing concept is extended to three-level converters, and a modulation scheme is proposed to reduce the high frequency ZSCC in three-level converters. Experiments have been conducted on two paralleled three-level inverters. The current jump in ZSCC is observed and mitigated. The ZSCC with proposed modulation scheme is reduced to less than half of the ZSCC with conventional continuous space vector modulation (CSVM) scheme.

Unlike conventional passive or active filters, an impedance balancing circuit reduces the common-mode (CM) electromagnetic interference (EMI) noise by establishing an impedance balancing bridge. The EMI noise can be significantly reduced when the impedance bridge is designed to be well balanced. This paper investigates impedance balancing circuits in Dc-fed motor drive systems where both DC input and AC output need to meet EMI standards and thus EMI filters are needed for both sides. An impedance balancing circuit is proposed to reduce both DC and AC side CM noise. Two auxiliary branches are added to the conventional passive filters to establish an impedance bridge and reduce CM noise. The design criteria are presented, and the impact of the proposed impedance balancing circuit on both sides CM noise are investigated. It shows that the proposed impedance balancing circuit can reduce DC side and AC side CM noise based on different mechanisms. The CM noise reduction performance of the proposed method does not depend on the motor and cable models. Experiment results are presented to demonstrate the feasibility and effectiveness of the proposed method.

One of the popular converter topologies applied in high power dc-ac applications is the three-level active neutral point clamped (ANPC). Owing to relatively low switching frequency and slow switching speed of these topologies in high power applications, the commutation loop analysis in these topologies has not been fully conducted, and the over-voltage issue of non-active switches has not been thoroughly analyzed. This paper reveals an over-voltage issue on non-active switches in three level inverters due to multi-commutation loop. The detailed mode analysis during the commutation and related over-voltage issue are given. Finally, Si-based ANPC with 140 kHz switching frequency and SiC-based ANPC converters with 280 kHz switching frequency and high switching speed are tested respectively to compare and verify the over-voltage issue for non-active switches.

In order to evaluate the feasibility of newly developed GaN devices in a cryogenic-cooled converter, this paper characterizes a 650 V enhancement-mode Gallium-Nitride heterojunction field-effect transistor (GaN HFET) at cryogenic temperatures. The characterization includes two parts: static and dynamic characterization. The results show that this GaN HEMT is an excellent device candidate to be applied in cryogenic-cooled applications. For example, transconductance at cryogenic temperature is 2.5 times of one at room temperature, and accordingly, peak di/dt during turn-on transients at cryogenic temperature is around 2 times of that at room temperature. Moreover, the on-resistance of the channel at cryogenic temperature is only one-fifth of that at room temperature.

A new single-stage AC/RF converter is proposed which directly converts a utility AC input to a regulated, high frequency (6.78MHz) AC output for wireless power transmission. The topology integrates a totem pole rectifier operating in discontinuous conduction mode (DCM) and a phase-shift controlled full bridge inverter. Compared to traditional multi-stage approaches, the single-stage approach improves system power efficiency by reducing the number of cascaded conversion stages. In addition, the reduced power semiconductor component count will be a potential benefit for compact size and lower cost. A 100W laboratory prototype has been built to verify theoretical analysis. Experimental measurements show the capability of the converter to provide power factor correction (PFC) with high conversion efficiency and low total harmonic distortion (THD).

Battery charging circuits for mobile applications, such as smart phones and tablets, require both small area and low losses. In addition, to reduce the charging time, high current is needed through the converter. In order to reduce conduction losses, low on-resistance of the switches is necessary. However, specific resistance (resistance per unit area) is a strong function of the maximum voltage blocking capability of the transistors. To maintain high efficiency and ensure device reliability, the designed breakdown voltage of the transistors needs to include some margin to account for ringing on the switching node. Bond wires add inductance to the power loop increasing the overshoot voltage. In this work the design, implementation and testing of a 40 W CMOS integrated buck converter with an on chip decoupling capacitor are presented. The design was optimized for a 5V to 4V application with a maximum of 2 W on-chip losses at 10 A with an operating frequency of 1 MHz.

This paper introduces a dead-time optimization technique for a 2-level voltage source converter (VSC) using turn-off transition monitoring. Dead-time in a VSC impacts power quality, reliability, and efficiency. Silicon carbide (SiC) based VSCs are more sensitive to dead-time from increased reverse conduction losses and turn-off time variability with operating conditions and load characteristics. An online condition monitoring system for SiC devices has been developed using gate drive assist circuits and a micro-controller. It can be leveraged to monitor turn-off time and indicate the optimal dead-time in each switching cycle of any converter operation. It can also be used to specify load current polarity, which is needed for dead-time optimization in an inverter. This is an important distinction from other inverter dead-time elimination/optimization schemes as current around the zero current crossing is hard to accurately detect. A 1kW half-bridge inverter was assembled to test the turn-off time monitoring and dead-time optimization scheme. Results show 91% reduction in reverse conduction power losses in the SiC devices compared to a set dead-time of 500ns switching at 50 kHz.

In this paper, a control strategy of an integrated, reconfigurable DC-DC converter for plugin electric vehicles (EVs) is proposed. The integrated converter, capable of operating in both traction and charging modes, can be reconfigured as an interleaved boost or a dual active bridge (DAB) converter. The existing contactors of the battery management system (BMS) are used for reconfiguration between the boost and DAB modes. To maximize overall power conversion efficiency during traction operation, the converter is dynamically reconfigured to operate in the mode with highest efficiency at the present operating point. A switching transition control approach is developed for fast and seamless switching, ensuring zero-voltage turn-on and zero-current turn-off of the BMS contactors. The smooth transitions minimize switching-induced degradation of the BMS contactors, and allow uninterrupted power delivery during mode transitions. The experimental results of the prototype are presented to verify the functionality of the proposed control approach.

This work presents an analytical model for integrated DC-DC converters at high currents. A loss model is constructed using parameters extracted from simulation or are available in the process manual and are scaled with the size of the device. The loss model is used to compare power converter implementations for varying on-chip size and power loss goals. Buck, 3-Level Buck, and Switched-Capacitor topologies are compared using this analytical model and then implemented in a commercial CMOS process. Validation of the constructed loss model is done through hardware measurements.

While fast switching brings many benefits, it also presents unwanted ringing during switching transient. In this paper, an increasing magnitude ringing phenomenon is observed during the MOSFET turn-off transient. The unusual phenomenon is replicated in simulation and it is found the MOSFET channel is turned on again after it is turned off. The major cause to this unexpected turn on is found to be common source inductance and a moderate 3 nH one in simulation replicates the severe self-turn-on ringing observed in experiment. This paper reveals the detrimental effect of common source inductance in fast switching. Therefore, Kelvin source connection in circuit and package design is strongly recommended.

With the growth of magnetic resonance wireless power transfer (WPT), the WPT field sees a push toward higher operating frequencies. New challenges arise as the fundamental frequency increases, namely the relevance of circuit parasitics and the difficulty in preventing harmonic distortion. A 6.78 MHz synchronous rectifier is shown to address the issues of total harmonic distortion (THD) and dynamic loading. This work focuses on further modeling the proposed rectifier, accounting for parasitic conduction losses, THD, input phase control, and characterization of design trade offs. The updated model includes both an exact solution for the complete dynamics of the dead time resonance which, by design, has significant impact on converter harmonics, impedance, and power delivery. The model is compared to the simpler model from previous work and is verified via experimental results.

Concurrent dual-frequency ac outputs from a single-inverter configuration potentially benefit many industrial applications, such as induction heating and wireless power transfer. In this paper, a phase-shift dual-frequency selective harmonic elimination (DFSHE) method is proposed to simultaneously generate and regulate two ac outputs at different frequencies from a single full-bridge inverter, which expands the family of DFSHEs. With the phase shift operation, all triplen harmonics of the fundamental are inherently suppressed in the inverter output spectrum, which improves the output THD, and may ease filter design. In addition, an evaluation of the unipolar, bipolar and phase-shift DFSHE techniques is presented, which analyzes design tradeoffs for multi-frequency applications. Finally, experimental results from a 50 W dual-output inverter validate the effectiveness of the proposed method, which agree with theoretical predictions and simulation results.

Cooling a converter to low temperatures, e.g. using cryogenic cooling, can significantly improve the efficiency and density of a power conversion system. For the development and optimization of a cryogenically-cooled converter, an understanding of power semiconductor characteristics is critical. This paper focuses on the characterization of high-voltage, high-speed switching, power semiconductors at cryogenic temperature. First, the testing setup for cryogenic temperature characterization is introduced. Three testing setups are established for cryogenic switch characterization, including: 1) on-state resistance and forward voltage drop of the body diode, 2) leakage current and breakdown voltage, and 3) switching characteristics. For each testing set up, the corresponding testing configurations, hardware setups, and practical considerations are summarized. Additionally, the test results at cryogenic temperature are illustrated and analyzed for 650-V Si CoolMOS. It is then demonstrated that when the cryogenic temperature test results are compared to that of room temperature, the device performance varies significantly; for example: on-state resistance reduces by 63%, breakdown voltage drops by 31%, switching time decreases and switching energy loss decreases by 26%. Furthermore, the peak dv/dt during transient switching at cryogenic temperature exceeds 100 V/ns which is comparable to the emerging wide bandgap Gallium Nitride devices.

Wide bandgap (WBG) semiconductors owing to their low loss and high switching capability, are gradually adopted in high power-density high efficiency applications, and impose new challenges from control to hardware design. In this paper, a Gallium Nitride (GaN) HEMT plus SiC diode based Vienna type rectifier is proposed to serve as the power factor correction stage for a high-density battery charger system. To meet low current harmonic requirement, PWM voltage distortion during turn-off transition, found as the main harmonics contributor, is studied. The distortion mechanism led by different parasitic capacitances of WBG devices is presented. A mitigation scheme is thereafter proposed considering their nonlinear voltage-dependent characteristics and eventually deduced from a pulse-based turn-off compensation to a generic modulation correction. Simulation and experimental results through a 450 kHz enhancement-mode GaN based Vienna type rectifier finally demonstrate the high performance of the proposed approach, showing a THD reduction up to 7% with a relatively low-speed control.

This paper presents a method of optimizing low power boost converters for use in far-field wireless energy harvesting systems. This method uses a database of manufacturer-provided device characteristics of both Silicon and GaN FETs to construct Figures of Merit (FOMs) used for evaluating device technologies for power loss based on boost converter parameters. A loss model is constructed for predicting device power losses and system efficiency over a wide range of operating points. Using the analysis framework, an asynchronous boost converter is constructed and experimentally verified with operation as low as 10 μW with a peak efficiency of 74% at an input power of 300 μW.

The properties of silicon carbide (SiC) integrated circuit (IC) processes are discussed and nonlinear-carrier control is proposed as a controller topology that can work within the design challenges presented by SiC. A boost converter with NLC controller is demonstrated using circuit blocks built with SiC IC models.

Due to the realization of zero voltage switching (ZVS) under the full load range, LLC resonant converter is widely adopted in the telecom, battery charger and several applications, characterized with high efficiency, high frequency and high power density, to realize DC conversion. Recently, by using Gallium Nitride (GaN) HFETS, switching frequency of LLC converters is further increased. However, ZVS failure cannot be predicted accurately in the high switching frequency condition by only considering traditional constraints generally applied in the low frequency design. The traditional constraints result in a too optimistic estimation of the dead time to obtain ZVS without considering the reverse resonance under the dead time and the design of resonant parameters at high resonant frequency and high load condition. The experiment shows the LLC converter loses ZVS even through the converter satisfies the ZVS constraints proposed by previous paper. In this paper, the failure mode will be investigated in detail and an accurate ZVS boundary is proposed for high frequency LLC converter design. The proposed theory was verified on a 1 MHz, 1500 W LLC prototype.

Junction temperature is a critical indicator for health condition monitoring of power devices. Concerning the reliability of emerging silicon carbide (SiC) power semiconductors due to immaturity of new material and packaging, junction temperature measurement becomes more significant and challenging, since SiC devices have low on-state resistance, fast switching speed, and high susceptibility to noise and parasitics in circuit implementations. This paper aims at developing a practical and cost-effective approach for online junction temperature monitoring of SiC devices using turn-off delay time as the thermo-sensitive electrical parameter (TSEP). The sensitivity is analyzed for fast switching SiC devices. A gate impedance regulation assist circuit is designed to improve the sensitivity by a factor of 60 and approach hundreds of ps/°C in the case study with little penalty of the power conversion performance. Also, an online monitoring system based on three gate assist circuits is developed to monitor the turn-off delay time in real time with the resolution within hundreds of ps. In the end, the micro-controller is capable of “reading” junction temperature during the converter operation with less than 0.5 °C measurement error. Two testing platforms for calibration and online junction temperature monitoring are constructed, and experimental results demonstrate the feasibility and accuracy of the proposed approach. Furthermore, the proposed gate assist circuits for sensitivity improvement and high resolution turn-off delay time measurement are transistor based and suitable for chip level integration.

High speed switching of WBG devices causes their switching behavior to be highly susceptible to the parasitics in the circuit, including inductive loads. An inductive load consisting of a motor and power cable significantly worsens the switching speed and losses of SiC MOSFETs in a PWM inverter. This paper focuses on the motor plus power cable based inductive load, and aims at mitigating its negative influence during the switching transient. An auxiliary filter is designed and inserted between the converter and inductive load so that the parasitics of the load will not be “seen” from the converter side during the switching transient. Test results with Cree 1200-V/20-A SiC MOSFETs show that the proposed auxiliary inductor enables the switching performance with a practical inductive load (e.g., motor plus cable based inductive load) to exhibit behavior close to that when the optimally-designed double pulse test load inductor is employed.

This work examines the potential of a GaN-based synchronous rectifier as a receiver in 6.78 MHz wireless power transfer (WPT) applications. Compared to a traditional diode-based rectifier, the synchronous rectifier has merits in its additional control freedoms. The active control of switching actions can be used to alter impedance presented to transmitting source, or, when combined with a zero-voltage switching (ZVS) resonant tank, to reduce harmonics generated by the switching actions, and therefore mitigate requirements on the filter network to meet EMI limitations. Analysis of control and hardware design strategies to maximize efficiency, limit total harmonic distortion (THD), and control impedance at the WPT frequency are presented and verified on a prototype experimental platform.

Enhancement-mode GaN HFETs enable efficient high-frequency converter design, but this technology is relatively new and exhibits different characteristics from Si or SiC MOSFETs. GaN performance at elevated temperature is especially unique. Turn-on time increases significantly with temperature, and turn-on losses increase as a result. This phenomenon can be explained based on the relationships between junction temperature and GaN device transconductance, and between transconductance and turn-on time. An analytical relationship between temperature and turn-on loss has been derived for the 650-V GS66508 from GaN Systems, and verified with experimental results. Based on this relationship, a detailed model is developed, and a simplified scaling factor is proposed for estimating turn-on loss in e-mode GaN HFETs, using room-temperature switching characterization and typically published datasheet parameters.

Gallium Nitride (GaN) HFETS are an enabling technology for high-density converter design. This paper proposes a three-level dc-dc converter with dual outputs based on enhancement-mode GaN devices, intended for use as a battery charger in aircraft applications. The charger can output either 28 V or 270 V, selected with a jumper, which meets the two most common dc bus voltages in airplanes. It operates as an LLC converter in the 28 V mode, and as a buck converter in the 270 V mode. In both operation modes, the devices can realize zero-voltage-switching (ZVS). With the chosen modulation method, the converter can realize the frequency doubling function to act as an interleaved converter. For the LLC mode, the resonant frequency is twice the switching frequency of primary-side switches, and for buck mode, the frequency of the output inductor current is also twice the switching frequency. This helps to reduce the size of magnetics while maintaining low switching loss. Also, the converter utilizes the matrix transformer with resonant parameters designed to avoid ZVS failure. The operation principle of the converter is analyzed and verified on a 1MHz resonant frequency prototype.

Simultaneous generation of two AC outputs at different frequencies from a single-phase inverter offers practical benefits and control flexibility for many industrial applications. In this paper, a dual-frequency selective harmonic elimination (DFSHE) modulation method is proposed to generate and control two individual frequencies in an H-bridge, while diminishing undesired harmonics. Two AC elements are synthesized independently in the modulation scheme, and thus flexible individual power regulation is achieved via the proposed method. In addition, both unipolar and bipolar DFSHE cases are investigated. Characteristics of the two methods are compared and alternatives are provided for different applications. The generation algorithms of the DFSHE are also studied in this paper, and can be applied to a variety of DC/AC topologies without adding extra switching devices. Finally, the experimental results from a 100W dual-load single-phase inverter verify the effectiveness of proposed method, where 50 kHz and 450 kHz AC outputs are generated and individually regulated.

In this paper, a single stage system which converts 400 V to 1 V within one stage and performs as the high voltage point of load (HV POL) converter for data centers is proposed. A load dependent soft switching method has been proposed for half bridge current doubler with simple auxiliary circuit. The operation principles of the soft switching converter have been analyzed in detail. A lossless RCD current sensing method is used to sense the output current value to reduce the auxiliary circuit loss and turn off loss of secondary side devices as load reduces to achieve higher efficiency. Experimental efficiency has been tested to prove the proposed method can increase the converter's efficiency in both heavy and light load condition. A prototype of the half bridge current doubler circuit has been built to verify the theory.

In this paper, an integrated, reconfigurable DC-DC converter for plugin and hybrid Electric Vehicles (EV) is proposed. The converter integrates functionality for both EV powertrain and charging operation into a single unit. During charging, the proposed converter functions as a DAB converter, providing galvanic isolation. For powertrain operation, the converter functions as an interleaved boost converter. During light load powertrain operation, the efficiency of the converter can be further improved by employing the integrated DAB. The proposed integrated converter does not require any extra relays or contactors for charging and powertrain operation. By using such integration, the overall volume and weight of the power electronics circuits, passives and associated cooling system can be improved. In addition, the power flow efficiency from EV battery to the high voltage DC bus for the motor inverter can be improved. The experimental results of the prototype are presented to verify the functionality of the proposed converter.

In this paper, a triple active bridge converter is proposed. The topology is capable of achieving ZVS across the full load range with wide input voltage while minimizing heavy load conduction losses to increase overall efficiency. This topology comprises three full bridges coupled by a three-winding transformer. At light load, by adjusting the phase shift between two input bridges, all switching devices can maintain ZVS due to a controlled circulating current. At heavy load, the two input bridges work in parallel to reduce conduction loss. The operation principles of this topology are introduced and the ZVS boundaries are derived. Based on analytical models of power loss, a 200W laboratory prototype has been built to verify theoretical considerations.

Many intelligent gate drivers being designed for new state-of-the-art WBG devices typically only focus on protection and driving capabilities of the devices. This paper introduces an intelligent gate driver that incorporates online condition monitoring of the WBG devices. For this specific case study, three timing conditions (turn-off delay time, turn-off time, and voltage commutation time) of a silicon carbide (SiC) device are online monitored. This online monitoring system is achieved through gate driver assist circuits and a micro-controller. These conditions are then utilized to develop converter-level benefits for the converter application the SiC devices are placed in. Junction temperature monitoring is realized through turn-off delay time monitoring. Dead-time optimization is achieved with turn-off time monitoring. Dead-time compensation is obtained with turn-off time and voltage commutation time monitoring. The case study converter assembled for testing purposes is a half-bridge inverter using two SiC devices in a phase-leg configuration. All timing conditions are correctly monitored within reasonable difference of the actual condition time. A calibration curve was created to give a direct relationship between turn-off delay time and junction temperature. The half-bridge inverter can operate at 600 Vdc input and successfully obtain a junction temperature measurement through monitored td_off and the calibration curve. Furthermore, the proposed online condition monitoring system is transistor based and suitable for the chip level integration, enabling this practical approach to be cost-effective for end users.

A two-stage power conversion architecture for the transmitter in wireless power transfer applications is introduced. The system achieves high efficiency at output powers up to 100W, and exhibits constant output current over varying load impedance. A front-end bridgeless totem pole rectifier provides power factor correction (PFC), necessary at the designed power level. This rectifier achieves high efficiency by eliminating the conventional diode full bridge and by achieving soft switching operation. A full bridge inverter, switching at 6.78MHz, generates the AC output. Combined with an output passive filter network, the inverter achieves constant output current with load variation without the need for dynamic feedback control. A prototype system is constructed and tested experimentally to verify operation.

Multi-frequency wireless power transfer (WPT) is advantageous in facilitating compatibility with different WPT standards. However, implementing a multi-frequency transmitter often requires compromises in system size, complexity, power transfer capability, or output regulation. In this paper, a single-inverter based dual-mode WPT system is proposed. The system employs a multi-frequency programmed pulse width modulation (MFPWM) scheme. This dual-frequency modulated inverter can simultaneously generate and regulate 100 kHz and 6.78 MHz outputs, which facilitates the development of multi-standard WPT technology for consumer electronics. In addition, the principle of the proposed modulation is illustrated, where two different frequencies are concurrently modulated in the programmed pulse train of square waveforms, while eliminating certain harmonics in between. Design tradeoffs and constraints are examined through analytical circuit models. Finally, experimental results are provided to verify the effectiveness of the proposed WPT system.

A concise, analytical method for incorporating the effects of zero voltage switching (ZVS) interval dynamics in small-signal discrete-time models of the dual-active bridge (DAB) converter is detailed. The method allows the influence of the resonant transition between tank inductor and switching device output capacitance to be examined. Importantly, the method does not require the inclusion of an additional state to account for these dynamics, which greatly simplifies the resulting models of converter behavior. The calculations are applicable to any alternate topology where ZVS transition behaviors contribute significantly to converter dynamics, as in many high frequency converters. The method is verified through experimental results on a 1 MHz DAB converter.

High voltage DC (400 V) power supply architecture is becoming a standard in today's data center power supply. To further convert from 400 V to 1 V, usually several power stages are connected in series. Therefore, even if the efficiency of each power stage is high; the overall system efficiency is limited because of the multiplication of each converter's efficiency. In this paper, a single power stage system which converts 400 V to 1 V directly and performs as the high voltage point of load (HV POL) is proposed. A multi-phase interleaved phase shift pulse width modulation (PWM) DC/DC converter with input series and output parallel (ISOP) connection is selected as the power stage topology. A simplified two phase connected system is discussed in this paper. Common duty cycle control technique is used to control the ISOP connected converters. Input voltage sharing and output current sharing is analyzed with different types of mismatches in the circuit. Finally, the preliminary testing results are given.

This paper investigates the Gallium Nitride (GaN) devices benefits on the LLC resonant DC-DC converter. First, the relationship between the device parameters and converter current based on an analytical loss model of LLC resonant converter has been established. After that, the loss analysis and comparison between Si-based and GaN-based converter is presented. The GaN-based design demonstrates about 40% loss reduction compared with the Si-based design. An insight on the extra winding loss due to the asymmetrical primary side and secondary side current is presented. The extra winding loss is reduced by 18% with GaN device application. The overall loss breakdown and the experimental result show the 20% overall loss reduction of the GaN-based LLC converter compared with the Si-based LLC converter.

Cross conduction is a well-known issue in buck converters and phase-leg topologies, in which fast switching transients cause spurious gate voltages in the synchronous device and a subsequent increase in switching loss. Cross conduction can typically be mitigated with a well-designed gate drive, but this is challenging with WBG devices. Phase legs using SiC and GaN devices can experience heavy cross conduction loss due to their exceptionally fast switching transients. Enhancement-mode GaN heterojunction field-effect transistors (HFETs) in the 600-V class are now commercially available, with switching transients as fast as 200 kV/μs. A double pulse test setup was used to measure the switching loss of one such GaN HFET, with several gate drive circuits and resistances. The results were analyzed and compared to characterize the effects of cross conduction in the active and synchronous devices of a phase-leg topology with enhancementmode GaN HFETs.

A novel resonant gate driver designed for the high-frequency enhancement-mode GaN HEMT power devices is proposed in this work. Simulation results indicate that it reduces gate driving loss more than 50% compared to the conventional non-resonant gate driving topology, and by 20% compared to the existing GaN resonant gate driver. The loss reduction is achieved by partially recovering gate charge to the supply during charging and discharging through a resonant process using an inductance in the gate loop. The resonant condition is managed using the desired turn-on and turn-off driving pulses at the input with specific driving time and pulse width control. These inputs also generate on-chip control signals for safely clamping the GaN power devices during the remaining switching cycle after the resonant transition has concluded. Simulations reveal improved switching waveforms using the proposed gate driver compared to the existing GaN resonant gate driving topologies.

Continuous variable series reactors (CVSRs), as a cost effective alternative to flexible AC transmission system (FACTS) series compensators, have been proposed to continuously vary the line reactance and control the power flow. The development of the power electronics based dc controller (DCC) is essential and unique to meet the need of CVSR in utility transmission grid applications. In addition to supplying the needed dc current to the CVSR dc winding, the DCC has to deal with the interaction from the ac winding. CVSR, together with DCC, will be installed outdoor in a substation, so the operation environment could be extremely harsh. The detailed design and implementation of the DCC are presented, along with simulations demonstrating the close relationship between the load profile of dc winding and converter output impedance. A 1000 A, 20 kW field prototype has been constructed and tested with a 115 kV, 1500 A CVSR to experimentally verify the performance of the whole CVSR system.

Four factors impact high speed switching of silicon carbide (SiC) devices in voltage source converters, including limited gate driving capability, cross-talk, parasitics associated in switching loop, and parasitics of inductive load. This paper focuses on a solution to mitigate the adverse impact of the aforementioned factors. First, an intelligent gate drive is developed for gate driving capability enhancement and cross-talk suppression. Second, placement and layout design of power devices, gate drive, and power stage board are proposed to minimize parasitics for fast switching and over-voltage mitigation. Third, an auxiliary filter is designed to mitigate the negative impact of inductive load's parasitics during the switching transient. Finally, by utilizing all techniques developed above, a three-phase voltage source inverter with Cree 1200-V/20-A SiC MOSFETs is established. Test results show that the switching behavior of SiC devices in actual three-phase voltage source inverter fed motor drives can mostly repeat the switching performance tested by the optimally-designed double pulse test.

GaN heterojunction field-effect transistors (HFETs) in the 600-V class are relatively new in commercial power electronics. The GaN Systems GS66508 is the first commercially available 650-V enhancement-mode device. Static and dynamic testing has been performed across the full current, voltage, and temperature range to enable GaN-based converter design using this new device. A curve tracer was used to measure Rds-on across the full operating temperature range, as well as the self-commutated reverse conduction (i.e. diode-like) behavior. Other static parameters such as transconductance and gate current were also measured. A double pulse test setup was constructed and used to measure switching loss and time at the fastest achievable switching speed, and the subsequent over-voltages due to the fast switching were characterized. Based on these results and analysis, an accurate loss model has been developed for the GS66508 to allow for GaN-based converter design and comparison with other commercially available devices in the 600-V class.

This paper presents an active gate driver for Silicon Carbide (SiC) devices to fully utilize their potentials of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control the gate voltages and gate loop impedances of both devices in a phase-leg during different switching transients. Compared to a conventional gate driver, the proposed circuit has the capability of increasing the switching speed of the phase-leg power devices, suppressing the cross-talk to below device limits. Based on CREE's 2nd generation 1200-V SiC MOSFETs, the test results demonstrate the effectiveness of this active gate driver under various operating conditions. The switching time decreases by up to 28% during turn-on and 50% during turn-off in the prototype circuit, resulting in up to 31% reduction in switching energy loss. In addition, spurious gate voltages induced by cross-talk are limited within the required range.

In this paper, the design of a high step down ratio (66:1) phase shift full bridge (PSFB) DC/DC converter used for data center power supplies in terms of primary side MOSFETs selection is covered. A detailed analysis of the converter's operation considering the impact of the output junction capacitance of primary side MOSFETs on the current RMS value has been performed. The study shows that a smaller output junction capacitance will lead to a smaller RMS current value on both primary and secondary side. For the high step down phase shift full bridge converter, transformer winding loss is the dominant loss; the reduction of current through the transformer will lead to a higher efficiency of the whole converter. This phenomenon is observed in experimental waveforms, and its impact on the converter's efficiency is also validated through experiment.

Dead-time in the voltage source converter significantly affects the reliability, power quality and losses. For SiC devices, considering the high sensitivity of turn-off time to the operating conditions (> 5× difference between light load and full load), as well as large extra energy loss induced by reverse conduction during superfluous dead-time (~ 15% of the switching loss), traditional fixed dead-time setting becomes inappropriate. This paper introduces an approach to achieve optimum dead-time for SiC based voltage source converter. First, turn-off behaviors under various operating conditions are investigated, and the relation between optimal dead-times and load currents are established. Second, a practical method for adaptive dead-time regulation is proposed, which consists of a dead-time optimization model and two gate assist circuits to sense the voltage commutation time during turn-off transient. Via synthesizing the monitored switching condition together with the preset dead-time optimization model, the micro-controller is able to online adjust the dead-time. Finally, based on a buck converter with 1200-V SiC MOSFETs, the test results show that by means of the proposed method, the power loss decreases by 12% at full load and 18.2% at light load.

A board-level integrated silicon carbide (SiC) MOSFET power module is developed in this work for high temperature and high power density applications. Specifically, a silicon-on-insulator (SOI) based gate driver is designed, fabricated and tested at different switching frequencies and temperatures. Also, utilizing high temperature packaging technologies, a 1200 V / 100 A SiC MOSFET phase-leg power module is built. The switching performance of the fabricated power module is fully evaluated at different temperatures up to 225 °C. Moreover, a buck converter prototype incorporating the SOI gate driver and SiC power module is built for high temperature continuous operation. The converter is operated within a wide range from 10 kHz to 100 kHz, with its junction temperature monitored by a thermo-sensitive electrical parameter (TSEP). The experimental results demonstrate that the integrated power module is able to operate at a junction temperature greater of 232 °C.

The paper describes the organizational framework and contents of a newly developed course on power electronics for electric drive vehicles. The course is developed and taught synchronously among three universities, with each institution individually managing student registration and assessments, and course administration. The participation of instructors and students from different institutions increases the impact of the course. In addition to the regular classes, followed on campus and remote, the high quality material generated by the instructors is available for the students, including a repository of recorded video lecturers and conferences given by specialist in key topics. Interaction with instructors and among students is promoted using a collaborative on-line tool.

The small-signal modeling of dual active bridge (DAB) converter dynamics in discrete time is a useful analysis tool due to the ability to incorporate behavior during zero-voltage switching (ZVS) intervals explicitly, and is advantageous for the direct design of digital compensators. While the control-to-output transfer function has been modeled previously, accurate models of the output impedance of the DAB converter which account for the converter behavior during switching intervals have not been proposed. A discrete time model of the DAB output impedance is developed and tested against experimental results for a 1 MHz, 50-to-4 V, 10 W DAB converter. The model is then extended to the analysis of load current step changes asynchronous to the discrete time sampling instances.

Wide band gap (WBG) power devices, such as Silicon Carbide (SiC) and Gallium Nitride (GaN) devices, have been innovatively applied in the data center power converters, which are based on the high voltage DC (HVDC) power distribution architecture, to evaluate the potential efficiency improvement. For the front-end AC-DC rectifier, a buck rectifier using SiC devices was implemented. The SiC devices were tested at first to obtain the static and switching characteristics. The number of devices in parallel, the switching frequency and the input/output filters were investigated. A prototype of 7.5 kW, 3 phase 480 VAC input, 400 VDC output front-end rectifier was built and tested. The peak efficiency reaches up to 98.55%, and the full load efficiency is 98.54%. For the intermediate DC-DC bus converter, the impact of the GaN devices on the LLC resonant converter efficiency was evaluated and compared with the Si counterparts. Based on the device loss analysis and the FEA simulation on the transformer winding loss, the GaN devices exhibited the reduced device loss, and also the capabilities to reduce the transformer winding loss. A 300 W, 400 VDC input, 12 VDC output GaN device based DC-DC bus converter was built and tested by 96.3% peak efficiency and 96.1% full load efficiency.

Electric-drive vehicles, including hybrid (HEV), plug-in hybrid (PHEV) and electric vehicles (EV), require a high-voltage (HV) battery pack for propulsion, and a low-voltage (LV) dc bus for auxiliary loads. This paper presents an architecture that uses modular dc-dc bypass converters to perform active battery cell balancing and to supply current to auxiliary loads, eliminating the need for a separate HV-to-LV high step-down dc-dc converter. The modular architecture, which achieves continuous balancing of all cells, can be used with an arbitrary number of cells in series, requires no control communications between converters, and naturally shares the auxiliary load current according to the relative state-of-charge (SOC) and capacities of the battery cells. Design and control details are provided for low-voltage, low-power dual active bridge (DAB) power converters serving as bypass converter modules. Experimental results are presented for a system consisting of two series 3.6 Ah NMC battery cells and two DAB bypass converters, with combined outputs rated to supply a 12 V, 35 W auxiliary load.

This paper describes a grid synchronization technique for single phase systems using only fixed filtering and compensation networks. Compared with other phase locking techniques, the proposed approach has the advantage of requiring no feedback control and a simplistic and predictable design. The paper uses test scenarios and metrics described in IEEE C37-118.1 for testing phasor measurement units (PMUs) to evaluate the performance of the proposed method. The dynamic response of the proposed approach is compared with the second order generalized integrator phase locked loop (SOGI-PLL) and second order generalized integrator frequency locked loop (SOGI-FLL).

This paper presents a board-level integrated silicon carbide (SiC) MOSFET power module for high temperature and high power density applications. Specifically, a silicon-on-insulator (SOI) based gate driver capable of operating at 200°C ambient temperature is designed and fabricated. The sourcing and sinking current capability of the gate driver are tested under various ambient temperatures. Also, a 1200 V/100 A SiC MOSFET phase-leg power module is developed utilizing high temperature packaging technologies. The static characteristics, switching performance, and short-circuit behavior of the fabricated power module are fully evaluated at different temperatures. Moreover, a buck converter prototype composed of the SOI gate driver and SiC power module is built for high temperature continuous operation. The converter is operated at different switching frequencies up to 100 kHz, with its junction temperature monitored by a thermo-sensitive electrical parameter (TSEP) and compared with thermal simulation results. The experimental results from the continuous operation demonstrate the high temperature capability of the power module at a junction temperature greater than 225°C.

Double pulse test (DPT) is a widely accepted method to evaluate the switching characteristics of semiconductor switches, including SiC devices. However, the observed switching performance of SiC devices in a PWM inverter for induction motor drives (IMD) is almost always worse than the DPT characterization, with slower switching speed, more switching losses, and more serious parasitic ringing. This paper systematically investigates the factors that limit the SiC switching performance from both the motor side and inverter side, including the load characteristics of induction motor/power cable, two more phase-legs for the three-phase PWM inverter as compared to the DPT, and the parasitic capacitive coupling effect between power devices and heat sink. Based on the three-phase PWM inverter with 1200 V SiC MOSFETs, the test results show that the induction motor, especially with a relatively long power cable, will significantly impact the switching performance, leading to switching time increase by a factor of 2, switching loss increase up to 30%, and serious parasitic ringing with 1.5 μs duration as compared to that tested by DPT. In addition, the interactions among the three phase-legs cannot be ignored unless the decoupling capacitors are mounted close to each phase-leg to support the dc bus voltage during switching transients. Also, the coupling capacitance induced by the heat sink equivalently increases the junction capacitance of power devices. However, its influence on the switching behavior in the motor drives is small considering the relatively large capacitance of the motor load.

This paper focuses on understanding the key impacting factors for switching speed of wide bandgap (WBG) devices in a voltage source converter. First, the constraints and challenges of WBG devices during fast switching transients are summarized. Special attention is given to the transient gate-source and drain-source voltages. Second, the impacts of major components in voltage source converter, including gate drivers, parasitics, inductive loads, and cooling systems, on the switching performance of power devices are systematically investigated. The critical parameters for each component are highlighted. Finally, design criteria are suggested to maximize switching speed of WBG devices.

Gallium Nitride High Electron Mobility Transistor (GaN HEMT) is an emerging wide band gap power device in recent years. Using a cascoded structure, the GaN HEMT can be combined with a low voltage MOSFET to make the combination behave as a normally-off device. This paper investigates the soft-switching behavior of cascode GaN HEMT in the phase-leg structure. The analysis reveals some internal device behaviors during the soft-switching transition, which are not found in the non-cascode device. Due to the internal feedback of the cascode structure, the channel current of the internal GaN HEMT drops to zero quickly, leading to extremely low turn-off loss. However, it has been found that there are switching energy loss dissipated in the internal GaN HEMT during the turn-on transient, although the external waveforms of the cascode GaN HEMT exhibit zero voltage switching. The fundamental reason is that ratio of the sum of MOSFET output capacitance and internal GaN HEMT input capacitance to the internal GaN HEMT output capacitance is quite low. Based on the simulation, by adding additional capacitance on the gate source terminals of internal GaN HEMT, these losses can be mitigated. Experimental tests using a commercially available GaN device are presented which show nearly 400 mW of loss at 1 MHz switching frequency in four different load current conditions.

The nature of reverse recovery losses is examined in hard-switched and soft-switched converters, using silicon (Si), silicon carbide (SiC), or gallium nitride (GaN) devices. A loss model and experimental results with a prototype 150-to-400 V, 150 W, boost converter operated at switching frequencies between 500 kHz and 2 MHz are used to characterize and quantify losses related to diode reverse recovery. It is found that reverse-recovery related losses with Si diodes cannot be neglected even when the converter is soft switched, with zero-current switching of the diode and zero-voltage switching of the transistor. The switching losses with SiC or GaN diodes are substantially smaller in all cases considered, and can be reduced to negligible values when the converter is soft switching.

Small mismatches in inductor-applied volt-seconds may arise in power converters due to asymmetries in circuit parasitics or modulation waveforms. These small mismatches can have significant impact on circuit operation, including the saturation of magnetic components, loss of regulation, and decrease in converter efficiency. Various auxiliary circuits and control methods have been developed to prevent volt-second imbalances from being applied to magnetic components. In this work, an inherent feedback specific to Zero-Voltage Switched (ZVS) converters is examined which automatically compensates for volt-second mismatch. A closed-form linearized relation between volt-second mismatch and inductor current offset is derived. This relation is then verified through simulation and experimental results using two prototype circuits comprised of an inductively loaded full-bridge and a dual active bridge (DAB) converter.

This paper describes a very simple Digital Pulse Width Modulator (DPWM), with under 100 picoseconds resolution capability in low-cost field-programmable gate arrays (FPGA). The DPWM implementation is based on internal carry chains and internal logic resources which are present in most FPGA families. The proposed approach does not require manual routing or placement, consumes few hardware resources, and does not rely on specialized phase locked loop or clock management resources. The DPWM is capable of supporting high switching frequencies for digitally controlled switched-mode power converters. A 50 MHz switching frequency DPWM with 60 picoseconds resolution and a 1 MHz switching frequency DPWM with 90 picoseconds resolution are experimentally demonstrated, with monotonicity and excellent linearity.

A control scheme is developed in which efficiency is optimized over a wide range of loads for a Dual Active Bridge (DAB) converter. A simple control strategy is proposed to adjust both the converter conversion ratio and switching dead times to maintain high efficiency in the presence of varying loads. To demonstrate feasibility of the proposed control method, experimental results are presented for a 150-to-12 V, 120 W, 1 MHz prototype converter which has 97.4% peak efficiency and maintains greater than 90% efficiency over a load range between 20 W and 120 W.

The existence of parasitic capacitances surrounding switching devices has been well established in the field. These capacitances are capable of having significant impact on the analysis, design, and performance of switched mode power supplies through increased switching loss or altered converter dynamics in the soft-switched case. As power converters continue to move to higher frequency, these effects become more pronounced and must be taken into account in converter design and analysis. This paper examines the nonlinear voltage-dependence of switching device capacitances and proposes a circuit-oriented analysis technique that allows the parasitic capacitances to be replaced with linear equivalents. The developed linear equivalents are then used with traditional circuit analysis to experimentally confirm their ability to accurately model converter operation of an example converter which exhibits significant loss and dynamic effects from device capacitances.

High switching frequencies can lead to converters with reduced size and high power density. Using RF/microwave devices, microwave design techniques can be applied to allow soft-switching of devices and thus high efficiency operation, at the cost of higher complexity and component count. This paper explores the use of microwave GaN High Electron Mobility Transistors (HEMT) to realize power conversion in the 10-100 MHz range using conventional PWM techniques that may enable simple, small and efficient converters. Several driver and test circuits are described, simulated and tested, and experimental results are also provided for a floating buck converter operating at 20 MHz and controlled using conventional PWM techniques.

A discrete-time, small-signal model is developed for the dual active bridge (DAB) converter which considers the effects of zero-voltage switching (ZVS) intervals on converter dynamics. The model is applied to the converter operating under phase-shift modulation, and is shown to be valid across a full range of load values constituting multiple operating modes of the converter. Finally, the model is applied to the case of an unregulated converter to show that output voltage variation that results in improved efficiency over wide range of loads can also lead to simplified control and compensation requirements across the full load range.

This paper describes a high step-down unregulated, fixed-ratio DC-DC converter (DCX) based on the dual active bridge (DAB) power stage operating at high switching frequency using enhancement-mode Gallium-Nitride-on-Silicon (GaN) transistors. The DAB power stage design as well as a comparison of losses using GaN and silicon MOS devices is based on a detailed state-plane analysis of resonant transitions. Experimental results are presented for a 150 W, 150-to-12 V prototype DCX operating at 1 MHz switching frequency.

This paper discusses a low-power 2.4GHz ISM band wireless sensor based on commercial components for sensing and data transmission. The sensor is powered wirelessly in the 5.8-GHz ISM band through an integrated dual-polarization antenna, rectifier and power management module. Since the unit is intended for mobile use, the variable available power is monitored, and the duty cycle for wireless data transmission adaptively adjusted through use of a low-power microcontroller and a custom power management circuit. In sleep mode, the circuit consumes 1μA at 2.5V.