To better support the superconducting propulsion system in the future aircraft applications, the technologies of high-power high switching frequency power electronics systems at cryogenic temperatures should be investigated. This article presents the development of a 40-kW cryogenically cooled three-level active neutral point clamped inverter with 3 kHz output line frequency and 140 kHz switching frequency. Si mosfets are characterized at cryogenic temperatures, and the results show that they have promising performance such as lower on-resistance and switching loss. The design of the inverter is presented in detail with the special consideration of the cryogenic temperature operation. Moreover, a packaging and integration architecture is designed and fabricated to demonstrate the feasibility and performance of the inverter in the lab. It is able to achieve no leakage with good thermal and air insulation. With the inverter and packaging, the experimental results show that the inverter operates properly at cryogenic temperatures. The loss is measured at different load conditions, and the loss analysis is given, which shows that the cryogenically cooled inverter has 30% less loss than operating at room temperature.

Using high voltage (HV) Silicon Carbide (SiC) power semiconductors in the modular multilevel converter (MMC) is promising because of a fewer submodules and lower switching loss compared to conventional Si based solutions. The nearest level pulse width modulation (NL-PWM) is commonly used in the MMC for medium voltage applications. However, with the NL-PWM and existing voltage balancing control, there are many submodules that switch their modes in a control cycle, resulting in a high dv/dt during the deadtime of the power semiconductor, which could be multiple times of the dv/dt of single device. This poses great challenges on the noise immunity and insulation design in the MMC using HV SiC devices, which have very fast switching speed. A novel voltage balancing control, which ensures only two submodules switch their modes in a control cycle, is proposed in this paper, limiting the maximum dv/dt to the dv/dt of single power semiconductor and meanwhile maintaining the voltage balance performance. The proposed voltage balancing control is experimentally validated in a 10 kV SiC MOSFET based MMC with four submodules per arm.

This article establishes an analytical model for the device drain–source overvoltage related to the two loops in three-level active neutral point clamped (3L-ANPC) converters. Taking into account the nonlinear device output capacitance, two common modulation methods are investigated in detail. The results show that the line switching frequency device usually has higher overvoltage, and the switching speed of the high switching frequency device is not strongly influenced by the multiple loops. By keeping the nonactive clamping switch off, the effect of the nonlinear device output capacitance can be significantly mitigated, which helps reduce the overvoltage. Moreover, the loop inductance can be reduced with vertical loop layout and magnetic cancellation in the printed circuit board and busbar design. A 500-kVA 3L-ANPC converter using silicon carbide mosfets was built and tested. The experimental results validate the overvoltage model of the two modulation methods as well as the busbar design. With the nonactive clamping switch off, the overvoltage of both the high and line switching frequency devices is significantly reduced, which helps achieve higher switching speed.

In order to evaluate the feasibility of newly developed gallium nitride (GaN) devices in a cryogenically cooled converter, this article characterizes a 650-V enhancement-mode GaN high-electron mobility transistor (GaN HEMT) at cryogenic temperatures. The characterization includes both static and dynamic behaviors. The results show that this GaN HEMT is an excellent device candidate to be applied in cryogenic-cooled applications. For example, transconductance at cryogenic temperature (93 K) is 2.5 times higher than one at room temperature (298 K), and accordingly, peak di/dt during turn-on transients at cryogenic temperature is around 2 times of that at room temperature. Moreover, the ON-resistance of the channel at the cryogenic temperature is only one-fifth of that at room temperature. The corresponding explanations of performance trends at cryogenic temperatures are also given from the view of semiconductor physics. In addition, several device failures were observed during the dynamic characterization of GaN HEMTs at cryogenic temperatures. The ultrafast switching speed-induced high di/dt and dv/dt at cryogenic temperatures amplify the negative effects of parasitics inside the switching loop. Based on failure waveforms, two failure modes were classified, and detailed failure mechanisms caused by ultrafast switching speed are given in this article.

Paralleling three phase three-level inverters is gaining popularity in industrial applications. However, analytical models for the harmonics calculation of a three-level neutral point clamped (NPC) inverter with popular space vector modulation (SVM) are not found in the literature. Moreover, how interleaving angle impacts the dc- and ac-side harmonics and electromagnetic interference (EMI) harmonics in parallel interleaved three-level inverters and how to optimize interleaving angle to reduce these harmonics have not been discussed in the literature. Furthering previous study, this article presents the modeling, analysis, and reduction of harmonics in paralleled and interleaved three-level NPC inverters with SVM. Analytical models for harmonic calculation are developed, and the dc-side harmonics characteristics of an NPC inverter are identified. The impact of interleaving angle on the ac-side voltage and dc-link current harmonics of parallel interleaved three-level NPC inverters is comprehensively studied. The impact of switching frequency and interleaving angle on EMI harmonics is also illustrated. Optimal interleaving angle ranges to reduce these harmonics are derived analytically. The developed models and harmonic reduction analysis are verified experimentally with two paralleled and interleaved three-level NPC inverters.

In order to apply power electronics systems to applications such as superconducting systems under cryogenic temperatures, it is necessary to investigate the characteristics of different parts in the power electronics system. This article reviews the influence of cryogenic temperature on power semiconductor devices including Si and wide bandgap switches, integrated circuits, passive components, interconnection and dielectric materials, and some typical cryogenic converter systems. Also, the basic theories and principles are given to explain the trends for different aspects of cryogenically cooled converters. Based on the review, Si active power devices, bulk Complementary metal-oxide-semiconductor (CMOS) based integrated circuits, nanocrystalline and amorphous magnetic cores, NP0 ceramic and film capacitors, thin/metal film and wirewound resistors are the components suitable for cryogenic operation. Pb-rich PbSn solder or In solder, classic printed circuit boards material, most insulation papers and epoxy encapsulant are good interconnection and dielectric parts for cryogenic temperatures.

This paper presents a new control method to enable large-scale solar photovoltaic (PV) plants to damp electromechanical oscillations. The proposed step-down modulation (SDM) control method is based on active power modulation, and it does not require curtailment as in other approaches. After an oscillation event is detected, the PV panel voltage is controlled to transiently deviate the power from its maximum power point (MPP), this power margin is used to modulate active power until the oscillation event is mitigated. Then, the SDM control restores the PV power to its MPP, and it is reset to operate for the next event. The control design, panel voltage strategy, and implementation is tested in a two-area system. A comparison of the SDM control with a curtailment-based PV damping control is also explored in a test case of the 179-bus WECC system with six large-scale PV plants, showing the improved damping capability of the proposed method.

Turn-on loss is the dominant part of the switching loss for SiC MOSFETs in hard switching. It is difficult to reduce turn-on loss with conventional voltage source gate drives (VSGs) because of the limited gate voltage rating and large internal gate resistance of SiC MOSFETs. A charge pump gate drive (CPG) that can reduce the turn-on loss is presented in this paper. By pre-charging the charge-storage capacitor in the gate drive with a charge pump circuit, the gate drive output voltage is pumped up to provide higher gate current during the turn-on transient. As a result, the turn-on time and loss is decreased. Moreover, due to the charge transfer from the charge-storage capacitor to the MOSFET gate capacitance, the pumped output voltage can naturally drop back to a normal value that avoids gate overcharging. The structure of the gate drive is simple, and no additional control is needed. The operation of the proposed CPG is verified with double pulse tests based on SiC MOSFETs. The switching loss of the proposed CPG is reduced by up to 71.7% compared to the conventional VSG at full load condition.

The attenuation performance of an electromagnetic interference filter can be significantly degraded by coupling, parasitics, and frequency-dependent nonlinearity, especially in high frequency (HF) range. This article reveals and investigates a mutual capacitive coupling effect in the popular filter structures with T-shaped joint. The mechanism is explained and the impact on filter attenuation is analyzed, which show this coupling is the dominant cause of performance degradation of T-shaped filters and a major cause for other T-shape-related filters. The effect patterns for both common-mode (CM) and differential-mode (DM) filters are analytically derived and further examined in multistage filter structures. Mitigation solutions using PCB slits and grounded shielding are proposed to improve filter transfer gain up to 30 dB in the HF range. A topological strategy is also presented, further enhancing filter attenuation. In addition, the impact of relative positions of the inductors on the coupling capacitance is discussed, and five positions are experimentally studied and compared. Experimental results obtained from three-phase LCL and LCLC filters verify the significance of this coupling and the effectiveness of the mitigation methods.

This paper studies how an outer fractional winding can impact the equivalent parallel capacitance (EPC) of a differential-mode inductor, which is a critical passive component in a power electronic converter to combat with electromagnetic noises, and proposes a winding scheme that can reduce EPC and increase inductance, achieving both high-frequency filtering performance and high density. To perform these studies, a comprehensive layer capacitance model based on energy equivalence principle is established, which decouples EPC contribution among three elements, i.e., outer fraction layer, layer-to-layer, and layer-to-core, thus enabling the impact evaluation of different winding elements and schemes. Experimental comparison results have validated the accuracy of this EPC model and excellent performance of the proposed winding scheme with EPC reduction by 4×. It reveals that contrary to previous understanding, the inverse winding, in fact, is more effective for EPC reduction than the direct winding in most of the partial layer scenarios, and that by using this scheme with the outer fraction layer, 45% higher inductance and slightly less EPC can be achieved, compared to the single-layer winding design.

Transformer flux dc bias is a critical issue, impacting the reliable operation of dual active bridge (DAB) converters especially when ungapped high permeability nanocrystalline core is used. Steady state current dc bias can easily saturate ungapped nanocrystalline transformers, and it is even more dangerous in transient conditions. A dc bias model is proposed to analyze steady state dc bias in different load conditions. The magnetizing current detection is necessary for closed loop control of dc bias, conductors’ position is shown to impact sensor noise, and it is detailed analyzed. To deal with both steady state and transient dc bias, a unified flux balancing control (UFBC) is proposed introducing a predictive bias suppression (PBS) method with closed-loop flux balancing control (CFBC). With the proposed PBS, both primary/secondary current balance and flux balance can be achieved within one switching cycle using UFBC. Power characteristics and interaction between power control and flux balancing control of DAB converters are analyzed, and the CFBC need to work in a low bandwidth due to sensor bandwidth limitation and interaction between power control and flux balancing control. The UFBC is verified on a 300kW cascaded DAB converter prototype.

For system planning of three-phase inverter-based islanded ac microgrids, the low frequency instability issue caused by interactions of inverter droop controllers is a major concern. When internal control information of procured commercial inverters is unknown, impedance-based small-signal stability criteria facilitate prediction of resonances in medium and high frequency ranges, but they usually assume the grid fundamental frequency as constant and thus they are incapable of analyzing the low-frequency oscillation of the fundamental frequency in islanded microgrids. Aiming at solving this issue, this paper proposes two stability analysis methods based on terminal characteristics of inverters and passive connection network including the dynamics of the fundamental frequency for analysis of low-frequency stability in islanded multiple-bus microgrids. Based on the Component Connection Method (CCM) to systematically separate inverters from the passive connection network, a general approach is developed to model the microgrid as a multiple-input-multiple-output (MIMO) negative feedback system in the common system d-q reference frame. By applying the generalized Nyquist stability criterion (GNC) to the return-ratio and return-difference matrices of the MIMO system model, the low-frequency stability related to the fundamental frequency can be analyzed using the measured terminal characteristics of inverters. Analysis and simulation of a 37-bus microgrid verify the effectiveness of the proposed stability analysis methods.

Dual-active-bridge (DAB) circuit is an excellent candidate for a high-efficiency, high-power density, and bidirectional electric vehicle charger. Unlike resonant circuits employing auxiliary inductors and capacitors, DAB minimizes the usage of passive components. The challenge, however, lies in the difficulty of securing zero-voltage switching (ZVS), particularly at light-to-medium load when using the conventional single-phase-shift (SPS) control. This is of utmost importance not only for the sake of the efficiency, but also for minimizing the switch-bridge crosstalk caused by the hard switching-on, thereby enhancing the system reliability. Although dual-phase-shift (DPS) and triple-phase-shift (TPS) can be the answer, they do introduce side effects such as larger switching-off current. This article systematically integrates SPS, DPS, and TPS to maximize full-power ZVS range for both steady state and transient operations in EV chargers. This article plots ZVS boundaries over the full power range, categorizes all operations into nine modes, and proposes a smooth transition method among all operation modes. Dead band is also incorporated in the ZVS boundary setting. Experimental results on a SiC-based charger validate the effectiveness of this method of widening ZVS range for output voltage of 200-450 Vdc and power of 0-20 kW, achieving smooth transitions among various operation modes, and suppressing the switch crosstalk, thereby securing high charger reliability.

Wide bandgap semiconductors with fast switching speed capability are becoming an enabler to achieve the higher power density design. However, the further increase of switching frequency cannot continuously improve the power quality of ac-side waveforms in dc-ac/ac-dc application. The main reason is the distortion of pulsewidth modulation (PWM) voltage at switching point under high switching frequency. In general, there are two contributors causing PWM voltage distortions in bridge-based topologies. One is the deadtime, which occupies higher ratio in the small duty cycle case under high switching frequency and induces the voltage errors. The other one is the turn-off transient in the small load current or around the zero-crossing point of the ac-side current, because the relatively slow rising slope of the drain-source voltage will affect the right duty cycle. To solve this issue, this paper proposes a closed-loop modulation scheme to compensate the duty cycle distortion of PWM voltage based on one-cycle control or charge control. Compared to the traditional feedforward type of compensation, the proposed scheme does not need online calculation and instantaneous inductor current sampling, and it shows potential to be a general scheme for variety of topologies and modulations. Simulations and experiments are carried out on a 400-kHz single-phase full-bridge inverter with 400-Hz fundamental frequency to demonstrate the performance of the proposed approach.

Wide-bandgap (WBG) devices are considered to be a better alternative to silicon switches to realize high-efficiency and high-power-density power electronics converters, such as electric vehicle (EV) onboard chargers. The two major challenges of GaN devices are their relatively high cost (~5 times compared to Si) and much smaller footprint than Si, which though is preferred in the high-power-density application is preferred but brings thermal challenges. Much like SiC is paralleled with Si, and GaN could be paralleled with Si to resolve these challenges. In this article, gallium nitride (GaN) high-electron-mobility transistors (HEMTs) are paralleled to various Si MOSFETs. Two different triggering approaches are considered: one adds a time delay between gate signals and the other uses a pulse triggering technique. Both methods ensure that the GaN endures the switching loss, while the Si switches conduct the majority of the current, thereby maximizing the advantages of both types of switches. To follow is a comprehensive study of the critical transient processes, such as the gate cross talking between Si and GaN, current commutation in the dead band, voltage spikes during the turn-off caused by parasitics, the thermal performance, and the cost analysis. Demonstrated success testing this approach at 400 V/80 A provides evidence that this is a possible approach in the onboard EV battery charger applications. The success of testing under 400 V/80 A makes it possible to an onboard EV battery charger.

Multi-pulse AC/DC Rectifiers (MPRs) are widely used in aviation application due to their rugged structure, cost effective, and high reliability features. In this paper, an overview of the recent advances and trends on the MPR technology, mainly the auto-configured transformer based MPRs, and its application in more electric aircrafts are performed. The work covers system topologies, transformer configurations, passive and active harmonic reduction schemes, case study, practical selection and design guideline, and applications. To fairly evaluate the performances of MPRs with different pulse number, necessary simulation studies are carried out under comparable conditions, including power rating, input and output specifications, and transformer configuration etc. Then, an 18-pulse asymmetric DP configured prototype is established based on the simulation evaluation and experimental verification is performed. It is expected that the paper can provide a broad perspective on MPR technology, and, in particular, highlight the latest emerged technology that significantly promotes the performances of MPRs. More importantly, it is desired that the results obtained in this paper can provide an effective selection guideline and design suggestion for researchers and engineers engaged in designing MPRs, especially for aviation application.

To understand the limitation of maximizing the switching speed of SiC low current discrete devices and high current power modules in hard switching applications, double pulse tests are conducted and the testing results are analyzed. For power modules, the switching speed is generally limited by the parasitics rather than the gate drive capability. For discrete SiC devices, the conventional voltage source gate drive (VSG) is not sufficient to maximize the switching speed even if the external gate resistance is minimized. The limitation of existing current source gate drives (CSG) are analyzed, and a CSG dedicated for SiC discrete devices is proposed, which can provide constant current during the switching transient regardless of the high Miller voltage and large internal gate resistance. Compared with the conventional VSG, the proposed CSG achieves 67% faster turnon time and 50% turn-off time, and 68% reduction in switching loss at full load condition.

For some distribution networks equipped with smart switches such as Chattanooga Electric Power Board (EPB) system, they can island some areas of the network to mitigate the impact through defensive islanding. However, due to intermittency and uncertainty of renewable-based distributed energy resources (DERs), it is highly likely that the islanded areas would experience insufficient or surplus power. This problem can be relieved by changing the boundaries of islanded areas to incorporate neighbouring load sections (LSs) or disconnect some connected LSs. Considering penetration level and sharply changing rate of renewable energy, it is challenging to define suitable boundaries for islanded areas in real time. Therefore, a two-stage energy management system (EMS) is proposed in this study, which includes day-ahead scheduling stage as well as short-term and real-time control stages. In the first stage, the initial switch combinations of LSs and DERs’ scheduling are obtained through a mixed integer quadratic programming, whereas the second stage is based on rule-based power management algorithm. Finally, a model reduced from real EPB system is used for validating the proposed two-stage EMS. The results successfully verify the effectiveness and performance of the proposed EMS for addressing the energy management of islanded areas under defensive islanding.

The design, implementation, and testing of a control system for a flexible microgrid (MG) is presented in this study. The MG controllers can be implemented in a real-world MG with multiple smart switches, photovoltaic panel system, and battery energy storage systems (BESSs). With the benefits from smart switches, the MG has unique characteristics such as dynamic boundary and flexible point of interconnection (POI) concepts. To control such a unique MG and realise the dynamic boundary, an MG central controller and two types of local controllers are implemented. Compared to the MG with fixed boundary, the MG with dynamic boundary can have smaller BESS capacity, better utilisation of renewable energy, and multiple POI options. Also, compared with IEEE Std 2030.7–2017, the topology identification and active and reactive power balance functions are newly designed to realise the dynamic boundary concept. The planned islanding and reconnection functions are modified to realise the flexible POI concept. These functions are introduced including the software architecture, cooperation, and interaction among them. Finally, a hardware-in-the-loop testing platform based on the Opal-RT real-time simulator is set up to verify the performance, realisation of the dynamic boundary, and flexible POI concepts with four comprehensive test scenarios.

Junction temperature is an important design/operation parameter, as well as, a significant indicator of device's health condition for power electronics converters. Compared to its silicon (Si) counterparts, it is more critical for silicon carbide (SiC) devices due to the reliability concern introduced by the immaturity of new material and packaging. This paper proposes a practical implementation using an intelligent gate drive for online junction temperature monitoring of SiC devices based on turn-off delay time as the thermo-sensitive electrical parameter. First, the sensitivity of turn-off delay time on the junction temperature for fast switching SiC devices is analyzed. A gate impedance regulation assist circuit is proposed to enhance the sensitivity by a factor of 60 and approach 736 ps/°C tested in the case study with little penalty on the power conversion performance. Next, an online monitoring unit based on gate assist circuits is developed to monitor the turn-off delay time in real time with the resolution less than 104 ps. As a result, the micro-controller is capable of “reading” junction temperature during the converter operation. Finally, a SiC-based half-bridge inverter is constructed with an intelligent gate drive consisting of the gate impedance regulation circuit and online turn-off delay time monitoring unit. Experimental results demonstrate the feasibility and accuracy of the proposed approach.

This paper identifies extra junction capacitances and switching commutation loops introduced by line-frequency devices (i.e., non-active every other half line cycle) in three-level ac/dc converters and investigates the corresponding effects. Junction capacitances and power loops are well known as the key factors that impact converter switching loss and device stress, thus influence device selection, power stage layout, and thermal design. By examining switching transients of the commonly used T-shaped and I-shaped three-level converters, the cause and mechanism of the extra junction capacitances and power loops are presented. The impacts on switching loss, device voltage stress, and ac-side voltage/current distortion are respectively reported and analyzed. A loss calculation scheme for the three-level converter to include that extra loss is proposed. A power layout scheme to mitigate the device voltage stress is provided. Compensation and modeling of the voltage and current distortion are also proposed. Experimental results conducted on several types of three-level converter prototypes including a gallium nitride based 115 Vac/650 Vdc/1.5-kW/450-kHz Vienna-type rectifier and a SiC MOSFET based 1-kV/10-kW/ 280-kHz three-level active neutral-point-clamped inverter confirm the presented effects and verify the associated analysis and solutions.

Battery energy storage systems (BESSs) tend to be too costly, restrictive, and require high maintenance for experimental use, but power system tests often need their representation. As a solution, we propose an all-in-one, reconfigurable BESS emulation tool for grid applications that only requires one three-phase voltage-source converter. This emulator provides chemistry-specific battery behavior like previous work, but it also includes the BESS's power electronics interface and control as well as automatic frequency and voltage support functions for the attached power system. Thus, it allows simple, plug-and-play BESS emulation for grid applications. This paper details the construction, verification, and use of the BESS emulator in an existing grid testbed and concludes that it provides an inexpensive, easy-to-use alternative to using real BESSs in power system experiments.

This paper presents the characterization of the temperature-dependent short-circuit performance of a Gen3 10 kV/20 A silicon carbide (SiC) mosfet. The test platform consisting of a phase-leg configuration and a fast speed 10-kV solid state circuit breaker, with temperature control, is introduced in detail. A novel FPGA-based short-circuit protection circuit having a response time of 1.5 μs is proposed and integrated into the gate driver. The short-circuit protection is validated through the platform. The short-circuit characteristics for both the hard switching fault and fault under load (FUL) types at various dc-link voltages (from 500 V to 6 kV) are tested and discussed. The saturation current increases with dc-link voltage and achieves 360 A at 6 kV. Different from low voltage SiC devices, there is no current spike in FUL type of fault. The temperature-dependent short-circuit performance is also presented from 25 to 125 °C. The difference of short-circuit waveforms at various initial junction temperatures can be neglected. A thermal model of the 10-kV SiC mosfet is built for the junction temperature estimation during the short circuit and for analysis of the initial junction temperature impact on the short-circuit performance.

As wide-bandgap (WBG) devices and applications move from niche to mainstream, a new generation of engineers trained in this area is critical to continue the development of the field. This paper introduces a new hands-on course in characterization of WBG devices, which is an emerging and fundamental topic in WBG-based techniques. First, the lecture-simulation-experiment format based course structure and design considerations, such as safety, are presented. Then, the necessary facilities to support this hands-on course are summarized, including classroom preparation, software tools, and laboratory equipment. Afterward, the detailed course implementation flow is presented to illustrate the approach of close interaction among lecture, simulation, and experiment to maximize students' learning outcomes. Finally, grading for students and course evaluation by students are discussed, highlighting the findings and potential improvements. Detailed course materials are provided via potenntial.eecs.utk.edu/WBGLab for educational use.

Semiconductor devices based solid-state circuit breakers (SSCBs) are promising in the dc power distribution system as protective equipment for their ultrashort action time. This letter proposes a topology of SSCB using series connected silicon carbide (SiC) metal oxide semiconductor field effect transistors (mosfets), which only requires a single isolated gate driver. The SSCB has very low cost and high reliability because it only has 13 components including passive components and diodes apart from two SiC mosfets to achieve both balanced voltage distribution during short-circuit interruption duration and reliable positive gate voltage during on-state. The SSCB prototype is built and experimentally verified to interrupt 75 A short-circuit current under the dc-bus voltage of 1200 V within 1.5 μs.

Silicon carbide (SiC) power modules are promising for high-power applications because of the high breakdown voltage, high operation temperature, low ON-resistance, and fast switching speed. However, the large parasitic inductance in existing package designs results in compromised performance, i.e., long blanking time in the desaturation protection scheme and large overvoltage spikes during the switching transient. Consequently, the benefits of SiC devices are often not fully utilized in practical applications. This paper deals with these two issues and aims at improving the electrical performance of the existing SiC module package. Specifically, a package design with Kelvin drain-to-source connection is first proposed to minimize the blanking time. More than 99% reduction of blanking time is achieved experimentally compared to the conventional package design. Second, a low parasitic inductance package with double-side cooling is proposed to allow the fast switching speed of SiC devices without sacrificing the thermal performance. A power loop inductance of 1.63 nH is realized from Q3D simulation. Verified by the experiment, more than 60% reduction of power loop inductance is achieved in comparison to a previously designed baseline module. At 0-Ω external gate resistance, the turn-off voltage spike is less than 9% of the dc-link voltage under the rated load condition.

Electric distribution systems around the world are seeing an increasing number of utility-owned and non-utility-owned (customer-owned) intelligent devices and systems being deployed. New deployments of utility-owned assets include self-healing systems, microgrids, and distribution automation. Non-utility-owned assets include solar photovoltaic generation, behind-the-meter energy storage systems, and electric vehicles. While these deployments provide potential data and control points, the existing centralized control architectures do not have the flexibility or the scalability to integrate the increasing number or variety of devices. The communication bandwidth, latency, and the scalability of a centralized control architecture limit the ability of these new devices and systems from being engaged as active resources. This paper presents a standards-based architecture for the distributed power system controls, which increases operational flexibility by coordinating centralized and distributed control systems. The system actively engages utility and non-utility assets using a distributed architecture to increase reliability during normal operations and resiliency during extreme events. Results from laboratory testing and preliminary field implementations, as well as the details of an ongoing full-scale implementation at Duke Energy, are presented.

Compared with grid to vehicle (G2V) and vehicle to grid (V2G) modes, electric vehicle (EV) battery chargers are more vulnerable to power quality problems at the autonomous mode, i.e., creating its own electric grid during the grid blackout while facing unbalanced and nonlinear loads. Active damping is another common challenge given most charger equip LC filters at grid-end voltage-source inverters (VSIs). In this article, an output-voltage control with harmonic compensation plus virtual impedance term is proposed to achieve high power quality and necessary damping, respectively. The physical meaning of the virtual impedance is further explained, and the voltage loop with PI plus multiresonant terms is analyzed in depth. More importantly, the analytical solutions and procedures to design such controllers considering the time delays are proposed. Finally, simulation results and experimental data on an EV battery charger prototype using SiC devices, which is made of one VSI and one isolated dc/dc converter, validate the effectiveness of the proposed design methodology.

As a new application area of electric vehicles, vehicle to home (V2H) recently becomes one of the most attractive research areas. In this paper, a three-phase four-wire inverter using four half-bridge legs is adopted to realize the V2H functionality. Such three-phase inverter acts as the grid-side ac/dc part of the battery charger. In order to deal with the imbalanced load, an independently controlled neutral module has been adopted to form the neutral line and provide the path for the zero-sequence current, together with split dc-bus capacitors. Each phase employs the independent sinusoidal pulse width modulation control with the virtual resistor paralleled with the load, namely, notch-filter-incorporated capacitor voltage feedback control, which damps harmonics around the resonant frequency at various load conditions. In addition, this paper quantifies the load imbalance versus the dc-link voltage oscillation and provides the guidance for the selection of the dc-link capacitance. Finally, a 10-kW three-phase four-wire inverter working at the V2H mode is built and tested, with the three-phase imbalanced load imposed to validate the proposed design and control strategy.

The integrated starter-generator system (ISGS) is a combination of starter and generator for independent power systems in transportation. It replaces both a conventional starter and generator with a single set of highly integrated devices. A power hardware in the loop simulation that is flexible and can include the hardware under test is used to test the ISGS under representative field conditions. This paper utilizes the special structure of the ISGS and proposes an ISGS emulator (ISGSE) to develop and test the converter. The proposed ISGSE can be used to test a variety of motor drives or rectifiers including dynamic capabilities without necessitating a connection to a large motor load. To emulate the ISGS, the structure and operation principle in different modes are introduced in detail. Also, the issue of stability and accuracy is discussed in this paper. Detailed simulation and experimental comparisons are carried out between the ISGS and the ISGSE, which validates the proposed ISGSE as an effective tool for designing and testing new motor drives.

For any voltage above 600-V dc, it is usually recommended to use 900-1200-V SiC MOSFETs instead of GaN high-electron-mobility transistors (HEMTs), given presently commercial GaN HEMTs have the maximum voltage rating up to 650 V. This paper is an attempt of employing 650-V E-mode GaN HEMTs to build a three-level bidirectional dc/dc converter, with the input as an 800-V battery, the output as the ~400-V dc grid, and half of the switches working at the hard-switching mode. The active-balancing control instead of using clamping diodes in the conventional neutral-point clamping topology is adopted, aiming at higher efficiency. Simulation based on the double-pulse test results shows that such a design strategy with GaN has a better efficiency over the conventional 1200-V SiC MOSFETbased buck/boost converter. Two bottom-cooled GaN HEMTs are in parallel to enhance the power capability and efficiency, which require the special focus on the parasitic parameters. The effects of parasitics, especially the stray inductance in the current commutating loop and the gate drive loop during switching transitions, have been comprehensively analyzed in this paper. Experimental results under 800-V bus voltage are presented to verify the proposed solution.

Middle-point inductance Lmiddle can be introduced in multiple-chip power module package designs. In this paper, the effect of middle-point inductance on switching transients is analyzed first using a frequency-domain analysis. Then a dedicated multiple-chip power module is fabricated with the capability of varying Lmiddle, and extensive switching tests are conducted to evaluate the middle-point inductance's impact. Experiment result shows that the active MOSFET's turn-on loss decreases at higher values of Lmiddle, while its turn-off loss increases. Detailed analysis of this loss variation is presented. In addition to the switching loss variation, it is also observed that different peak voltage stresses are imposed on the active switch and antiparallel diode during the switching transients. Specifically, in the case of lower MOSFET's turn-off, the maximum voltage of the lower MOSFET increases as Lmiddle goes up; however, the peak voltage of the antiparallel diode decreases significantly. The induced voltage spikes during upper MOSFET turn-on process is also evaluated, and an opposite trend is observed experimentally. Analysis of the voltage overshoot variation is discussed. Based on the experimental evaluation and analysis, a multiple-chip power module package design guideline is summarized considering the middle-point inductance's effect.

Parasitic ringing is commonly observed during the high-speed switching of wide band-gap (WBG) devices. Additional loss contributed by parasitic ringing becomes a concern especially for high switching frequency applications. This paper investigates the effects of parasitic ringing on the switching loss of WBG devices in a phase-leg configuration. An analytical switching loss model considering parasitics in power devices and application circuit is derived. Two switching commutation modes, gate drive dominated mode and power loop dominated mode, are investigated, respectively, and the switching loss induced by damping ringing is identified. It is found that this portion of the loss is at most the energy stored in parasitics, which always exists regardless of the switching speed and parasitic ringing. Therefore, with the given WBG device in the specific application circuit, damping more severe parasitic ringing during faster switching transient would not introduce higher switching loss. Additionally, the extra switching loss induced by resonance among parasitics and crosstalk is investigated. It is observed that severe resonance and its resultant over-voltage during the turn-on transient worsen the crosstalk, causing large shoot-through current and excessive switching loss. The theoretical analysis has been verified by the double pulse test with a 1200-V/50-A SiC-based phase-leg power module.

The integrated starter-generator system (ISGS) is a combination of starter and generator for independent power systems in transportation. It replaces both a conventional starter and generator with a single set of highly integrated devices. A power hardware in the loop simulation that is flexible and can include the hardware under test is used to test the ISGS under representative field conditions. This paper utilizes the special structure of the ISGS and proposes an ISGS emulator (ISGSE) to develop and test the converter. The proposed ISGSE can be used to test a variety of motor drives or rectifiers including dynamic capabilities without necessitating a connection to a large motor load. To emulate the ISGS, the structure and operation principle in different modes are introduced in detail. Also, the issue of stability and accuracy is discussed in this paper. Detailed simulation and experimental comparisons are carried out between the ISGS and the ISGSE, which validates the proposed ISGSE as an effective tool for designing and testing new motor drives.

For any voltage above 600-V dc, it is usually recommended to use 900-1200-V SiC MOSFETs instead of GaN high-electron-mobility transistors (HEMTs), given presently commercial GaN HEMTs have the maximum voltage rating up to 650 V. This paper is an attempt of employing 650-V E-mode GaN HEMTs to build a three-level bidirectional dc/dc converter, with the input as an 800-V battery, the output as the ~400-V dc grid, and half of the switches working at the hard-switching mode. The active-balancing control instead of using clamping diodes in the conventional neutral-point clamping topology is adopted, aiming at higher efficiency. Simulation based on the double-pulse test results shows that such a design strategy with GaN has a better efficiency over the conventional 1200-V SiC MOSFETbased buck/boost converter. Two bottom-cooled GaN HEMTs are in parallel to enhance the power capability and efficiency, which require the special focus on the parasitic parameters. The effects of parasitics, especially the stray inductance in the current commutating loop and the gate drive loop during switching transitions, have been comprehensively analyzed in this paper. Experimental results under 800-V bus voltage are presented to verify the proposed solution.

Middle-point inductance Lmiddle can be introduced in multiple-chip power module package designs. In this paper, the effect of middle-point inductance on switching transients is analyzed first using a frequency-domain analysis. Then a dedicated multiple-chip power module is fabricated with the capability of varying Lmiddle, and extensive switching tests are conducted to evaluate the middle-point inductance's impact. Experiment result shows that the active MOSFET's turn-on loss decreases at higher values of Lmiddle, while its turn-off loss increases. Detailed analysis of this loss variation is presented. In addition to the switching loss variation, it is also observed that different peak voltage stresses are imposed on the active switch and antiparallel diode during the switching transients. Specifically, in the case of lower MOSFET's turn-off, the maximum voltage of the lower MOSFET increases as Lmiddle goes up; however, the peak voltage of the antiparallel diode decreases significantly. The induced voltage spikes during upper MOSFET turn-on process is also evaluated, and an opposite trend is observed experimentally. Analysis of the voltage overshoot variation is discussed. Based on the experimental evaluation and analysis, a multiple-chip power module package design guideline is summarized considering the middle-point inductance's effect.

Parasitic ringing is commonly observed during the high-speed switching of wide band-gap (WBG) devices. Additional loss contributed by parasitic ringing becomes a concern especially for high switching frequency applications. This paper investigates the effects of parasitic ringing on the switching loss of WBG devices in a phase-leg configuration. An analytical switching loss model considering parasitics in power devices and application circuit is derived. Two switching commutation modes, gate drive dominated mode and power loop dominated mode, are investigated, respectively, and the switching loss induced by damping ringing is identified. It is found that this portion of the loss is at most the energy stored in parasitics, which always exists regardless of the switching speed and parasitic ringing. Therefore, with the given WBG device in the specific application circuit, damping more severe parasitic ringing during faster switching transient would not introduce higher switching loss. Additionally, the extra switching loss induced by resonance among parasitics and crosstalk is investigated. It is observed that severe resonance and its resultant over-voltage during the turn-on transient worsen the crosstalk, causing large shoot-through current and excessive switching loss. The theoretical analysis has been verified by the double pulse test with a 1200-V/50-A SiC-based phase-leg power module.

Owing to the recent power outages caused by extreme events, installing battery energy storage and backup generators is important to improve resiliency for a grid-tied microgrid. In the design stage, the event occurrence time and duration, which are highly uncertain and cannot be effectively predicted, may affect the needed battery and backup generator capacity but are usually assumed to be pre-determined in utility planning tools. This study investigates the optimal battery and backup generator sizing problem considering the stochastic event occurrence time and duration for the grid-tied microgrid under islanded operation. The reliability requirement is quantified by the mean value of the critical customer interruption time in each stochastic islanding time window (ITW), whose length is the duration and the centre is the occurrence time. The stochastic ITW constraint is then transformed to a probability-weighted expression to derive an equivalent Mixed Integer Linear Programming model. Numerical simulations on a realistic grid-tied PV-based microgrid demonstrate that the total cost is reduced by 11.5% considering the stochastic ITW, compared with the deterministic ITW under the same reliability requirement.

Wide bandgap semiconductors are gradually being adopted in high power-density high efficiency applications, providing faster switching and lower loss, and at the same time imposing new challenges in control and hardware design. In this paper, a gallium nitride-based Vienna-type rectifier with SiC diodes is proposed to serve as the power factor correction stage in a high-density battery charger system targeting for aircraft applications with 800 Hz ac system and 600 V level dc link, where power quality is required according to DO160E standard. To meet the current harmonic requirement, PWM voltage distortion during the turn-off transient, is studied as the main harmonics contributor. The distortion mechanism caused by different junction capacitances of the switching devices is presented. A mitigation scheme considering the nonlinear voltage-dependent characteristics of these capacitances is proposed and then simplified from a pulse-based turn-off compensation method to a general modulation scheme. Simulation and experimental results with a 450 kHz Vienna-type rectifier demonstrate the performance of the proposed approach, showing a THD reduction from 10% to 3% with a relatively low-speed controller.

A transmission line emulator has been developed to flexibly represent interconnected ac lines under normal operating conditions in a voltage-source-converter-based power system emulation platform. As the most serious short-circuit fault condition, the three-phase short-circuit fault emulation is essential for power system studies. This paper proposes a model to realize a three-phase short-circuit fault emulation at different locations along a single transmission line or one of several parallel-connected transmission lines. At the same time, a combination method is proposed to eliminate the undesired transients caused by the current reference step changes while switching between the fault state and the normal state. Experiment results verify the developed transmission line three-phase short-circuit fault emulation capability.

A Hardware Testbed(HTB) is developed for accurate and flexible emulation and testing of electrical power system and their control, measurement, and protection systems. In the HTB, modular and programmable power electronics converters are used to mimic the static and dynamic characteristics of electrical power components. This paper overviews the development, integration, and application of the HTB, covering emulation principle, hardware and software configuration, and example results of power system research using the HTB. The advantages of the HTB, compared with real-time digital simulation and downscaled hardware-based testing platform are discussed.

A systematic study on a gallium nitride (GaN) high-electron-mobility transistor (HEMT) based battery charger, consisting of a Vienna-type rectifier plus a dc-dc converter, reveals a common phenomenon. That is, the high switching frequency, and high di/dt and dv/dt noise inside GaN converters may induce a dc drift or low frequency distortion on sensing signals. The distortion mechanisms for different types of sensing errors are identified and practical minimization techniques are developed. Experimental results on the charger system have validated these mechanisms and corresponding approaches, showing an overall reduction of input current total harmonic distortion (THD) by up to 5 percentage points and improved dc-dc output voltage regulation accuracy. The knowledge helps engineers tackle the troublesome issues related to noise.

The series connection of insulated gate bipolar transistors (IGBTs) allows operation at voltage levels higher than the rated voltage of one IGBT and has less power semiconductor costs compared to multilevel topologies. However, voltage unbalance during the switching transient is a challenge for series-connected device application. This paper presents an field-programmable gate array (FPGA)-based voltage balancing strategy for multiseries-connected high-voltage (HV)-IGBTs including an FPGA-based active voltage balancing control (AVBC) circuit integrated into the gate driver and the control for multiseries-connected IGBTs. The effectiveness of the control has been experimentally validated in a prototype using four 4.5 kV HV-IGBTs in series connection.

The temperature-dependent characteristics of the third-generation 10-kV/20-A SiC MOSFET including the static characteristics and switching performance are carried out in this paper. The steady-state characteristics, including saturation current, output characteristics, antiparallel diode, and parasitic capacitance, are tested. A double pulse test platform is constructed including a circuit breaker and gate drive with >10-kV insulation and also a hotplate under the device under test for temperature-dependent characterization during switching transients. The switching performance is tested under various load currents and gate resistances at a 7-kV dc-link voltage from 25 to 125 C and compared with previous 10-kV MOSFETs. A simple behavioral model with its parameter extraction method is proposed to predict the temperature-dependent characteristics of the 10-kV SiC MOSFET. The switching speed limitations, including the reverse recovery of SiC MOSFET's body diode, overvoltage caused by stray inductance, crosstalk, heat sink, and electromagnetic interference to the control are discussed based on simulations and experimental results.

This paper proposes a simple and cost-effective current measurement technique for four-phase switched reluctance motor (SRM) control, by splitting the dual bus line of the converter, without pulse injection and voltage penalty. Only two Hall-effect sensors are utilized, where one is installed in the upper bus to measure two phase currents, and the other is placed in the lower bus to measure other two phase currents. In order to realize independent current measurement in the whole turn-on region, switching functions are redesigned so that upper switches of two phases act as the choppers, while lower switches of the other two phases are employed as the choppers. Compared to traditional drives, the developed system requires only two Hall-effect sensors in the dual bus line, without a need for individual phase sensors or additional devices, which reduces the cost and volume for SRM drives. Furthermore, compared to the single-sensor based current measurement scheme, the proposed method has no need to implement pulse injection and will not cause any voltage penalty and current distortion, which also improve the current measurement accuracy and system performance. Simulation and experiments carried out on a 150-W four-phase 8/6 SRM confirm the effectiveness of the proposed technique.

As two exemplary candidates of wide-bandgap devices, SiC MOSFETs and GaN HEMTs are regarded as successors of Si devices in medium-to-high-voltage (>1200 V) and low-voltage (<;650 V) domains, respectively, thanks to their excellent switching performance and thermal capability. With the introduction of 650 V SiC MOSFETs and GaN HEMTs, the two technologies are in direct competition in <;650 V domains, such as Level 2 battery chargers for electric vehicles (EVs). This study applies 650 V SiC and GaN to two 240 VAC/7.2 kW EV battery chargers, respectively, aiming to provide a head-to-head comparison of these two devices in terms of overall efficiency, power density, thermal performance, and cost. The charger essentially is an indirect matrix converter with a dual-active-bridge stage handling the power factor correction and power delivery simultaneously. These two chargers utilise the same control strategy, varying the phase-shift and switching frequency to cover the wide input range (80-260 VAC) and wide output range (200 V-450 VDC). Experimental results indicated that at the same efficiency level, the GaN charger is smaller, more efficient and cheaper, while the SiC charger has a better thermal performance.

The hybrid electric bus (HEB) presents an emerging solution to exhaust gas emissions in urban transport. This paper proposes a multiport bidirectional switched reluctance motor (SRM) drive for solar-assisted HEB (SHEB) powertrain, which not only improves the motoring performance, but also achieves flexible charging functions. To extend the driving miles and achieve self-charging ability, photovoltaic (PV) panels are installed on the bus to decrease the reliance on fuelsbatteries and charging stations. A bidirectional front-end circuit with a PV-fed circuit is designed to integrate electrical components into one converter. Six driving and five charging modes are achieved. The dc voltage is boosted by the battery in generator control unit (GCU) driving mode and by the charge capacitor in battery driving mode, where the torque capability is improved. Usually, an extra converter is needed to achieve battery charging. In this paper, the battery can be directly charged by the demagnetization current in GCU or PV driving mode, and can be quickly charged by the PV panels and GCUAC grids at SHEB standstill conditions, by utilizing the traction motor windings and integrated converter circuit, without external charging converters. Experiments on a three-phase 128 SRM confirm the effectiveness of the proposed drive and control scheme.

A high-frequency injection (HFI) sensorless control for interior permanent magnet synchronous motors with enhanced precision and widened speed range is proposed in this paper. The injection frequency reaches up to 2 kHz under a 50~100 kHz silicon carbide (SiC)-based three-phase inverter. In addition to the high switching frequency, the field-programmable gate array (FPGA) is utilized to achieve high control bandwidth (>200 kHz) when implementing the field-oriented control algorithm. The benefits of high switching frequency and high control bandwidth in senseless controls are explained theoretically, i.e., leaving enough room for the injection frequency by using SiC while tuning down the noise-to-signal ratio by using the FPGA. Experimental results verified that such manners improved the position estimation and lifted the injection frequency effectively, which further allows us to widen the motor speed range under the HFI sensorless control from 0 to 500 r/min with the conventional Si+DSP design to 0~1200 r/min with the proposed SiC+FPGA.

This paper introduces the concept of modular design methodology for hardware design and development of motor drives. The modular design process is first introduced separating the hardware development into three parts: controller, mother board and phase-leg module. The control and circuit function can be decoupled from the phase-leg module development. The hardware update can be simplified with the phase-leg module development and verification. Two design examples are used to demonstrate this method: a DC-fed motor drive with Si IGBTs and an AC-fed motor drive with SiC devices. Design of DC-fed motor drive aims at developing the converter with customized IGBT package for high temperature. Experience with development of the converter with commercial IGBTs simplifies the process. As the AC-fed motor drive is a more complex topology using more advanced devices, the modular design method can simplify and improve the development especially for new packaged devices. Also, the modular design method can help to study the electromagnetic interference (EMI) issue for motor drives, which is presented with an extra design example.

This paper introduces series work of common-mode (CM) voltage reduction for the paralleled inverters. The paralleled inverters' phase-legs are connected through coupling inductors and the combined three-phase currents are provided to the load. Interleaving is an approach to reduce the CM voltage for the paralleled inverters but it cannot eliminate CM voltage. A novel pulse-width-modulation (PWM) method for paralleled inverters which can theoretically achieve zero CM voltage is developed. Considering the basic voltage vectors in each inverter, novel paralleled voltage vectors which have zero CM voltage are proposed to combine the reference voltage vector. The action time's distribution and voltage vectors' sending sequence for each inverter are also introduced. The proposed PWM method can make sure the voltage of the two inverters are balanced in each switching cycle and limits the circulating current through small coupling inductors. Similar to interleaving space vector PWM, the proposed zero CM PWM also has the ability to reduce the output current ripple and electromagnetic interference (EMI). Simulation and experimental results are provided to show the advantage of paralleled inverters in CM voltage reduction and validate the proposed method has good performance to reduce CM current and CM EMI noise.

The emergence of wide bandgap (WBG) semiconductor devices such as silicon carbide (SiC) and gallium nitride (GaN) devices promises to revolutionize next-generation power electronics converters. Featuring high breakdown electric field, low specific on-resistance, fast switching speed, and high junction temperature capability, these devices are beneficial for the efficiency, power density, reliability, and/or cost of power electronics converters. WBG devices have been employed in some commercial and industrial products with more applications expected in near future. However, extremely fast switching and other superior characteristics of WBG device, and high switching frequency/high voltage/high junction temperature operation, present new design challenges in gate drive and protection, packaging and layout, EMI suppression, and converter control, etc. Addressing these design and application issues is critical to the adoption, commercialization, and success of WBG based power electronics. This special issue intends to report the latest progress in these important areas.

A high-frequency injection (HFI) sensorless control for interior permanent magnet synchronous motors with enhanced precision and widened speed range is proposed in this paper. The injection frequency reaches up to 2 kHz under a 50~100 kHz silicon carbide (SiC)-based three-phase inverter. In addition to the high switching frequency, the field-programmable gate array (FPGA) is utilized to achieve high control bandwidth (>200 kHz) when implementing the field-oriented control algorithm. The benefits of high switching frequency and high control bandwidth in senseless controls are explained theoretically, i.e., leaving enough room for the injection frequency by using SiC while tuning down the noise-to-signal ratio by using the FPGA. Experimental results verified that such manners improved the position estimation and lifted the injection frequency effectively, which further allows us to widen the motor speed range under the HFI sensorless control from 0 to 500 r/min with the conventional Si+DSP design to 0~1200 r/min with the proposed SiC+FPGA.

This paper introduces the concept of modular design methodology for hardware design and development of motor drives. The modular design process is first introduced separating the hardware development into three parts: controller, mother board and phase-leg module. The control and circuit function can be decoupled from the phase-leg module development. The hardware update can be simplified with the phase-leg module development and verification. Two design examples are used to demonstrate this method: a DC-fed motor drive with Si IGBTs and an AC-fed motor drive with SiC devices. Design of DC-fed motor drive aims at developing the converter with customized IGBT package for high temperature. Experience with development of the converter with commercial IGBTs simplifies the process. As the AC-fed motor drive is a more complex topology using more advanced devices, the modular design method can simplify and improve the development especially for new packaged devices. Also, the modular design method can help to study the electromagnetic interference (EMI) issue for motor drives, which is presented with an extra design example.

This paper introduces series work of common-mode (CM) voltage reduction for the paralleled inverters. The paralleled inverters' phase-legs are connected through coupling inductors and the combined three-phase currents are provided to the load. Interleaving is an approach to reduce the CM voltage for the paralleled inverters but it cannot eliminate CM voltage. A novel pulse-width-modulation (PWM) method for paralleled inverters which can theoretically achieve zero CM voltage is developed. Considering the basic voltage vectors in each inverter, novel paralleled voltage vectors which have zero CM voltage are proposed to combine the reference voltage vector. The action time's distribution and voltage vectors' sending sequence for each inverter are also introduced. The proposed PWM method can make sure the voltage of the two inverters are balanced in each switching cycle and limits the circulating current through small coupling inductors. Similar to interleaving space vector PWM, the proposed zero CM PWM also has the ability to reduce the output current ripple and electromagnetic interference (EMI). Simulation and experimental results are provided to show the advantage of paralleled inverters in CM voltage reduction and validate the proposed method has good performance to reduce CM current and CM EMI noise.

The emergence of wide bandgap (WBG) semiconductor devices such as silicon carbide (SiC) and gallium nitride (GaN) devices promises to revolutionize next-generation power electronics converters. Featuring high breakdown electric field, low specific on-resistance, fast switching speed, and high junction temperature capability, these devices are beneficial for the efficiency, power density, reliability, and/or cost of power electronics converters. WBG devices have been employed in some commercial and industrial products with more applications expected in near future. However, extremely fast switching and other superior characteristics of WBG device, and high switching frequency/high voltage/high junction temperature operation, present new design challenges in gate drive and protection, packaging and layout, EMI suppression, and converter control, etc. Addressing these design and application issues is critical to the adoption, commercialization, and success of WBG based power electronics. This special issue intends to report the latest progress in these important areas.

As one of the most popular cloud services, data storage has attracted great attention in recent research efforts. Key-value (k-v) stores have emerged as a popular option for storing and querying billions of key-value pairs. So far, existing methods have been deterministic. Providing such accuracy, however, comes at the cost of memory and CPU time. In contrast, we present an approximate k-v storage for cloud-based systems that is more compact than existing methods. The tradeoff is that it may, theoretically, return errors. Its design is based on the probabilistic data structure called “bloom filter”, where we extend the classical bloom filter to support key-value operations. We call the resulting design as the kBF (key-value bloom filter). We further develop a distributed version of the kBF (d-kBF) for the unique requirements of cloud computing platforms, where multiple servers cooperate to handle a large volume of queries in a load-balancing manner. Finally, we apply the kBF to a practical problem of implementing a state machine to demonstrate how the kBF can be used as a building block for more complicated software infrastructures.

This paper presents an intelligent gate drive for silicon carbide (SiC) devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control gate voltages and gate loop impedances of both devices in a phase-leg configuration during different switching transients. Compared to conventional gate drives, the proposed circuit has the capability of accelerating the switching speed of the phase-leg power devices and suppressing the crosstalk to below device limits. Based on Wolfspeed 1200-V SiC MOSFETs, the test results demonstrate the effectiveness of this intelligent gate drive under varying operating conditions. More importantly, the proposed intelligent gate assist circuitry is embedded into a gate drive integrated circuit, offering a simple, compact, and reliable solution for end-users to maximize benefits of SiC devices in actual power electronics applications.

With the increased cloud computing and digital information storage, the energy requirement of data centers keeps increasing. A high-voltage point of load (HV POL) with an input series output parallel structure is proposed to convert 400 to 1 VDC within a single stage to increase the power conversion efficiency. The symmetrical controlled half-bridge current doubler is selected as the converter topology in the HV POL. A load-dependent soft-switching method has been proposed with an auxiliary circuit that includes inductor, diode, and MOSFETs so that the hard-switching issue of typical symmetrical controlled half-bridge converters is resolved. The operation principles of the proposed soft-switching half-bridge current doubler have been analyzed in detail. Then, the necessity of adjusting the timing with the loading in the proposed method is analyzed based on losses, and a controller is designed to realize the load-dependent operation. A lossless RCD current sensing method is used to sense the output inductor current value in the proposed load-dependent operation. Experimental efficiency of a hardware prototype is provided to show that the proposed method can increase the converter's efficiency in both heavy- and light-load conditions.

Dead time significantly affects the reliability, power quality, and efficiency of voltage-source converters. For silicon carbide (SiC) devices, considering the high sensitivity of turn-off time to the operating conditions (> 5× difference between light load and full load) and characteristics of inductive loads (> 2× difference between motor load and inductor), as well as large additional energy loss induced by the freewheeling diode conduction during the superfluous dead time (~15% of the switching loss), then the traditional fixed dead time setting becomes inappropriate. This paper introduces an approach to adaptively regulate the dead time considering the current operating condition and load characteristics via synthesizing online monitored turn-off switching parameters in the microcontroller with an embedded preset optimization model. Based on a buck converter built with 1200-V SiC MOSFETs, the experimental results show that the proposed method is able to ensure reliability and reduce power loss by 12% at full load and 18.2% at light load (8% of the full load in this case study).

This paper develops a synchronous generator emulator by using a three-phase voltage source converter for transmission level power system testing. Different interface algorithms are compared, and the voltage type ideal transformer model is selected considering accuracy and stability. At the same time, closed-loop voltage control with current feed-forward is proposed to decrease the emulation error. The emulation is then verified through two different ways. First, the output waveforms of the emulator in experiments are compared with the simulation under the same condition. Second, a transfer function perturbation-based error model is obtained and redefined as the relative error for the amplitude and phase between the emulated and the target system over the frequency range of interest. The major cause of the error is investigated through a quantitative analysis of the error with varying parameters.

This paper presents a steady-state model of MMC for the second-order phase voltage ripple prediction under unbalanced conditions, taking the impact of negative-sequence current control into account. From the steady-state model, a circular relationship is found among current and voltage quantities, which can be used to evaluate the magnitudes and initial phase angles of different circulating current components. Moreover, in order to calculate the circulating current in a point-to-point MMC-based HVdc system under unbalanced grid conditions, the derivation of equivalent dc impedance of an MMC is discussed as well. According to the dc impedance model, an MMC inverter can be represented as a series connected R-L-C branch, with its equivalent resistance and capacitance directly related to the circulating current control parameters. Experimental results from a scaled-down three-phase MMC system under an emulated single-line-to-ground fault are provided to support the theoretical analysis and derived model. This new models provides an insight into the impact of different control schemes on the fault characteristics and improves the understanding of the operation of MMC under unbalanced conditions.

The double pulse test (DPT) is a widely accepted method to evaluate the dynamic behavior of power devices. Considering the high switching-speed capability of wide band-gap devices, the test results are very sensitive to the alignment of voltage and current (V-I) measurements. Also, because of the shoot-through current induced by Cdv/dt (i.e., cross-talk), the switching losses of the nonoperating switch device in a phase-leg must be considered in addition to the operating device. This paper summarizes the key issues of the DPT, including components and layout design, measurement considerations, grounding effects, and data processing. Additionally, a practical method is proposed for phase-leg switching loss evaluation by calculating the difference between the input energy supplied by a dc capacitor and the output energy stored in a load inductor. Based on a phase-leg power module built with 1200-V/50-A SiC MOSFETs, the test results show that this method can accurately evaluate the switching loss of both the upper and lower switches by detecting only one switching current and voltage, and it is immune to V-I timing misalignment errors.

This paper presents the development of a scaled four-terminal high-voltage direct current (HVDC) testbed, including hardware structure, communication architecture, and different control schemes. The developed testbed is capable of emulating typical operation scenarios including system start-up, power variation, line contingency, and converter station failure. Some unique scenarios are also developed and demonstrated, such as online control mode transition and station re-commission. In particular, a dc line current control is proposed, through the regulation of a converter station at one terminal. By controlling a dc line current to zero, the transmission line can be opened by using relatively low-cost HVDC disconnects with low current interrupting capability, instead of the more expensive dc circuit breaker. Utilizing the dc line current control, an automatic line current limiting scheme is developed. When a dc line is overloaded, the line current control will be automatically activated to regulate current within the allowable maximum value.

Small-signal stability is an important concern in three-phase inverter-based ac power systems. The impedance-based approach based on the generalized Nyquist stability criterion (GNC) can analyze the stability related with the medium and high-frequency modes of the systems. However,. the GNC involves the right-half-plane (RHP) pole calculation of return-ratio transfer function matrices, which cannot be avoided for stability analysis of complicated ac power systems. Therefore, it necessitates the detailed internal control information of the inverters, which is not normally available for commercial inverters. To address this issue, this paper introduces the component connection method (CCM) in the frequency domain for stability analysis in the synchronous d-q frame, by proposing a method of deriving the impedance matrix of the connection networks of inverter-based ac power systems. Demonstration on a two-area system and a microgrid shows that: The CCM-enabled approach can avoid the RHP pole calculation of return-ratio matrices and enables the stability analysis by using only the impedances of system components, which could be measured without the need for the internal information. A stability analysis method based on d-q impedances, the CCM, and the determinant-based GNC is also proposed to further simplify the analysis process. Inverter controller parameters can be designed as stability regions in parameter spaces, by repetitively applying the proposed stability analysis method. Simulation and experimental results verify the validity of the proposed stability analysis method and the parameter design approach.

Hybrid ac/dc transmission extends the power transfer capacity of existing long ac lines closer to their thermal limit, by superposing the dc current onto three-phase ac lines through a zigzag transformer. However, this transformer could suffer saturation under unbalanced line impedance conditions. This paper introduces the concept of hybrid line impedance conditioner (HLIC) as a cost-effective approach to compensate for the line unbalance and therefore avoid saturation. The topology and operation principle are presented. The two-level control strategy is described, which enables autonomous adaptive regulation without the need of system-level control. Design and implementation are also analyzed, including dc-link capacitance as one of the key line conditioner components, HLIC installation, and protection under fault conditions. The cost study on this HLIC-based hybrid system is also performed to reveal the benefits of the solution. Simulation results and experimental results based on a down-scaled prototype are provided to verify the feasibility of the proposed approach.

One way to incorporate the increasing amount of wind penetration is to control wind turbines to emulate the behavior of conventional synchronous generators. However, the energy balance is the main issue for the wind turbines to be truly dispatchable by the power system operator such as the generators. This paper presents a comprehensive virtual generator control method for the full converter wind turbine, with a minute-level energy storage in the dc link as the energy buffer. The voltage closed-loop virtual synchronous generator control of the wind turbine allows it to work under both grid-connected and stand-alone condition. Power balance of the wind turbine system is achieved by controlling the rotor speed of the turbine according to the loading condition. With the proposed control, the wind turbine system can enhance the dynamic response, and can be dispatched and regulated by the system operator. The sizing design of the short term energy storage is also discussed in this paper. Experimental results are presented to demonstrate the feasibility and effectiveness of the proposed control method.

Newly emerged gallium nitride (GaN) devices feature ultrafast switching speed and low on-state resistance that potentially provide significant improvements for power converters. This paper investigates the benefits of GaN devices in an LLC resonant converter and quantitatively evaluates GaN devices' capabilities to improve converter efficiency. First, the relationship of device and converter design parameters to the device loss is established based on an analytical model of LLC resonant converter operating at the resonance. Due to the low effective output capacitance of GaN devices, the GaN-based design demonstrates about 50% device loss reduction compared with the Si-based design. Second, a new perspective on the extra transformer winding loss due to the asymmetrical primary-side and secondary-side current is proposed. The device and design parameters are tied to the winding loss based on the winding loss model in the finite element analysis (FEA) simulation. Compared with the Si-based design, the winding loss is reduced by 18% in the GaN-based design. Finally, in order to verify the GaN device benefits experimentally, 400- to 12-V, 300-W, 1-MHz GaN-based and Si-based LLC resonant converter prototypes are built and tested. One percent efficiency improvement, which is 24.8% loss reduction, is achieved in the GaN-based converter.

Research on high voltage (HV) silicon carbide (SiC) power semiconductor devices has attracted much attention in recent years. This paper overviews the development and status of HV SiC devices. Meanwhile, benefits of HV SiC devices are presented. The technologies and challenges for HV SiC device application in converter design are discussed. The state-of-the-art applications of HV SiC devices are also reviewed.

Three-phase inverter-based multibus ac power systems could suffer from the harmonic instability issue. The existing impedance-based stability analysis method using the Nyquist stability criterion once requires the calculation of right-half-plane (RHP) poles of impedance ratios, which would result in a heavy computation burden for complicated systems. In order to analyze the harmonic stability of multibus ac systems consisting of both voltage-controlled and current-controlled inverters without the need for RHP pole calculation, this paper proposes two sequence-impedance-based harmonic stability analysis methods. Based on the summary of all major connection types including mesh, the proposed Method 1 can analyze the harmonic stability of multibus ac systems by adding the components one by one from nodes in the lowest level to areas in the highest system level, and accordingly, applying the stability criteria multiple times in succession. The proposed Method 2 is a generalized extension of the impedance-sum-type criterion to be used for the harmonic stability analysis of any multibus ac systems based on Cauchy's theorem. The inverter controller parameters can be designed in the forms of stability regions in the parameter space, by repetitively applying the proposed harmonic stability analysis methods. Experimental results of inverter-based multibus ac systems validate the effectiveness of the proposed harmonic stability analysis methods and parameter design approach.

Arm inductor in a modular multilevel converter (MMC) is used to limit the circulating current and dc short circuit fault current. The circulating current in MMC is dominated by second-order harmonic, which can be largely reduced with circulating current suppressing control. By analyzing the mechanism of the circulating current suppressing control, it is found that the circulating current at switching frequency becomes the main harmonic when suppression control is implemented. Unlike the second-order harmonic that circulates only within the three phases, switching frequency harmonic also flows through the dc side and may further cause high-frequency dc voltage harmonic. This paper develops the theoretical relationship between the arm inductance and switching frequency circulating current, which can be used to guide the arm inductance selection. The experimental results with a downscaled MMC prototype verify the existence of the switching frequency circulating current and its relationship with arm inductance.

Multifrequency wireless power transfer (WPT) is advantageous in facilitating compatibility with different WPT standards. However, implementing a multifrequency transmitter often requires compromises in system size, complexity, power transfer capability, or output regulation. In this paper, a single-inverter-based dual-mode WPT system is proposed. The system employs a multifrequency programmed pulse width modulation scheme. This multifrequency modulated inverter can simultaneously generate and regulate 100-kHz and 6.78-MHz outputs, or multiple frequencies within ranges of 87-300 kHz, which facilitates the development of multistandard WPT technology for consumer electronics. The principle of the proposed modulation is illustrated, where two different frequencies are concurrently modulated using a programmed pulse train of square waveforms for power delivery, while eliminating certain harmonics. Design tradeoffs and constraints are examined through analytical circuit models. Finally, experimental results are provided to verify the method on a gallium-nitride-based WPT prototype.

This paper presents a comprehensive short-circuit ruggedness evaluation and numerical investigation of up-to-date commercial silicon carbide (SiC) MOSFETs. The short-circuit capability of three types of commercial 1200-V SiC MOSFETs is tested under various conditions, with case temperatures from 25 to 200 °C and dc bus voltages from 400 to 750 V. It is found that the commercial SiC MOSFETs can withstand short-circuit current for only several microseconds with a dc bus voltage of 750 V and case temperature of 200 °C. The experimental short-circuit behaviors are compared, and analyzed through numerical thermal dynamic simulation. Specifically, an electrothermal model is built to estimate the device internal temperature distribution, considering the temperature-dependent thermal properties of SiC material. Based on the temperature information, a leakage current model is derived to calculate the main leakage current components (i.e., thermal, diffusion, and avalanche generation currents). Numerical results show that the short-circuit failure mechanisms of SiC MOSFETs can be thermal generation current induced thermal runaway or high-temperature-related gate oxide damage.

High power density is a desirable feature of power electronics design, which prompts economic incentives for industrial applications. In this paper, a gallium nitride (GaN)-based 2-kVA single-phase inverter design was developed for the Google Little Box Challenge, which achieves a 102-W/in3 power density. First, the static and dynamic temperature-dependent characteristics of multiple SiC and enhancement-mode GaN FETs are investigated and compared. Based on the device testing results, several topologies of the inverter stage and different power decoupling solutions are compared with respect to the device volume, efficiency, and thermal requirements. Moreover, some design approaches for magnetic devices and the implementation of gate drives for GaN devices are discussed in this paper, which enable a compact and robust system. Finally, a dc notch filter and a hard switching full-bridge converter are combined as the proposed design for the prototype. A 2-kVA prototype is demonstrated, which meets the volume, efficiency, and thermal requirements. The performance of the prototype is verified by the experimental results.

A hardware testbed platform emulating multiple-area power system scenario dynamics has been established aiming at multiple time-scale real-time emulations. In order to mimic real power flow situations in the utility system, the load emulators have to behave like real ones in both their static and dynamic characteristics. A constant-impedance, constant-current, and constant-power (ZIP) model has been used for static load types, while a three-phase induction motor model has been built to represent dynamic load types. In this paper, ways of modeling ZIP and induction motor loads and the performance of each load emulator are discussed. Comparisons between simulation and experimental results are shown as well for the validation of the emulator behaviors. A real-time composite power load emulator is then demonstrated with desired characteristics and detailed transients for representing a power system PQ bus dynamics.

Gallium nitride (GaN) heterojunction field-effect transistors are an enabling technology for high-density converter design. This paper proposes a three-level dc-dc converter with dual outputs based on enhancement-mode GaN devices, intended for use as a battery charger in aircraft applications. The charger can output either 28 or 270 V, selected with a jumper, to satisfy the two most common dc bus voltage requirements in airplanes. It operates as an LLC converter in the 28 V mode and as a buck converter in the 270 V mode. In both operation modes, the devices can realize zero voltage switching (ZVS). With the chosen modulation method, the converter can realize automatic voltage balancing of the flying capacitor and the frequency doubling function to act as an interleaved converter. For the LLC mode, the resonant frequency is twice the switching frequency of primary-side switches, and for the buck mode, the frequency of the output inductor current is also twice the switching frequency. This helps to reduce the size of magnetics while maintaining a low switching loss. Also, the converter utilizes a matrix transformer, with resonant parameters designed to reduce conduction loss and avoid ZVS failure. The operating principle of the converter is analyzed and then experimentally verified on a 1.5-kW prototype with 1 MHz resonant frequency.

Gallium nitride (GaN) power devices are an emerging technology that have only recently become available commercially. This new technology enables the design of converters at higher frequencies and efficiencies than those achievable with conventional Si devices. This paper reviews the characteristics and commercial status of both vertical and lateral GaN power devices, providing the background necessary to understand the significance of these recent developments. In addition, the challenges encountered in GaN-based converter design are considered, such as the consequences of faster switching on gate driver design and board layout. Other issues include the unique reverse conduction behavior, dynamic Rds,on, breakdown mechanisms, thermal design, device availability, and reliability qualification. This review will help prepare the reader to effectively design GaN-based converters, as these devices become increasingly available on a commercial scale.

Voltage-balancing control in a modular multilevel converter (MMC) impacts not only the voltage difference among submodule capacitors, but also the power device switching patterns. As a result, MMC possesses a nondeterministic switching pattern and its switching frequency is no longer an independent parameter. This paper theoretically investigates how voltage-balancing control influences the switching frequency in the MMC. Equations describing the relationship between the submodule capacitor unbalanced voltage and converter switching frequency are derived. Since unbalanced voltage also impacts the submodule capacitor ripple voltage and voltage/current harmonics, the design interaction between switching frequency and submodule capacitance, as well as the selection of unbalanced voltage are further investigated. Both simulation and experimental verifications are provided.

This paper overviews the silicon carbide (SiC) technology. The focus is on the benefits of SiC based power electronics for converters and systems, as well as their ability in enabling new applications. The challenges and research trends on the design and application of SiC power electronics are also discussed.

Electric-drive vehicles, including hybrid, plug-in hybrid, and electric vehicles, require a high-voltage (HV) battery pack for propulsion and a low-voltage (LV) dc bus for auxiliary loads. This paper presents an architecture that uses modular dc-dc bypass converters to perform active battery cell balancing and to supply current to auxiliary loads, eliminating the need for a separate HV-to-LV high step-down dc-dc converter. The modular architecture, which achieves continuous balancing of all cells, can be used with an arbitrary number of cells in series, requires no control communication between converters, and naturally shares the auxiliary load current according to the relative state-of-charge (SOC) and capacities of the battery cells. Design and control details are provided for LV low-power dual active bridge (DAB) power converters serving as the bypass converter modules. Furthermore, current sharing is examined and worst-case SOC and current deviations are derived for mismatches in cell capacities, SOCs, and parasitic resistances. Experimental results are presented for a system consisting of 21 series 25 Ah Panasonic lithium-ion NMC battery cells and 21 DAB bypass converters, with combined outputs rated to supply a 650-W auxiliary load.

The three-phase current source rectifier (CSR) features a step-down ac-dc voltage conversion function, smaller ac filter size compared with the traditional two-level voltage source rectifier, and inrush current limiting capability. However, large conduction loss of semiconductor devices has limited the wide application of traditional CSRs. In this paper, a new CSR topology, delta-type current source rectifier (DCSR), is proposed to reduce the conduction loss. The proposed rectifier has delta-type connections on its ac input side and its dc-link current can be shared by multiple devices at a given time. This paper introduces the DCSR's operation principle, modulation scheme, and design method. Based on the analysis, the conduction loss can be reduced by up to 20% with the proposed topology. An 8-kW prototype is then built to experimentally verify the performance of the DCSR.

Electric-drive vehicles, including hybrid, plug-in hybrid, and electric vehicles, require a high-voltage (HV) battery pack for propulsion and a low-voltage (LV) dc bus for auxiliary loads. This paper presents an architecture that uses modular dc-dc bypass converters to perform active battery cell balancing and to supply current to auxiliary loads, eliminating the need for a separate HV-to-LV high step-down dc-dc converter. The modular architecture, which achieves continuous balancing of all cells, can be used with an arbitrary number of cells in series, requires no control communication between converters, and naturally shares the auxiliary load current according to the relative state-of-charge (SOC) and capacities of the battery cells. Design and control details are provided for LV low-power dual active bridge (DAB) power converters serving as the bypass converter modules. Furthermore, current sharing is examined and worst-case SOC and current deviations are derived for mismatches in cell capacities, SOCs, and parasitic resistances. Experimental results are presented for a system consisting of 21 series 25 Ah Panasonic lithium-ion NMC battery cells and 21 DAB bypass converters, with combined outputs rated to supply a 650-W auxiliary load.

The three-phase current source rectifier (CSR) features a step-down ac-dc voltage conversion function, smaller ac filter size compared with the traditional two-level voltage source rectifier, and inrush current limiting capability. However, large conduction loss of semiconductor devices has limited the wide application of traditional CSRs. In this paper, a new CSR topology, delta-type current source rectifier (DCSR), is proposed to reduce the conduction loss. The proposed rectifier has delta-type connections on its ac input side and its dc-link current can be shared by multiple devices at a given time. This paper introduces the DCSR's operation principle, modulation scheme, and design method. Based on the analysis, the conduction loss can be reduced by up to 20% with the proposed topology. An 8-kW prototype is then built to experimentally verify the performance of the DCSR.

Double pulse test (DPT) is a widely accepted method to evaluate the switching characteristics of semiconductor switches, including SiC devices. However, the observed switching performance of SiC devices in a PWM inverter for induction motor drives is almost always worse than the DPT characterization, with slower switching speed, more switching losses, and more serious parasitic ringing. This paper systematically investigates the factors that limit the SiC switching performance from both the motor side and inverter side, including the load characteristics of induction motor and power cable, two more phase legs for the three-phase PWM inverter in comparison with the DPT, and the parasitic capacitive coupling effect between power devices and heat sink. Based on a three-phase PWM inverter with 1200 V SiC MOSFETs, test results show that the induction motor, especially with a relatively long power cable, will significantly impact the switching performance, leading to a switching time increase by a factor of 2, switching loss increase up to 30% in comparison with that yielded from DPT, and serious parasitic ringing with 1.5 μs duration, which is more than 50 times of the corresponding switching time. In addition, the interactions among the three phase legs cannot be ignored unless the decoupling capacitors are mounted close to each phase leg to support the dc bus voltage during switching transients. Also, the coupling capacitance due to the heat sink equivalently increases the junction capacitance of power devices; however, its influence on the switching behavior in the motor drives is small considering the relatively large capacitance of the motor load.

With the emerging area of smart grids, one critical challenge faced by administrators of wide-area measurement systems is to analyze and model streaming data with limited resources on their embedded controllers. Usually, streaming data can be modeled as a multiset where each data item has its own frequency. In this paper, we study the problem on how to generate histograms of data items based on their frequency, so we can identify various issues such as power line tripping or line faults under constraints. The primary challenge for achieving this goal using conventional methods is that keeping an individual counter for each unique type of data is too memory-consuming, slow, and costly. In this paper, we describe a novel data structure and its associated algorithms, called the loglog bloom filter, for this purpose. This data structure extends the classical bloom filter with a recent technique called probabilistic counting, so it can effectively generate histograms for streaming data in one pass with sub-linear overhead. Therefore, this method is suitable for data processing in smart grids, where limited computational resources are available on the controllers. We analyze the performance, trade-offs, and capacity of this data structure, and evaluate it with real data traces collected through the frequency disturbance recorders deployed for the FNET/GridEye infrastructure. We demonstrate that this method can identify the frequencies of all unique items with high accuracy and low memory overhead, so that data outliers can be conveniently identified.

This paper presents the analysis and control of a multilevel modular converter (MMC)-based HVDC transmission system under three possible single-line-to-ground fault conditions, with special focus on the investigation of their different fault characteristics. Considering positive-, negative-, and zero-sequence components in both arm voltages and currents, the generalized instantaneous power of a phase unit is derived theoretically according to the equivalent circuit model of the MMC under unbalanced conditions. Based on this model, a novel double-line frequency dc-voltage ripple suppression control is proposed. This controller, together with the negative- and zero-sequence current control, could enhance the overall fault-tolerant capability of the HVDC system without additional cost. To further improve the fault-tolerant capability, the operation performance of the HVDC system with and without single-phase switching is discussed and compared in detail. Simulation results from a three-phase MMC-HVDC system generated with MATLAB/Simulink are provided to support the theoretical analysis and proposed control schemes.

This paper presents a board-level integrated silicon carbide (SiC) mosfet power module for high temperature and high power density application. Specifically, a silicon-on-insulator (SOI)-based gate driver capable of operating at 200 °C ambient temperature is designed and fabricated. The sourcing and sinking current capability of the gate driver are tested under various ambient temperatures. Also, a 1200 V/100 A SiC mosfet phase-leg power module is developed utilizing high temperature packaging technologies. The static characteristics, switching performance, and short-circuit behavior of the fabricated power module are fully evaluated at different temperatures. Moreover, a buck converter prototype composed of the SOI gate driver and SiC power module is built for high temperature continuous operation. The converter is operated at different switching frequencies up to 100 kHz, with its junction temperature monitored by a thermosensitive electrical parameter and compared with thermal simulation results. The experimental results from the continuous operation demonstrate the high temperature capability of the power module at a junction temperature greater than 225 °C.

Reliability of power converters and lifetime prediction has been a major topic of research in the last few decades, especially for traction applications. The main failures in high power semiconductors are caused by thermomechanical fatigue. Power cycling and temperature cycling are the two most common thermal acceleration tests used in assessing reliability. The objective of this paper is to study the various power cycling tests found in the literature and to develop generalized steps in planning application specific power cycling tests. A comparison of different tests based on the failures, duration, test circuits, and monitored electrical parameters is presented.

The three-phase buck-type rectifier features a step-down ac-dc conversion function, smaller filter size, inrush current limiting capability, and potential for high efficiency, where its switching loss is dependent on the modulation scheme and the specific semiconductors used. In this paper, three different device combinations are compared through experiments on their switching characteristics for the buck rectifier application. It is shown that the switching performance of two series-connected devices becomes worse than a single device due to the superposition of the nonideal semiconductor characteristics. Moreover, the switching loss in the commutation between two switches is usually higher than the one in the commutation between a switch and the freewheeling diode. Taking into consideration both types of commutations, the switching loss of the buck rectifier is then modeled and the analytical equations are derived for four space vector modulation schemes. According to the analysis, each modulation scheme has its own field for high-efficiency application. The most advantageous modulation scheme is identified in this paper for each of the device combinations investigated.

Nonlinear, voltage-dependent capacitances of power semiconductor devices are capable of having significant impact on the operation of switched-mode power converters. Particularly at high switching frequency, these nonlinearities play a significant role in determining switching times, losses, and converter dynamics during switching transitions. In order to accommodate the well-established design and analysis techniques commonly used for linear circuits, this paper examines the nonlinear voltage-dependence of switching device capacitances and proposes a circuit-oriented analysis technique that allows the parasitic capacitances to be replaced with linear equivalents. The multitude of developed equivalents are verified through full nonlinear simulation in both MATLAB/Simulink and SPICE, as well as through experimental results.

This paper presents the design and implementation of a single-phase on-board bidirectional plug-in electric vehicle (PEV) charger that can provide reactive power support to the utility grid in addition to charging the vehicle battery. The topology consists of two-stages: a full-bridge ac-dc boost converter; and a half-bridge bidirectional dc-dc converter. The charger operates in two quadrants in the active-reactive power (PQ) power plane with five different operation modes (i.e., charging-only, charging-capacitive, charging-inductive, capacitive-only, and inductive-only). This paper also presents a unified controller to follow utility PQ commands in a smart grid environment. The cascaded two-stage system controller receives active and reactive power commands from the grid, and results in line current and battery charging current references while also providing a stable dynamic response. The vehicle's battery is not affected during reactive power operation in any of the operation modes. Testing the unified system controller with a 1.44 kVA experimental charger design demonstrates the successful implementation of reactive power support functionality of PEVs for future smart grid applications.

Nonlinear, voltage-dependent capacitances of power semiconductor devices are capable of having significant impact on the operation of switched-mode power converters. Particularly at high switching frequency, these nonlinearities play a significant role in determining switching times, losses, and converter dynamics during switching transitions. In order to accommodate the well-established design and analysis techniques commonly used for linear circuits, this paper examines the nonlinear voltage-dependence of switching device capacitances and proposes a circuit-oriented analysis technique that allows the parasitic capacitances to be replaced with linear equivalents. The multitude of developed equivalents are verified through full nonlinear simulation in both MATLAB/Simulink and SPICE, as well as through experimental results.

This paper presents the design and implementation of a single-phase on-board bidirectional plug-in electric vehicle (PEV) charger that can provide reactive power support to the utility grid in addition to charging the vehicle battery. The topology consists of two-stages: a full-bridge ac-dc boost converter; and a half-bridge bidirectional dc-dc converter. The charger operates in two quadrants in the active-reactive power (PQ) power plane with five different operation modes (i.e., charging-only, charging-capacitive, charging-inductive, capacitive-only, and inductive-only). This paper also presents a unified controller to follow utility PQ commands in a smart grid environment. The cascaded two-stage system controller receives active and reactive power commands from the grid, and results in line current and battery charging current references while also providing a stable dynamic response. The vehicle's battery is not affected during reactive power operation in any of the operation modes. Testing the unified system controller with a 1.44 kVA experimental charger design demonstrates the successful implementation of reactive power support functionality of PEVs for future smart grid applications.

A situational awareness system is essential to provide accurate understanding of power system dynamics, such that proper actions can be taken in real time in response to system disturbances and to avoid cascading blackouts. Event analysis has been an important component in any situational awareness system. However, most state-of-the-art techniques can only handle single event analysis. This paper tackles the challenging problem of multiple event detection and recognition. We propose a new conceptual framework, referred to as event unmixing, where we consider real-world events mixtures of more than one constituent root event. This concept is a key enabler for analysis of events to go beyond what are immediately detectable in a system, providing high-resolution data understanding at a finer scale. We interpret the event formation process from a linear mixing perspective and propose an innovative nonnegative sparse event unmixing (NSEU) algorithm for multiple event separation and temporal localization. The proposed framework has been evaluated using both PSS/E simulated cases and real event cases collected from the frequency disturbance recorders (FDRs) of the Frequency Monitoring Network (FNET). The experimental results demonstrate that the framework is reliable to detect and recognize multiple cascading events as well as their time of occurrence with high accuracy.

This paper presents an active gate driver (AGD) for IGBT modules to improve their overall performance under normal condition as well as fault condition. Specifically, during normal switching transients, a di/dt feedback controlled current source and current sink is introduced together with a push-pull buffer for dynamic gate current control. Compared to a conventional gate drive strategy, the proposed one has the capability of reducing the switching loss, delay time, and Miller plateau duration during turn-on and turn-off transient without sacrificing current and voltage stress. Under overcurrent condition, it provides a fast protection function for IGBT modules based on the evaluation of fault current level through the di/dt feedback signal. Moreover, the AGD features flexible protection modes, which overcomes the interruption of converter operation in the event of momentary short circuits. A step-down converter is built to evaluate the performance of the proposed driving schemes under various conditions, considering variation of turn-on/off gate resistance, current levels, and short-circuit fault types. Experimental results and detailed analysis are presented to verify the feasibility of the proposed approach.

In a phase-leg configuration, the high-switching-speed performance of silicon carbide (SiC) devices is limited by the interaction between the upper and lower devices during the switching transient (crosstalk), leading to additional switching losses and overstress of the power devices. To utilize the full potential of fast SiC devices, this paper proposes two gate assist circuits to actively suppress crosstalk on the basis of the intrinsic properties of SiC power devices. One gate assist circuit employs an auxiliary transistor in series with a capacitor to mitigate crosstalk by gate loop impedance reduction. The other gate assist circuit consists of two auxiliary transistors with a diode to actively control the gate voltage for crosstalk elimination. Based on CREE CMF20120D SiC MOSFETs, the experimental results show that both active gate drivers are effective to suppress crosstalk, enabling turn-on switching losses reduction by up to 17%, and negative spurious gate voltage minimization without the penalty of decreasing the switching speed. Furthermore, both gate assist circuits, even without a negative isolated power supply, are more effective in improving the switching behavior of SiC devices in comparison to the conventional gate driver with a -2 V turn-off gate voltage. Accordingly, the proposed active gate assist circuits are simple, efficient, and cost-effective solutions for crosstalk suppression.

This paper presents an improved phase disposition pulsewidth modulation (PWM) (PDPWM) for the modular multilevel converter (MMC) which is based on the selective loop bias mapping (SLBM) method. Its main idea is to change the bias of the PDPWM carrier wave cycling according to the balance situation of the system. This new modulation method can operate at symmetric condition to generate an output voltage with as many as 2N + 1 levels, and by SLBM, the voltages of the upper/lower arm capacitors can be well balanced. Compared to carrier phase-shifted PWM, this method is more easily to be realized and has much stronger dynamic regulation ability. Specially, this method has no issues of sorting, which makes it suitable for MMC with a large number of submodules in one leg. With simulation and experiments, the validity of the proposed method has been shown.

This paper proposes a novel packaging method for insulated-gate bipolar transistor (IGBT) modules based on the concepts of P-cell and N-cell. The novel packaging reduces the stray inductance in the current commutation path in a phase-leg module and hence improves the switching behavior. A P-cell- and N-cell-based module and a conventional module are designed. Using finite-element-analysis-based Ansys Q3D Extractor, electromagnetic simulations are conducted to extract the stray inductance from the two modules. Two prototype phase-leg modules based on the two different designs are fabricated. The parasitics are measured using a precision impedance analyzer. Finally, a double pulse tester based-switching characterization is performed to illustrate the effect of stray inductance reduction in the proposed packaging design. The experimental results show the reduction in overshoot voltage with the proposed layout.

This paper presents a unified control method for the combined permanent magnet generator (PMG) and active rectifier that can be used in autonomous power systems such as more-electric aircraft requiring high power density and efficiency. With the proposed control, the system can function well without additional boost inductors and rotor position sensors. The design procedure for the control is presented, including current loops, a voltage loop, and a rotor position estimator loop. Simulation and experimental results show that both the dc-link voltage and the reactive power could be controlled effectively. A system efficiency optimization technique is proposed by selecting the permanent magnet flux linkage and determining the operating points at various load and speed conditions. The power density and efficiency of the PMG and active rectifier system are improved with the unified control.

In this paper, the analysis of space vector modulation of a three-phase/wire/level Vienna rectifier is conducted, according to which the implementation of the equivalent carrier-based pulsewidth modulation is deduced theoretically within each separated sector in the diagram of vectors. The voltage balancing ability of dc-link neutral point, which depends on the uneven distribution of short vectors, is analyzed as well. An adaptive and robust controller to balance the output voltage under the unbalanced load limit for different modulation indices is proposed. The proposed controller can work at wide range of unbalanced load condition as well. Furthermore, the maximum unbalanced load is deduced versus the modulation index m when the converter works in unity power factor. An experimental prototype of 2.5 kW was built to verify the effectiveness of the theoretical analysis. Finally, the tested unbalanced limit of outputs for the experimental platform was given under different modulation indices. The output voltages for dual bus are balanced, and the theoretical analysis is verified.

Current ripple is generated by pulse width modulation (PWM) switching in multiphase voltage source converters (VSCs). This letter introduces a general and fast current ripple prediction method for multiphase VSCs with arbitrary phase numbers. An equivalent converter-load model is derived for the n -phase converter system. By combining the common-mode voltage of both converter terminal and load, the equivalent circuit for each phase can be modeled. The voltage dropping on the ac inductor can be calculated for the 2 n + 2 zones in each switching cycle based on the equivalent circuit for each phase. Then the current ripple can be reconstructed based on the linear di/dt model in each zone. Simulation examples of five- and six-phase converters prove that the current prediction method is accurate. With this real-time prediction method, the current ripple can be controlled in application. An application example of five-phase variable switching frequency PWM is introduced to control the peak current ripple and reduce the switching losses.

A three-phase nonlinear load emulator using a power electronic converter is presented in this study. The proposed nonlinear load emulator is intended to be used in an ultrawide-area grid transmission network emulator, also called hardware testbed (HTB). The emulator converter is controlled in rectifier mode to act as the real nonlinear three-phase diode rectifier load. This paper presents an accurate controller for the nonlinear load emulator based on a three-phase diode rectifier system to be used in the HTB. This study also demonstrates simulation and experimental results for verification of the proposed controller.

An analytical model has been developed for predicting the forced-air cooling system performance, including a detailed optimization process to minimize the total weight. With a design example in a high-density high-temperature SiC converter, the presented design method was verified through numerical simulations and experiments.

The three-phase pulsewidth-modulation (PWM) converter is one of the most widely used topologies for power conversion. In order to design PWM methods, the influence of PWM methods on the current ripple is needed. This paper studies the current ripple of a three-phase PWM converter with general PWM methods for the design and control of this kind of converter. The current ripple is analyzed with eight different Thevenin equivalent circuits for the eight different voltage vectors. Then, the current-ripple slope and effective time could be achieved for every period. The current ripple could be predicted with both peak and rms values. Analytical predicted results show that discontinuous PWM could generate obviously bigger current ripples than space vector PMW for both peak and rms values with the same conditions. Simulation and experiments are built to verify the analytical results, proving that the theoretical prediction is valid. This analysis provides the basis for the design and control of the PWM method for converters.

A thermally integrated packaging structure for an all silicon carbide (SiC) power module was used to realize highly efficient cooling of power semiconductor devices through direct bonding of the power stage and a cold baseplate. The prototype power modules composed of SiC metal-oxide-semiconductor field-effect transistors and Schottky barrier diodes demonstrate significant improvements such as low-power losses and low-thermal resistance. Direct comparisons to their silicon counterparts, which are composed of insulated gate bipolar transistors and PiN diodes, as well as conventional thermal packaging, were experimentally performed. The advantages of this SiC module in efficiency and power density for power electronics systems have also been identified, with clarification of the SiC attributes and packaging advancements.

To further reduce system costs and package volumes of hybrid electric vehicles, it is important to optimize the power module and associated cooling system. This paper reports the thermal performance evaluation and analysis of three commercial power modules and a proposed planar module with different cooling system. Results show that power electronics can be better merged with the mechanical environment. Experiments and simulations were conducted to help further optimization.

A multilayer planar interconnection structure was used for the packaging of liquid-cooled automotive power modules. The power semiconductor switch dies are sandwiched between two symmetric substrates, providing planar electrical interconnections and insulation. Two minicoolers are directly bonded to the outside of these substrates, allowing double-sided, integrated cooling. The power switch dies are orientated in a face-up/face-down 3-D interconnection configuration to form a phase leg. The bonding areas between the dies and substrates, and the substrates and coolers are designed to use identical materials and are formed in one heating process. A special packaging process has been developed so that high-efficiency production can be implemented. Incorporating high-efficiency cooling and low-loss electrical interconnections allows dramatic improvements in systems' cost, and electrical conversion efficiency. These features are demonstrated in a planar bond-packaged prototype of a 200 A/1200 V phase-leg power module made of silicon (Si) insulated gate bipolar transistor and PiN diodes.

In this paper, the analysis of space vector modulation of a three-phase/wire/level Vienna rectifier is conducted, according to which the implementation of the equivalent carrier-based pulsewidth modulation is deduced theoretically within each separated sector in the diagram of vectors. The voltage balancing ability of dc-link neutral point, which depends on the uneven distribution of short vectors, is analyzed as well. An adaptive and robust controller to balance the output voltage under the unbalanced load limit for different modulation indices is proposed. The proposed controller can work at wide range of unbalanced load condition as well. Furthermore, the maximum unbalanced load is deduced versus the modulation index m when the converter works in unity power factor. An experimental prototype of 2.5 kW was built to verify the effectiveness of the theoretical analysis. Finally, the tested unbalanced limit of outputs for the experimental platform was given under different modulation indices. The output voltages for dual bus are balanced, and the theoretical analysis is verified.

Current ripple is generated by pulse width modulation (PWM) switching in multiphase voltage source converters (VSCs). This letter introduces a general and fast current ripple prediction method for multiphase VSCs with arbitrary phase numbers. An equivalent converter-load model is derived for the n -phase converter system. By combining the common-mode voltage of both converter terminal and load, the equivalent circuit for each phase can be modeled. The voltage dropping on the ac inductor can be calculated for the 2 n + 2 zones in each switching cycle based on the equivalent circuit for each phase. Then the current ripple can be reconstructed based on the linear di/dt model in each zone. Simulation examples of five- and six-phase converters prove that the current prediction method is accurate. With this real-time prediction method, the current ripple can be controlled in application. An application example of five-phase variable switching frequency PWM is introduced to control the peak current ripple and reduce the switching losses.

A three-phase nonlinear load emulator using a power electronic converter is presented in this study. The proposed nonlinear load emulator is intended to be used in an ultrawide-area grid transmission network emulator, also called hardware testbed (HTB). The emulator converter is controlled in rectifier mode to act as the real nonlinear three-phase diode rectifier load. This paper presents an accurate controller for the nonlinear load emulator based on a three-phase diode rectifier system to be used in the HTB. This study also demonstrates simulation and experimental results for verification of the proposed controller.

An analytical model has been developed for predicting the forced-air cooling system performance, including a detailed optimization process to minimize the total weight. With a design example in a high-density high-temperature SiC converter, the presented design method was verified through numerical simulations and experiments.

The three-phase pulsewidth-modulation (PWM) converter is one of the most widely used topologies for power conversion. In order to design PWM methods, the influence of PWM methods on the current ripple is needed. This paper studies the current ripple of a three-phase PWM converter with general PWM methods for the design and control of this kind of converter. The current ripple is analyzed with eight different Thevenin equivalent circuits for the eight different voltage vectors. Then, the current-ripple slope and effective time could be achieved for every period. The current ripple could be predicted with both peak and rms values. Analytical predicted results show that discontinuous PWM could generate obviously bigger current ripples than space vector PMW for both peak and rms values with the same conditions. Simulation and experiments are built to verify the analytical results, proving that the theoretical prediction is valid. This analysis provides the basis for the design and control of the PWM method for converters.

A thermally integrated packaging structure for an all silicon carbide (SiC) power module was used to realize highly efficient cooling of power semiconductor devices through direct bonding of the power stage and a cold baseplate. The prototype power modules composed of SiC metal-oxide-semiconductor field-effect transistors and Schottky barrier diodes demonstrate significant improvements such as low-power losses and low-thermal resistance. Direct comparisons to their silicon counterparts, which are composed of insulated gate bipolar transistors and PiN diodes, as well as conventional thermal packaging, were experimentally performed. The advantages of this SiC module in efficiency and power density for power electronics systems have also been identified, with clarification of the SiC attributes and packaging advancements.

To further reduce system costs and package volumes of hybrid electric vehicles, it is important to optimize the power module and associated cooling system. This paper reports the thermal performance evaluation and analysis of three commercial power modules and a proposed planar module with different cooling system. Results show that power electronics can be better merged with the mechanical environment. Experiments and simulations were conducted to help further optimization.

A multilayer planar interconnection structure was used for the packaging of liquid-cooled automotive power modules. The power semiconductor switch dies are sandwiched between two symmetric substrates, providing planar electrical interconnections and insulation. Two minicoolers are directly bonded to the outside of these substrates, allowing double-sided, integrated cooling. The power switch dies are orientated in a face-up/face-down 3-D interconnection configuration to form a phase leg. The bonding areas between the dies and substrates, and the substrates and coolers are designed to use identical materials and are formed in one heating process. A special packaging process has been developed so that high-efficiency production can be implemented. Incorporating high-efficiency cooling and low-loss electrical interconnections allows dramatic improvements in systems' cost, and electrical conversion efficiency. These features are demonstrated in a planar bond-packaged prototype of a 200 A/1200 V phase-leg power module made of silicon (Si) insulated gate bipolar transistor and PiN diodes.

The low power losses of silicon carbide (SiC) devices provide new opportunities to implement an ultra high-efficiency front-end rectifier for data center power supplies based on a 400-Vdc power distribution architecture, which requires high conversion efficiency in each power conversion stage. This paper presents a 7.5-kW high-efficiency three-phase buck rectifier with 480-Vac,rms input line-to-line voltage and 400-Vdc output voltage using SiC MOSFETs and Schottky diodes. To estimate power devices' losses, which are the dominant portion of total loss, the method of device evaluation and loss calculation is proposed based on a current source topology. This method simulates the current commutation process and estimates devices' losses during switching transients considering devices with and without switching actions in buck rectifier operation. Moreover, the power losses of buck rectifiers based on different combinations of 1200-V power devices are compared. The investigation and comparison demonstrate the benefits of each combination, and the lowest total loss in the all-SiC rectifier is clearly shown. A 7.5-kW prototype of the all-SiC three-phase buck rectifier using liquid cooling is fabricated and tested, with filter design and switching frequency chosen based on loss minimization. A full-load efficiency value greater than 98.5% is achieved.

In this paper, a fully integrated silicon carbide (SiC)-based six-pack power module is designed and developed. With 1200-V, 100-A module rating, each switching element is composed of four paralleled SiC junction gate field-effect transistors (JFETs) with two antiparallel SiC Schottky barrier diodes. The stability of the module assembly processes is confirmed with 1000 cycles of -40°C to +200°C thermal shock tests with 1.3°C/s temperature change. The static characteristics of the module are evaluated and the results show 55 mΩ on-state resistance of the phase leg at 200°C junction temperature. For switching performances, the experiments demonstrate that while utilizing a 650-V voltage and 60-A current, the module switching loss decreases as the junction temperature increases up to 150°C. The test setup over a large temperature range is also described. Meanwhile, the shoot-through influenced by the SiC JFET internal capacitance as well as package parasitic inductances are discussed. Additionally, a liquid cooled three-phase inverter with 22.9 cm × 22.4 cm × 7.1 cm volume and 3.53-kg weight, based on this power module, is designed and developed for electric vehicle and hybrid electric vehicle applications. A conversion efficiency of 98.5% is achieved at 10 kHz switching frequency at 5 kW output power. The inverter is evaluated with coolant temperature up to 95°C successfully.

This paper analyzes pulsewidth modulation (PWM) methods' impact on the motor drives' common-mode (CM) noise current and CM choke saturation. The modulation in the motor drive terminals serves as the CM noise source. A few improved PWM methods could reduce the CM voltage amplitude in comparison with the conventional space vector PWM and discontinuous PWM. However, some harmonics of the improved PWM methods increase when considering the spectrum. Because the CM loop of the motor drive system is an L-R-C circuit which has its resonant frequency, the CM noise current is highly influenced by the noise near the resonant frequency. This paper studies the CM current with different PWM methods and claims that the design of PWM methods and switching frequency should be together with the CM loop impedance. Reduced CM voltage does not mean reduced CM current. With a CM choke to attenuate the CM noise, the choke size is determined by the CM volt-seconds on the choke. This paper studies the general case and the worst case of the choke size. The conclusions are supported by simulation and experimental results.

Unbalanced grids introduce performance deterioration for Vienna rectifier topology by producing twice fundamental frequency ripples in dc-link voltage and input active/reactive power. A common current reference generation for the purpose of eliminating the input power ripple, such as dual-frame hybrid vector control, can maintain constant input power and eliminate ripples in dc-link voltage under light voltage unbalanced grids. Under severe unbalanced grids, this type of a control method will fail to work. This paper first analyzes the theoretical operation area of a constant power control method under unbalanced grids, and then a novel control method is proposed. The proposed control method can work under severe unbalanced grids by injecting a small amount of input power ripple and balance the performance of working area and output dc voltage ripples. Finally, the experiment results using the constant power control method are given and validate the performance of the proposed control method.

A new approach for modulation of an 11-level cascade multilevel inverter using selective harmonic elimination is presented in this paper. The dc sources feeding the multilevel inverter are considered to be varying in time, and the switching angles are adapted to the dc source variation. This method uses genetic algorithms to obtain switching angles offline for different dc source values. Then, artificial neural networks are used to determine the switching angles that correspond to the real-time values of the dc sources for each phase. This implies that each one of the dc sources of this topology can have different values at any time, but the output fundamental voltage will stay constant and the harmonic content will still meet the specifications. The modulating switching angles are updated at each cycle of the output fundamental voltage. This paper gives details on the method in addition to simulation and experimental results.

This paper proposed an improved phase disposition pulse width modulation (PDPWM) for a modular multilevel inverter which is used for Photovoltaic grid connection. This new modulation method is based on selective virtual loop mapping, to achieve dynamic capacitor voltage balance without the help of an extra compensation signal. The concept of virtual submodule (VSM) is first established, and by changing the loop mapping relationships between the VSMs and the real submodules, the voltages of the upper/lower arm's capacitors can be well balanced. This method does not requiring sorting voltages from highest to lowest, and just identifies the MIN and MAX capacitor voltage's index which makes it suitable for a modular multilevel converter with a large number of submodules in one arm. Compared to carrier phase-shifted PWM (CPSPWM), this method is more easily to be realized in field-programmable gate array and has much stronger dynamic regulation ability, and is conducive to the control of circulating current. Its feasibility and validity have been verified by simulations and experiments.

A Si insulated-gate bipolar transistor (IGBT) phase-leg module is developed for operating at 200°C in hybrid electric vehicle applications utilizing the high temperature packaging technologies and appropriate thermal management. The static and switching electrical characteristics of the fabricated power module are tested at various temperatures, showing that the module can operate reliably with increased but acceptable losses at 200°C. The criterion on thermal performance is given to prevent thermal runaway caused by fast increase of the leakage current during a high temperature operation. Afterward, the thermal management system is designed to meet the criterion, the performance of which is evaluated with experiment. Furthermore, two temperature-sensitive electrical parameters, on-state voltage drop and the switching time, are employed for thermal impedance characterization and the junction temperature measurement during converter operation, respectively. Finally, a 10-kW buck converter prototype composed of the module assembly is built and operated at the junction temperature up to 200°C. The experimental results demonstrate the feasibility of operating Si device-based converters continuously at 200°C.

In order to satisfy the high-density requirement and harsh thermal conditions while reducing cost in future electric and hybrid electric vehicles (HEV), a systematic study of a 1200-V trench-gate field-stop Si insulated gate bipolar transistor (IGBT) operating up to 200°C is performed to determine its feasibility, issues, and application guideline. The device forward conduction characteristics, leakage current, and switching performance are evaluated at various temperatures. Based on the device characterization, the impact of the increased junction temperature on a traction drive converter loss and thermal management is analyzed. It is shown that by extending the device junction temperature to 200°C, the additional 65°C coolant loop can be eliminated without compromising power density and thermal management design. Furthermore, the possible failure mechanisms including latching, short circuit fault, and avalanche capability are tested at elevated temperatures. The criteria considering thermal stability, thermal management, short circuit capability, and avalanche capability are given at 200°C to ensure the safe and reliable operation of Si IGBTs.

This paper presents a front-end three-phase ac/dc power factor correction rectifier, which is based on the three-level bidirectional-switch Vienna topology. On one hand, the rectifier is designed to operate in continuous-conduction mode (CCM) at full power. However, at reduced load, it operates in discontinuous-conduction mode (DCM). On the other hand, with reduced input inductance, the DCM mode occurs even when the rectifier operates at full power. In this paper, the digitized feedfoward compensation method is proposed for the rectifier to reduce the impact of the switch between DCM and CCM. The theoretical analysis of the proposed method is deduced; furthermore, the control design strategy is given. The experimental results are obtained by using a digitally controlled Vienna rectifier, which validated the proposed compensation method.

High-temperature (HT) converters have gained importance in industrial applications where the converters operate in a harsh environment, such as in hybrid electrical vehicles, aviation, and deep-earth petroleum exploration. These environments require the converter to have not only HT semiconductor devices (made of SiC or GaN), but also reliable HT packaging, HT gate drives, and HT control electronics. This paper describes a detailed design process for an HT SiC three-phase PWM rectifier that can operate at ambient temperatures above 100°C. SiC HT planar structure packaging is designed for the main semiconductor devices, and an edge-triggered HT gate drive is also proposed to drive the designed power module. The system is designed to make use of available HT components, including the passive components, silicon-on-insulator chips, and auxiliary components. Finally, a 1.4 kW lab prototype is tested in a harsh environment for verification.

This paper presents a summary of the available single-phase ac-dc topologies used for EV/PHEV, level-1 and -2 on-board charging and for providing reactive power support to the utility grid. It presents the design motives of single-phase on-board chargers in detail and makes a classification of the chargers based on their future vehicle-to-grid usage. The pros and cons of each different ac-dc topology are discussed to shed light on their suitability for reactive power support. This paper also presents and analyzes the differences between charging-only operation and capacitive reactive power operation that results in increased demand from the dc-link capacitor (more charge/discharge cycles and increased second harmonic ripple current). Moreover, battery state of charge is spared from losses during reactive power operation, but converter output power must be limited below its rated power rating to have the same stress on the dc-link capacitor.

Compared with the widely used constant switching frequency pulse-width-modulation (PWM) method, variable switching frequency PWM can benefit more because of the extra freedom. Based on the analytical expression of current ripple of three-phase converters, variable switching frequency control methods are proposed to satisfy different ripple requirements. Switching cycle Ts is updated in DSP in every interruption period based on the ripple requirement. Two methods are discussed in this paper. The first method is designed to arrange the current ripple peak value within a certain value and can reduce the equivalent switching frequency and electromagnetic interference (EMI) noise; the second method is designed to keep ripple current RMS value constant and reduce the EMI noise. Simulation and experimental results show that variable switching frequency control could improve the performance of EMI and efficiency without impairing the power quality.

This paper presents a front-end three-phase ac/dc power factor correction rectifier, which is based on the three-level bidirectional-switch Vienna topology. On one hand, the rectifier is designed to operate in continuous-conduction mode (CCM) at full power. However, at reduced load, it operates in discontinuous-conduction mode (DCM). On the other hand, with reduced input inductance, the DCM mode occurs even when the rectifier operates at full power. In this paper, the digitized feedfoward compensation method is proposed for the rectifier to reduce the impact of the switch between DCM and CCM. The theoretical analysis of the proposed method is deduced; furthermore, the control design strategy is given. The experimental results are obtained by using a digitally controlled Vienna rectifier, which validated the proposed compensation method.

High-temperature (HT) converters have gained importance in industrial applications where the converters operate in a harsh environment, such as in hybrid electrical vehicles, aviation, and deep-earth petroleum exploration. These environments require the converter to have not only HT semiconductor devices (made of SiC or GaN), but also reliable HT packaging, HT gate drives, and HT control electronics. This paper describes a detailed design process for an HT SiC three-phase PWM rectifier that can operate at ambient temperatures above 100°C. SiC HT planar structure packaging is designed for the main semiconductor devices, and an edge-triggered HT gate drive is also proposed to drive the designed power module. The system is designed to make use of available HT components, including the passive components, silicon-on-insulator chips, and auxiliary components. Finally, a 1.4 kW lab prototype is tested in a harsh environment for verification.

This paper presents a summary of the available single-phase ac-dc topologies used for EV/PHEV, level-1 and -2 on-board charging and for providing reactive power support to the utility grid. It presents the design motives of single-phase on-board chargers in detail and makes a classification of the chargers based on their future vehicle-to-grid usage. The pros and cons of each different ac-dc topology are discussed to shed light on their suitability for reactive power support. This paper also presents and analyzes the differences between charging-only operation and capacitive reactive power operation that results in increased demand from the dc-link capacitor (more charge/discharge cycles and increased second harmonic ripple current). Moreover, battery state of charge is spared from losses during reactive power operation, but converter output power must be limited below its rated power rating to have the same stress on the dc-link capacitor.

Compared with the widely used constant switching frequency pulse-width-modulation (PWM) method, variable switching frequency PWM can benefit more because of the extra freedom. Based on the analytical expression of current ripple of three-phase converters, variable switching frequency control methods are proposed to satisfy different ripple requirements. Switching cycle Ts is updated in DSP in every interruption period based on the ripple requirement. Two methods are discussed in this paper. The first method is designed to arrange the current ripple peak value within a certain value and can reduce the equivalent switching frequency and electromagnetic interference (EMI) noise; the second method is designed to keep ripple current RMS value constant and reduce the EMI noise. Simulation and experimental results show that variable switching frequency control could improve the performance of EMI and efficiency without impairing the power quality.

Silicon Carbide (SiC) devices have obvious advantages compared with conventional Si devices, and especially so at high temperatures. This paper aims at developing a method for the characterization of SiC JFET conduction and switching losses at high temperatures as well as the calculation of semiconductor losses in SiC JFET-based converters. To this end, the steady-state performance of SiC JFET and Schottky diodes at different temperatures is studied, and an improved conduction loss evaluation is proposed considering the bidirectional conduction paths of the JFET. Specifically, a SiC JFET bridge test bed is built to measure the switching losses at different temperatures with and without antiparallel diodes, where experimental results show that using SiC Schottky diodes in antiparallel eliminates the reverse recovery of the JFET body diode, improving the switching behavior and reducing the losses of the devices. Further, these test results are used to estimate the losses of a 10-kW ac-dc-ac converter, which shows that the use of Schottky diodes as freewheeling devices helps reduce both conduction and switching losses, presenting an even greater reduction at higher operating temperatures.

High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 °C. This new gate driver prototype has been designed and implemented in a 0.8 μm, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 °C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature (≥220 °C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 μW for operating temperature up to 200 °C.

This paper presents an alternative to the traditional dc-dc converter interfacing the battery with the inverter dc bus in plug-in hybrid electric vehicle (HEV) traction drives. The boost converter used in commercial HEVs meets with obstacles when it comes to upgrading the power rating and achieving high efficiency while downsizing the converter. A four-level flying-capacitor dc-dc converter is explored that can overcome these drawbacks by dramatically reducing the inductance requirement. A special case of the four-level converter, the 3X dc-dc converter, operates at three discrete output/input voltage ratios, thus further reducing the inductance requirement to a minimal value (almost zero). When further compared to its switched-capacitor dc-dc converter counterparts, the 3X dc-dc converter can be operated at variable output/input voltage ratios without sacrificing efficiency, and it lowers the capacitance requirement by utilizing the parasitic inductance. The operating principle, current ripple analysis, the transient control to limit the inrush current, and power loss analysis are introduced. Experimental results of a 55-kW prototype are provided to demonstrate the principle and analysis of this topology.

This paper presents a complete design methodology for the sensorless vector control of permanent-magnet synchronous machine (PMSM) motor drives in fan-type applications. The proposed strategy is built over a linear asymptotic state observer used to estimate the PMSM back EMF and a novel tracking controller based on a phase-locked loop system, which, by synchronizing the estimated and actual d-q frames, estimates the rotor speed and position. This paper presents the complete derivation of all associated control loops, namely, state observer; tracking controller; d-q-axis current regulator; speed controller; an antisaturation control loop, which provides inherent operation in the flux-weakening region; and all corresponding antiwindup loops. Detailed design rules are provided for each of these loops, respectively verified through time-domain simulations, frequency-response analysis, and experimental results using a three-phase 7.5-kW PMSM motor drive, validating both the design methodology and the expected performance attained by the proposed control strategy.

This paper presents a control method to minimize the total flux in the integrated interphase inductors of paralleled, interleaved three-phase two-level voltage-source converters (VSCs) using discontinuous space vector modulation (DPWM). Specifically, different inductor structures used to limit circulating currents are introduced and compared, and the structure and flux distribution of two types of integrated interphase inductors are analyzed in detail. Based on that, a control method to minimize the total flux in such integrated interphase inductor is proposed for a parallel converter system using interleaved DPWM. The method eliminates the circulating currents during the peak range of the converter output currents; hence the total flux is minimized and only determined by the system load requirements. This control method introduces very limited additional switching actions, which do not significantly affect the converter electrothermal design. Experimental results verify the analysis and the feasibility of the proposed control method.

This paper presents an improved asymmetric space vector modulation (ASVM) for two-level voltage source converters (VSCs) when the switching frequency is as low as nine times of line frequency. By adding two pulses in each line cycle when the fundamental voltage crosses zero, the total harmonic distortion (THD) of output current can be reduced significantly. The penalty of additional switching loss is very limited for high power factor operation. The applications of the improved ASVM in a single VSC or in two interleaved VSCs are shown, respectively. With the optimization of the duration and position of the additional pulses, the ac current THD can be reduced to as low as 50% for single VSC and even lower to less than 25% for interleaved VSCs systems. Such THD reduction has close relationship with space vectors' position, modulation index, and interleaving angle. Improved ASVM can also reduce the amplitude of circulating current in the interleaved VSCs, leading to smaller interphase inductors. Finally, the weights of total inductors needed to meet the same THD requirement are compared to demonstrate the benefits of improved ASVM when different pulsewidth modulation schemes are used. The analysis results are verified by experiments on a demo system.

Robust system control design and seamless transition between various modes of operation are paramount for multifunctional converters in microgrid systems. This paper proposes a control system for single-phase bidirectional PWM converters for residential power level microgrid systems which is robust and can tolerate transitions between the different modes of operation. This is achieved by means of a common inner ac current-loop. Each of the operating modes has an individually designed outer loop performing the corresponding regulation tasks, most commonly including the ac voltage and the dc voltage regulation. A modified , phase-locked loop (PLL) system is used for system-level operation with both small steady-state error and fast response; and a novel islanding detection algorithm based on PLL stability is proposed to facilitate the transition between grid-connected mode and stand-alone mode. Finally, a frequency-response based design procedure for the proposed control system is presented in detail for all operating modes, and its performance is verified experimentally using a DSP-controlled 6 kW 120 V rms (ac)/ 300 V (dc) laboratory converter prototype.

Fault detection and protection is an important design aspect for any power converter, especially in high-power high-voltage applications, where cost of failure can be high. The three-level dc-dc converter and its varied derivatives are attractive topologies in high-voltage high-power converter applications. The protection method can not only prevent the system failure against unbalanced voltage stresses on the switches, but also provide a remedy for the system as faults occur and save the remaining components. The three-level converter is subject to voltage unbalance in certain abnormal conditions, which can result in switch overvoltage and system failure. The reasons for the unbalanced voltage stresses are fully investigated and categorized. The solutions to each abnormal condition are introduced. In addition to the voltage unbalance, the three-level converters can be protected against multiple faults by the proposed protection method through monitoring the flying capacitor voltage. Phenomena associated with each fault are thoroughly analyzed and summarized. The protection circuit is simple and can be easily implemented, while it can effectively protect the three-level converters and its derivatives, which has been verified by the experiment with a three-level parallel resonant converter.

This paper presents a reliability-oriented design (ROD) procedure for three-phase power converters in aircraft applications. These require the highest reliability levels for all its components-as high as space applications; hence the need to maximize the reliability of three-phase power converters, which are in increasing demand and use in commercial and military aircrafts as a result of the more-electric aircraft (MEA) initiative. Specifically, the proposed procedure takes reliability up-front in the design process of power converters, carrying out the design in three steps. First, the identification of critical system components; second, the assessment of reliability factors such as risk analysis, failure mode analysis, and fishbone diagrams; and third, the actual design, which is carried out by minimizing system complexity and stress, and by the use of the most reliable components, materials, and structures. To this end, reliability models were developed for all critical components based on the military handbook MIL-HDBK-217F, and field and vendor data. For verification purposes, the paper includes the ROD of a 60 kW three-phase power converter for aircraft applications together with experimental results of the prototype constructed.

This paper presents an alternative to the traditional dc-dc converter interfacing the battery with the inverter dc bus in plug-in hybrid electric vehicle (HEV) traction drives. The boost converter used in commercial HEVs meets with obstacles when it comes to upgrading the power rating and achieving high efficiency while downsizing the converter. A four-level flying-capacitor dc-dc converter is explored that can overcome these drawbacks by dramatically reducing the inductance requirement. A special case of the four-level converter, the 3X dc-dc converter, operates at three discrete output/input voltage ratios, thus further reducing the inductance requirement to a minimal value (almost zero). When further compared to its switched-capacitor dc-dc converter counterparts, the 3X dc-dc converter can be operated at variable output/input voltage ratios without sacrificing efficiency, and it lowers the capacitance requirement by utilizing the parasitic inductance. The operating principle, current ripple analysis, the transient control to limit the inrush current, and power loss analysis are introduced. Experimental results of a 55-kW prototype are provided to demonstrate the principle and analysis of this topology.

This paper presents a complete design methodology for the sensorless vector control of permanent-magnet synchronous machine (PMSM) motor drives in fan-type applications. The proposed strategy is built over a linear asymptotic state observer used to estimate the PMSM back EMF and a novel tracking controller based on a phase-locked loop system, which, by synchronizing the estimated and actual d-q frames, estimates the rotor speed and position. This paper presents the complete derivation of all associated control loops, namely, state observer; tracking controller; d-q-axis current regulator; speed controller; an antisaturation control loop, which provides inherent operation in the flux-weakening region; and all corresponding antiwindup loops. Detailed design rules are provided for each of these loops, respectively verified through time-domain simulations, frequency-response analysis, and experimental results using a three-phase 7.5-kW PMSM motor drive, validating both the design methodology and the expected performance attained by the proposed control strategy.

This paper presents a control method to minimize the total flux in the integrated interphase inductors of paralleled, interleaved three-phase two-level voltage-source converters (VSCs) using discontinuous space vector modulation (DPWM). Specifically, different inductor structures used to limit circulating currents are introduced and compared, and the structure and flux distribution of two types of integrated interphase inductors are analyzed in detail. Based on that, a control method to minimize the total flux in such integrated interphase inductor is proposed for a parallel converter system using interleaved DPWM. The method eliminates the circulating currents during the peak range of the converter output currents; hence the total flux is minimized and only determined by the system load requirements. This control method introduces very limited additional switching actions, which do not significantly affect the converter electrothermal design. Experimental results verify the analysis and the feasibility of the proposed control method.

This paper presents an improved asymmetric space vector modulation (ASVM) for two-level voltage source converters (VSCs) when the switching frequency is as low as nine times of line frequency. By adding two pulses in each line cycle when the fundamental voltage crosses zero, the total harmonic distortion (THD) of output current can be reduced significantly. The penalty of additional switching loss is very limited for high power factor operation. The applications of the improved ASVM in a single VSC or in two interleaved VSCs are shown, respectively. With the optimization of the duration and position of the additional pulses, the ac current THD can be reduced to as low as 50% for single VSC and even lower to less than 25% for interleaved VSCs systems. Such THD reduction has close relationship with space vectors' position, modulation index, and interleaving angle. Improved ASVM can also reduce the amplitude of circulating current in the interleaved VSCs, leading to smaller interphase inductors. Finally, the weights of total inductors needed to meet the same THD requirement are compared to demonstrate the benefits of improved ASVM when different pulsewidth modulation schemes are used. The analysis results are verified by experiments on a demo system.

Robust system control design and seamless transition between various modes of operation are paramount for multifunctional converters in microgrid systems. This paper proposes a control system for single-phase bidirectional PWM converters for residential power level microgrid systems which is robust and can tolerate transitions between the different modes of operation. This is achieved by means of a common inner ac current-loop. Each of the operating modes has an individually designed outer loop performing the corresponding regulation tasks, most commonly including the ac voltage and the dc voltage regulation. A modified , phase-locked loop (PLL) system is used for system-level operation with both small steady-state error and fast response; and a novel islanding detection algorithm based on PLL stability is proposed to facilitate the transition between grid-connected mode and stand-alone mode. Finally, a frequency-response based design procedure for the proposed control system is presented in detail for all operating modes, and its performance is verified experimentally using a DSP-controlled 6 kW 120 V rms (ac)/ 300 V (dc) laboratory converter prototype.

Fault detection and protection is an important design aspect for any power converter, especially in high-power high-voltage applications, where cost of failure can be high. The three-level dc-dc converter and its varied derivatives are attractive topologies in high-voltage high-power converter applications. The protection method can not only prevent the system failure against unbalanced voltage stresses on the switches, but also provide a remedy for the system as faults occur and save the remaining components. The three-level converter is subject to voltage unbalance in certain abnormal conditions, which can result in switch overvoltage and system failure. The reasons for the unbalanced voltage stresses are fully investigated and categorized. The solutions to each abnormal condition are introduced. In addition to the voltage unbalance, the three-level converters can be protected against multiple faults by the proposed protection method through monitoring the flying capacitor voltage. Phenomena associated with each fault are thoroughly analyzed and summarized. The protection circuit is simple and can be easily implemented, while it can effectively protect the three-level converters and its derivatives, which has been verified by the experiment with a three-level parallel resonant converter.

This paper presents a reliability-oriented design (ROD) procedure for three-phase power converters in aircraft applications. These require the highest reliability levels for all its components-as high as space applications; hence the need to maximize the reliability of three-phase power converters, which are in increasing demand and use in commercial and military aircrafts as a result of the more-electric aircraft (MEA) initiative. Specifically, the proposed procedure takes reliability up-front in the design process of power converters, carrying out the design in three steps. First, the identification of critical system components; second, the assessment of reliability factors such as risk analysis, failure mode analysis, and fishbone diagrams; and third, the actual design, which is carried out by minimizing system complexity and stress, and by the use of the most reliable components, materials, and structures. To this end, reliability models were developed for all critical components based on the military handbook MIL-HDBK-217F, and field and vendor data. For verification purposes, the paper includes the ROD of a 60 kW three-phase power converter for aircraft applications together with experimental results of the prototype constructed.

Energy infrastructure is a critical underpinning of modern society that any compromise or sabotage of its secure and reliable operation has an enormous impact on people's daily lives and the national economy. The massive northeastern power blackout of August 2003 and the most recent Florida blackout have both revealed serious defects in both system-level management and device-level designs of the power grid in handling attacks. At the system level, the control area operators lack the capability to 1) obtain real-time status information of the vastly distributed equipment; 2) respond rapidly enough once events start to unravel; and 3) perform coordinated actions autonomously across the region. At the device level, the traditional hardware lacks the capability to 1) provide reliable frequency and voltage control according to system demands and 2) rapidly reconfigure the system to a secure state through switches and power-electronics based devices. These blackouts were a wake-up call for both the industry and academia to consider new techniques and system architecture design that can help assure the security and reliability of the power grid. In this paper, we present a hardware-in-the-loop reconfigurable system design with embedded intelligence and resilient coordination schemes at both local and system levels that would tackle the vulnerabilities of the grid. The new system design consists of five key components: 1) a location-centric hybrid system architecture that facilitates not only distributed processing but also coordination among geographically close devices; 2) the insertion of intelligence into power electronic devices at the lower level of the power grid to enable a more direct reconfiguration of the physical makeup of the grid; 3) the development of a robust collaboration algorithm among neighboring devices to handle possible faulty, missing, or incomplete information; 4) the design of distributed algorithms to better understand the local state of the power grid; and 5) the adoption of a control-theoretic real-time adaptation strategy to guarantee the availability of large distributed systems. Preliminary evaluation results showing the advantages of each component are provided. A phased implementation plan is also suggested at the end of the discussion.

This work approximates the selective harmonic elimination problem using artificial neural networks (ANNs) to generate the switching angles in an 11-level full-bridge cascade inverter powered by five varying dc input sources. Each of the five full bridges of the cascade inverter was connected to a separate 195-W solar panel. The angles were chosen such that the fundamental was kept constant and the low-order harmonics were minimized or eliminated. A nondeterministic method is used to solve the system for the angles and to obtain the data set for the ANN training. The method also provides a set of acceptable solutions in the space where solutions do not exist by analytical methods. The trained ANN is a suitable tool that brings a small generalization effect on the angles' precision and is able to perform in real time (50-/60-Hz time window).

To take full advantage of silicon carbide semiconductor devices, high-temperature device packaging needs to be developed. This paper describes potential defects from design and fabrication procedures, and presents a systematic electrical evaluation process to detect such defects. This systematic testing procedure can rapidly detect many defects and reduce the risk in high-temperature packaging testing. A multichip module development procedure that uses this testing procedure is also presented and demonstrated with an example.

It is well known that single-phase pulse width modulation rectifiers have second-order harmonic currents and corresponding ripple voltages on the dc bus. The low-frequency harmonic current is normally filtered using a bulk capacitor in the bus, which results in low power density. However, pursuing high power density in converter design is a very important goal in the aerospace applications. This paper studies methods for reducing the energy storage capacitor for single-phase rectifiers. The minimum ripple energy storage requirement is derived independently of a specific topology. Based on the minimum ripple energy requirement, the feasibility of the active capacitor's reduction schemes is verified. Then, we propose a bidirectional buck-boost converter as the ripple energy storage circuit, which can effectively reduce the energy storage capacitance. The analysis and design are validated by simulation and experimental results.

The application of silicon carbide (SiC) devices as battery interface, motor controller, etc., in a hybrid electric vehicle (HEV) will be beneficial due to their high-temperature capability, high-power density, and high efficiency. Moreover, the light weight and small volume will affect the whole powertrain system in a HEV and, thus, the performance and cost. In this paper, the performance of HEVs is analyzed using the vehicle simulation software Powertrain System Analysis Toolkit (PSAT). Power loss models of a SiC inverter based on the test results of latest SiC devices are incorporated into PSAT powertrain models in order to study the impact of SiC devices on HEVs from a system standpoint and give a direct correlation between the inverter efficiency and weight and the vehicle's fuel economy. Two types of HEVs are considered. One is the 2004 Toyota Prius HEV, and the other is a plug-in HEV (PHEV), whose powertrain architecture is the same as that of the 2004 Toyota Prius HEV. The vehicle-level benefits from the introduction of SiC devices are demonstrated by simulations. Not only the power loss in the motor controller but also those in other components in the vehicle powertrain are reduced. As a result, the system efficiency is improved, and vehicles that incorporate SiC power electronics are predicted to consume less energy and have lower emissions and improved system compactness with a simplified thermal management system. For the PHEV, the benefits are even more distinct; in particular, the size of the battery bank can be reduced for optimum design.

Power electronics is an enabling technology found in most renewable energy generation systems. Because of its superior voltage blocking capabilities and fast switching speeds, silicon carbide (SiC) power electronics are considered for use in power conversion units in wind generation systems in this paper. The potential efficiency gains from the use of SiC devices in a wind generation system are explored by simulations, with the system modeling explained in detail. The performance of the SiC converter is analyzed and compared to its silicon counterpart at different wind speeds, temperatures, and switching frequencies. The quantitative results are based on SiC metal-oxide-semiconductor field-effect transistor (MOSFET) prototypes from Cree and modern Si insulated-gate bipolar transistor (IGBT) products. A conclusion is drawn that the SiC converters can improve the wind system power conversion efficiency and can reduce the system's size and cost due to the low-loss, high-frequency, and high-temperature properties of SiC devices, even for one-for-one replacement for Si devices.

This paper presents a control method to limit the common-mode (CM) circulating current between paralleled three-phase two-level voltage-source converters (VSCs) with discontinuous space-vector pulsewidth modulation (DPWM) and interleaved switching cycles. This CM circulating current can be separated into two separate components based on their frequency; the high-frequency component, close to the switching frequency, can be effectively limited by means of passive components; the low-frequency component, close to the fundamental frequency, embodies the jumping CM circulating current observed in parallel VSCs. This is the main reason why it is usually recommended not to implement discontinuous and interleaving PWM together. The origin of this low-frequency circulating current is analyzed in detail, and based on this, a method to eliminate its presence is proposed by impeding the simultaneous use of different zero vectors between the converters. This control method only requires six additional switching actions per line cycle, presenting a minimum impact on the converter thermal design. The analysis and the feasibility of the control method are verified by simulation and experimental results.

A crucial component of grid-connected converters is the phase-locked loop (PLL) control subsystem that tracks the grid voltage's frequency and phase angle. Therefore, accurate fast-responding PLLs for control and protection purposes are required to provide these measurements. This paper proposes a novel feedback mechanism for single-phase PLL phase detectors using the estimated phase angle. Ripple noise appearing in the estimated frequency, most commonly the second harmonic under phase-lock conditions, is reduced or eliminated without the use of low-pass filters, which can cause delays to occur and limits the overall performance of the PLL response to dynamic changes in the system. The proposed method has the capability to eliminate the noise ripple entirely and, under extreme line distortion conditions, can reduce the ripple by at least half. Other modifications implemented through frequency feedback are shown to decrease the settling time of the PLL up to 50%. Mathematical analyses with the simulated and experimental results are provided to confirm the validity of the proposed methods.

The problem of electromagnetic interference (EMI) plays an important role in the design of power electronic converters, especially for airplane electrical systems. This paper explores techniques to reduce EMI noise in three-phase active front-end rectifier. The Vienna-type rectifier is used as the object. The design approach introduced in this paper is using a high-density EMI filter to satisfy the EMI standard. Design methodology is introduced in the paper by a three-stage LC- LC-L filter structure. In particular, the cause of high noise at high frequencies is studied in experiments, and the coupling effect of the final-stage capacitor and inductors is investigated. In order to reduce the EMI noise in the mid-frequency range, the application of random pulsewidth modulation (PWM) is also presented. The performance of random PWM in a Vienna-type rectifier is verified by theoretical analysis and experimental results. The approaches discussed in this paper significantly reduce the EMI noise in the Vienna-type rectifier, and therefore, the filter size can also be reduced.

Multispectral imaging (MSI) is becoming a powerful tool for tissue abnormality detection. Conventional MSI systems, however, are not readily suitable for challenges of routine clinical uses due to the fact that they are expensive, bulky, and time consuming to acquire the data. In this letter we report a novel approach to instrument MSI technology into a handheld, low-cost, standing-alone, real-time operational device that is suitable for home-based health care. It covers techniques used to produce multiple images at discrete signature wavelengths of tissues with a single shot.

This paper comprehensively investigates and compares different multiloop linear control schemes for single-phase pulsewidth modulation inverters, both in stationary and synchronous (d -q) frames, by focusing on their steady-state error under different loading conditions. Specifically, it is shown how proportional plus resonant (P + R) control and load current feedback (LCF) control can, respectively, improve the steady-state and transient performance of the inverter, leading to the proposal of a PID + R + LCF control scheme. Furthermore, the LCF control and capacitive current feedback control schemes are shown to be subject to stability issues under second and higher order filter loads. Additionally, the equivalence between the stationary frame and d -q frame controllers is discussed depending on the orthogonal term generation method, and a d-q frame voltage control strategy is proposed eliminating the need for the generation of this orthogonal component. This is achieved while retaining all the advantages of operating in the synchronous d-q frame, i.e., zero steady-state error and ease of implementation. All theoretical findings are validated experimentally using a 1.5 kW laboratory prototype.

To take full advantage of silicon carbide semiconductor devices, high-temperature device packaging needs to be developed. This paper describes potential defects from design and fabrication procedures, and presents a systematic electrical evaluation process to detect such defects. This systematic testing procedure can rapidly detect many defects and reduce the risk in high-temperature packaging testing. A multichip module development procedure that uses this testing procedure is also presented and demonstrated with an example.

It is well known that single-phase pulse width modulation rectifiers have second-order harmonic currents and corresponding ripple voltages on the dc bus. The low-frequency harmonic current is normally filtered using a bulk capacitor in the bus, which results in low power density. However, pursuing high power density in converter design is a very important goal in the aerospace applications. This paper studies methods for reducing the energy storage capacitor for single-phase rectifiers. The minimum ripple energy storage requirement is derived independently of a specific topology. Based on the minimum ripple energy requirement, the feasibility of the active capacitor's reduction schemes is verified. Then, we propose a bidirectional buck-boost converter as the ripple energy storage circuit, which can effectively reduce the energy storage capacitance. The analysis and design are validated by simulation and experimental results.

The application of silicon carbide (SiC) devices as battery interface, motor controller, etc., in a hybrid electric vehicle (HEV) will be beneficial due to their high-temperature capability, high-power density, and high efficiency. Moreover, the light weight and small volume will affect the whole powertrain system in a HEV and, thus, the performance and cost. In this paper, the performance of HEVs is analyzed using the vehicle simulation software Powertrain System Analysis Toolkit (PSAT). Power loss models of a SiC inverter based on the test results of latest SiC devices are incorporated into PSAT powertrain models in order to study the impact of SiC devices on HEVs from a system standpoint and give a direct correlation between the inverter efficiency and weight and the vehicle's fuel economy. Two types of HEVs are considered. One is the 2004 Toyota Prius HEV, and the other is a plug-in HEV (PHEV), whose powertrain architecture is the same as that of the 2004 Toyota Prius HEV. The vehicle-level benefits from the introduction of SiC devices are demonstrated by simulations. Not only the power loss in the motor controller but also those in other components in the vehicle powertrain are reduced. As a result, the system efficiency is improved, and vehicles that incorporate SiC power electronics are predicted to consume less energy and have lower emissions and improved system compactness with a simplified thermal management system. For the PHEV, the benefits are even more distinct; in particular, the size of the battery bank can be reduced for optimum design.

Power electronics is an enabling technology found in most renewable energy generation systems. Because of its superior voltage blocking capabilities and fast switching speeds, silicon carbide (SiC) power electronics are considered for use in power conversion units in wind generation systems in this paper. The potential efficiency gains from the use of SiC devices in a wind generation system are explored by simulations, with the system modeling explained in detail. The performance of the SiC converter is analyzed and compared to its silicon counterpart at different wind speeds, temperatures, and switching frequencies. The quantitative results are based on SiC metal-oxide-semiconductor field-effect transistor (MOSFET) prototypes from Cree and modern Si insulated-gate bipolar transistor (IGBT) products. A conclusion is drawn that the SiC converters can improve the wind system power conversion efficiency and can reduce the system's size and cost due to the low-loss, high-frequency, and high-temperature properties of SiC devices, even for one-for-one replacement for Si devices.

This paper presents a control method to limit the common-mode (CM) circulating current between paralleled three-phase two-level voltage-source converters (VSCs) with discontinuous space-vector pulsewidth modulation (DPWM) and interleaved switching cycles. This CM circulating current can be separated into two separate components based on their frequency; the high-frequency component, close to the switching frequency, can be effectively limited by means of passive components; the low-frequency component, close to the fundamental frequency, embodies the jumping CM circulating current observed in parallel VSCs. This is the main reason why it is usually recommended not to implement discontinuous and interleaving PWM together. The origin of this low-frequency circulating current is analyzed in detail, and based on this, a method to eliminate its presence is proposed by impeding the simultaneous use of different zero vectors between the converters. This control method only requires six additional switching actions per line cycle, presenting a minimum impact on the converter thermal design. The analysis and the feasibility of the control method are verified by simulation and experimental results.

A crucial component of grid-connected converters is the phase-locked loop (PLL) control subsystem that tracks the grid voltage's frequency and phase angle. Therefore, accurate fast-responding PLLs for control and protection purposes are required to provide these measurements. This paper proposes a novel feedback mechanism for single-phase PLL phase detectors using the estimated phase angle. Ripple noise appearing in the estimated frequency, most commonly the second harmonic under phase-lock conditions, is reduced or eliminated without the use of low-pass filters, which can cause delays to occur and limits the overall performance of the PLL response to dynamic changes in the system. The proposed method has the capability to eliminate the noise ripple entirely and, under extreme line distortion conditions, can reduce the ripple by at least half. Other modifications implemented through frequency feedback are shown to decrease the settling time of the PLL up to 50%. Mathematical analyses with the simulated and experimental results are provided to confirm the validity of the proposed methods.

The problem of electromagnetic interference (EMI) plays an important role in the design of power electronic converters, especially for airplane electrical systems. This paper explores techniques to reduce EMI noise in three-phase active front-end rectifier. The Vienna-type rectifier is used as the object. The design approach introduced in this paper is using a high-density EMI filter to satisfy the EMI standard. Design methodology is introduced in the paper by a three-stage LC- LC-L filter structure. In particular, the cause of high noise at high frequencies is studied in experiments, and the coupling effect of the final-stage capacitor and inductors is investigated. In order to reduce the EMI noise in the mid-frequency range, the application of random pulsewidth modulation (PWM) is also presented. The performance of random PWM in a Vienna-type rectifier is verified by theoretical analysis and experimental results. The approaches discussed in this paper significantly reduce the EMI noise in the Vienna-type rectifier, and therefore, the filter size can also be reduced.

Multispectral imaging (MSI) is becoming a powerful tool for tissue abnormality detection. Conventional MSI systems, however, are not readily suitable for challenges of routine clinical uses due to the fact that they are expensive, bulky, and time consuming to acquire the data. In this letter we report a novel approach to instrument MSI technology into a handheld, low-cost, standing-alone, real-time operational device that is suitable for home-based health care. It covers techniques used to produce multiple images at discrete signature wavelengths of tissues with a single shot.

This paper comprehensively investigates and compares different multiloop linear control schemes for single-phase pulsewidth modulation inverters, both in stationary and synchronous (d -q) frames, by focusing on their steady-state error under different loading conditions. Specifically, it is shown how proportional plus resonant (P + R) control and load current feedback (LCF) control can, respectively, improve the steady-state and transient performance of the inverter, leading to the proposal of a PID + R + LCF control scheme. Furthermore, the LCF control and capacitive current feedback control schemes are shown to be subject to stability issues under second and higher order filter loads. Additionally, the equivalence between the stationary frame and d -q frame controllers is discussed depending on the orthogonal term generation method, and a d-q frame voltage control strategy is proposed eliminating the need for the generation of this orthogonal component. This is achieved while retaining all the advantages of operating in the synchronous d-q frame, i.e., zero steady-state error and ease of implementation. All theoretical findings are validated experimentally using a 1.5 kW laboratory prototype.

Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimising system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8--m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

Common-mode (CM) choke saturation is a practical problem in CM filter applications. It is generally believed that the leakage inductance of CM chokes makes the core saturated. This paper analyzes two new mechanisms for CM choke saturation due to CM voltage, and these mechanisms are verified in experiment. CM choke saturation is particularly important for motor drive systems, which have a high CM voltage and comparably higher stray grounding capacitance. A model is established to describe the relationship between the CM voltage and the volume of the CM magnetic components. According to the analysis, line impedance stabilization networks (LISNs) play an important role in the design of CM magnetic components.

This paper presents the design, development, and testing of a phase-leg power module packaged by a novel planar packaging technique for high-temperature (250°C) operation. The nanosilver paste is chosen as the die-attach material as well as playing the key functions of electrically connecting the devices' pads. The electrical characteristics of the SiC-based power semiconductors, SiC JFETs, and SiC Schottky diodes have been measured and compared before and after packaging. No significant changes (<;5%) are found in the characteristics of all the devices. Prototype module is fabricated and operated up to 400 V, 1.4 kW at junction temperature of 250°C in the continuous power test. Thermomechanical robustness has also been investigated by passive thermal cycling of the module from -55°C to 250°C. Electrical and mechanical performances of the packaged module are characterized and considered to be reliable for at least 200 cycles.

High-frequency common-mode (CM) electromagnetic-interference (EMI) noise is difficult to suppress in electronics systems. EMI filters are used to suppress CM noise, but their performance is greatly affected by the parasitic effects of the grounding paths. In this paper, the parasitic effects of the grounding paths on an EMI filter's performance are investigated in a motor-drive system. The effects of the mutual inductance between two grounding paths are explored. Guidelines for the grounding of CM EMI filters are derived. Simulations and experiments are finally carried out to verify the theoretical analysis.

The SiC JFET is an attractive semiconductor device due to its superior switching performance and high-temperature operating capability. Its shoot-through protection remains a challenge due to the limited practical knowledge existent on this device and due to its inherent normally on nature. Addressing this limitation, this paper presents a novel shoot-through protection scheme in which a bidirectional switch, compounded by a Si insulated-gate bipolar transistor (IGBT) and a relay,is embedded into the dc-link midpoint in order to detect and clear shoot-through faults, taking advantage of the well-known desaturation protection schemes of IGBTs to protect SiC JFETs. This paper describes in detail the proposed protection mechanism and its circuit design, presenting as well the experimental results that verified the effectiveness of the proposed scheme using, first, Si MOSFETs and second, a 10-kW ac-ac converter system using SiC JFETs.

Terminal models have been used for various applications. In this paper, a three-terminal model is proposed for electromagnetic-interference (EMI) characterization. The model starts with a power electronic system at a particular operating condition and creates a unique linearized equivalent circuit. Impedances and current/voltage sources define the noise throughout the entire EMI frequency spectrum. All parameters needed to create the model are clearly defined to ensure convergence and maximize accuracy. In addition, the accuracy of the model is confirmed up to 100 MHz for a dc-dc boost converter using both simulation and experimental validation.

This paper will present the analytical proof of concept of the multilevel modular capacitor-clamped converter (MMCCC). The quantitative analysis of the charge transfer mechanism among the capacitors of the MMCCC explains the start-up and steady-state voltage balancing. Once these capacitor voltages are found for different time intervals, the start-up and steady-state voltages at various nodes of the MMCCC can be obtained. This analysis provides the necessary proof that explains the stable operation of the converter when a load is connected to the low-voltage side of the circuit. In addition, the analysis also shows how the LV side of the converter is (1/N)th of the HV side excitation when the conversion ratio of the circuit is N. In addition to the analytical and simulation results, experimental results are included to support the analytical proof of concept.

This letter presents a novel integration approach for the electromagnetic interference choke. A low-permeability differential-mode (DM) choke is placed within the open window of the common-mode (CM) choke. Both chokes share the same winding structure. With the proposed approach, the footprint of inductors is greatly reduced, and high-DM inductance can be achieved. First, small-signal measurement is carried out to demonstrate the design concept and the symmetry of the proposed structure. Then large-signal experimental results verify the attenuation characteristics, as well as the thermal performance.

This paper begins with an analysis of the common-mode (CM) noise in a motor drive system. Based on the developed CM noise model, two cancellation techniques, CM noise voltage cancellation and CM noise current cancellation, are discussed. The constraints and impedance requirements for these two cancellation methods are investigated. An active filter with a feedforward current cancellation technique is proposed, implemented, and tested, and techniques to improve the performance of active filters are explored. It is found that due to the limitations of speed, power loss, and gain bandwidth of active filters, active electromagnetic interference (EMI) filters are not good at suppressing high di/dt or high amplitude noise current. Hybrid filters that include a passive filter and an active filter are proposed to overcome the shortcomings of active filters. Hybrid EMI filters are investigated based on the impedance requirements and frequency responses between the passive and active filters. The experiments show that the proposed active filter can greatly reduce noise by up to 50 dB at low frequencies (LFs), and therefore, the corner frequency of the passive filter can be increased considerably; as a result, the CM inductance of the passive filter is greatly reduced. The power loss of the proposed active EMI filter can be well-controlled in the experiments.

A three-phase insulated gate bipolar transistor (IGBT)-based static var compensator (STATCOM) is used for voltage and/or current unbalance compensation. An instantaneous power theory is adopted for real-time calculation and control. Three control schemes - current control, voltage control and integrated control - are proposed to compensate the unbalance of current, voltage or both. The compensation results of the different control schemes in unbalance cases (load current unbalance or voltage unbalance) are compared and analysed. The simulation and experimental results show that the control schemes can compensate the unbalance in load current or in the voltage source. Different compensation objectives can be achieved, that is, balanced and unity power factor source current, balanced and regulated voltage or both, by choosing appropriate control schemes.

This paper presents strategies to reduce both differential-mode (DM) and common-mode (CM) noise using a passive filter in a dc-fed motor drive. The paper concentrates on the type of grounding and the components to optimize filter size and performance. Grounding schemes, material comparison between ferrite and nanocrystalline cores, and a new integrated filter structure are presented. The integrated structure maximizes the core window area and increases the leakage inductance by integrating both CM and DM inductances onto one core. Small-signal and large-signal experiments validate the structure, showing it to have reduced filter size and good filtering performance when compared with standard filters at both low and high frequencies.

Common-mode (CM) choke saturation is a practical problem in CM filter applications. It is generally believed that the leakage inductance of CM chokes makes the core saturated. This paper analyzes two new mechanisms for CM choke saturation due to CM voltage, and these mechanisms are verified in experiment. CM choke saturation is particularly important for motor drive systems, which have a high CM voltage and comparably higher stray grounding capacitance. A model is established to describe the relationship between the CM voltage and the volume of the CM magnetic components. According to the analysis, line impedance stabilization networks (LISNs) play an important role in the design of CM magnetic components.

This paper presents the design, development, and testing of a phase-leg power module packaged by a novel planar packaging technique for high-temperature (250°C) operation. The nanosilver paste is chosen as the die-attach material as well as playing the key functions of electrically connecting the devices' pads. The electrical characteristics of the SiC-based power semiconductors, SiC JFETs, and SiC Schottky diodes have been measured and compared before and after packaging. No significant changes (<;5%) are found in the characteristics of all the devices. Prototype module is fabricated and operated up to 400 V, 1.4 kW at junction temperature of 250°C in the continuous power test. Thermomechanical robustness has also been investigated by passive thermal cycling of the module from -55°C to 250°C. Electrical and mechanical performances of the packaged module are characterized and considered to be reliable for at least 200 cycles.

High-frequency common-mode (CM) electromagnetic-interference (EMI) noise is difficult to suppress in electronics systems. EMI filters are used to suppress CM noise, but their performance is greatly affected by the parasitic effects of the grounding paths. In this paper, the parasitic effects of the grounding paths on an EMI filter's performance are investigated in a motor-drive system. The effects of the mutual inductance between two grounding paths are explored. Guidelines for the grounding of CM EMI filters are derived. Simulations and experiments are finally carried out to verify the theoretical analysis.

The SiC JFET is an attractive semiconductor device due to its superior switching performance and high-temperature operating capability. Its shoot-through protection remains a challenge due to the limited practical knowledge existent on this device and due to its inherent normally on nature. Addressing this limitation, this paper presents a novel shoot-through protection scheme in which a bidirectional switch, compounded by a Si insulated-gate bipolar transistor (IGBT) and a relay,is embedded into the dc-link midpoint in order to detect and clear shoot-through faults, taking advantage of the well-known desaturation protection schemes of IGBTs to protect SiC JFETs. This paper describes in detail the proposed protection mechanism and its circuit design, presenting as well the experimental results that verified the effectiveness of the proposed scheme using, first, Si MOSFETs and second, a 10-kW ac-ac converter system using SiC JFETs.

Terminal models have been used for various applications. In this paper, a three-terminal model is proposed for electromagnetic-interference (EMI) characterization. The model starts with a power electronic system at a particular operating condition and creates a unique linearized equivalent circuit. Impedances and current/voltage sources define the noise throughout the entire EMI frequency spectrum. All parameters needed to create the model are clearly defined to ensure convergence and maximize accuracy. In addition, the accuracy of the model is confirmed up to 100 MHz for a dc-dc boost converter using both simulation and experimental validation.

This paper will present the analytical proof of concept of the multilevel modular capacitor-clamped converter (MMCCC). The quantitative analysis of the charge transfer mechanism among the capacitors of the MMCCC explains the start-up and steady-state voltage balancing. Once these capacitor voltages are found for different time intervals, the start-up and steady-state voltages at various nodes of the MMCCC can be obtained. This analysis provides the necessary proof that explains the stable operation of the converter when a load is connected to the low-voltage side of the circuit. In addition, the analysis also shows how the LV side of the converter is (1/N)th of the HV side excitation when the conversion ratio of the circuit is N. In addition to the analytical and simulation results, experimental results are included to support the analytical proof of concept.

This letter presents a novel integration approach for the electromagnetic interference choke. A low-permeability differential-mode (DM) choke is placed within the open window of the common-mode (CM) choke. Both chokes share the same winding structure. With the proposed approach, the footprint of inductors is greatly reduced, and high-DM inductance can be achieved. First, small-signal measurement is carried out to demonstrate the design concept and the symmetry of the proposed structure. Then large-signal experimental results verify the attenuation characteristics, as well as the thermal performance.

This paper begins with an analysis of the common-mode (CM) noise in a motor drive system. Based on the developed CM noise model, two cancellation techniques, CM noise voltage cancellation and CM noise current cancellation, are discussed. The constraints and impedance requirements for these two cancellation methods are investigated. An active filter with a feedforward current cancellation technique is proposed, implemented, and tested, and techniques to improve the performance of active filters are explored. It is found that due to the limitations of speed, power loss, and gain bandwidth of active filters, active electromagnetic interference (EMI) filters are not good at suppressing high di/dt or high amplitude noise current. Hybrid filters that include a passive filter and an active filter are proposed to overcome the shortcomings of active filters. Hybrid EMI filters are investigated based on the impedance requirements and frequency responses between the passive and active filters. The experiments show that the proposed active filter can greatly reduce noise by up to 50 dB at low frequencies (LFs), and therefore, the corner frequency of the passive filter can be increased considerably; as a result, the CM inductance of the passive filter is greatly reduced. The power loss of the proposed active EMI filter can be well-controlled in the experiments.

A three-phase insulated gate bipolar transistor (IGBT)-based static var compensator (STATCOM) is used for voltage and/or current unbalance compensation. An instantaneous power theory is adopted for real-time calculation and control. Three control schemes - current control, voltage control and integrated control - are proposed to compensate the unbalance of current, voltage or both. The compensation results of the different control schemes in unbalance cases (load current unbalance or voltage unbalance) are compared and analysed. The simulation and experimental results show that the control schemes can compensate the unbalance in load current or in the voltage source. Different compensation objectives can be achieved, that is, balanced and unity power factor source current, balanced and regulated voltage or both, by choosing appropriate control schemes.

This paper presents strategies to reduce both differential-mode (DM) and common-mode (CM) noise using a passive filter in a dc-fed motor drive. The paper concentrates on the type of grounding and the components to optimize filter size and performance. Grounding schemes, material comparison between ferrite and nanocrystalline cores, and a new integrated filter structure are presented. The integrated structure maximizes the core window area and increases the leakage inductance by integrating both CM and DM inductances onto one core. Small-signal and large-signal experiments validate the structure, showing it to have reduced filter size and good filtering performance when compared with standard filters at both low and high frequencies.

A 5-kW multilevel modular capacitor-clamped DC-DC converter (MMCCC) with bi-directional power management and real-time fault bypassing capability will be presented in this study. The modular structure of the MMCCC topology was utilised to build this 5-kW converter with necessary redundancy and hot swap feature for industrial and automotive applications including a future plug-in hybrid or fuel-cell powered all electric vehicles. Moreover, the circuit has flexible conversion ratio that leads to establish bi-directional power management for automotive applications mitigating the boost voltage for the fuel-cell or dual battery architecture. In addition, the MMCCC exhibits better component utilisation compared to many capacitor-clamped or classical DC-DC converters based on inductive energy transfer mechanism. Thus, the MMCCC circuit can be made more compact and reliable compared to many other DC-DC converters for high-power applications.

A 5-kW multilevel modular capacitor-clamped DC-DC converter (MMCCC) with bi-directional power management and real-time fault bypassing capability will be presented in this study. The modular structure of the MMCCC topology was utilised to build this 5-kW converter with necessary redundancy and hot swap feature for industrial and automotive applications including a future plug-in hybrid or fuel-cell powered all electric vehicles. Moreover, the circuit has flexible conversion ratio that leads to establish bi-directional power management for automotive applications mitigating the boost voltage for the fuel-cell or dual battery architecture. In addition, the MMCCC exhibits better component utilisation compared to many capacitor-clamped or classical DC-DC converters based on inductive energy transfer mechanism. Thus, the MMCCC circuit can be made more compact and reliable compared to many other DC-DC converters for high-power applications.

In this work, we develop a methodology and tool to quantitatively evaluate the reliability of a self-healing system that considers practical distribution system features such as the distributed energy resources, microgrids, and service restoration strategies. Also, this paper addresses various practical issues when being applied to an actual Duke Energy distribution system, including the design of feasible and practical service restoration strategies that are used to identify the customer interruptions after a fault, and the incorporation of the utility's historical reliability indices that are used to calibrate the failure rate and repair time of distribution system components such as overhead lines and underground cables. This case study demonstrates the effectiveness of the proposed method.

With the development of wide band-gap (WBG) technology, the switching speed of power semiconductor devices increases, which makes circuits more sensitive to parasitics. For three-level active neutral point clamped (3L-ANPC) converters, the over-voltage caused by additional non-active switch loop can be an issue. This paper analyzes the multiple commutation loops in 3L-ANPC converter and summarizes the impact factors of the device over-voltage. The nonlinearity of the output capacitance of the device can significantly influence the over-voltage. A simple control without introducing additional hardware circuit or complex software algorithm is proposed to attenuate the effect of the nonlinear output capacitance. Multi-pulse test is conducted for a 3L-ANPC converter built with silicon carbide (SiC) MOSFETs. With the proposed control, the testing results show that the peak drain-source voltage of both active and non-active switches is reduced by more than 20% compared to the conventional control.

The performance of the gate drive power supply (GDPS) greatly impacts the safety and reliability of the gate drive for power semiconductor power devices. This paper focuses on the design of isolated gate driver power supply for 10 kV silicon-carbide (SiC) MOSFET for medium-voltage (MV) applications. Different insulation schemes are compared for the high-voltage insulated transformer in GDPS. Impact factors for transformer interwinding capacitance are analyzed, with which, a low inter-winding capacitance design approach is proposed for the high-voltage insulated transformer. Furthermore, an upward-voltage-reference based voltage regulation scheme is proposed for achieving good load regulation without output voltage feedback. Finally, a 20-kV-insulated GDPS is built and tested, and experimental results are presented to verify the effectiveness of the design approach.

The newly emerged 10 kV MOSFETs will be a game changer for the next generation medium-voltage (MV) power converters. While the unique feature of the fast switching speed benefits the development of high efficiency and high power-density MV converters, high dv/dt will be imposed on the power devices and passive components, which will result in accelerated insulation degradation and extreme EMI. This paper investigates the high dv/dt resulting from dead-time insertion in the modular multilevel converter (MMC). For reducing dv/dt, a multiple-step commutation scheme is proposed, in which, the submodules that transfer from bypass-state to insert-state are one-by-one commutated with those transferring from insert-state to bypass-state before the remaining unpaired submodules. Finally, the proposed multiple-step commutation scheme is verified on a single-phase MMC with 10-kV SiC MOSFET.

This paper focuses on the testing approach and validation of a 10 kV SiC MOSFET based Modular Multilevel Converter (MMC) phase-leg meant to interface to a 13.8 kV microgrid. Many of the difficulties associated with testing high-voltage SiC converters are shared regardless of topology, thus the testing setup and challenges associated with it are emphasized while the converter is only briefly summarized. Each component is individually verified, and the entire system is tested up to its rated dc link voltage and power, 25 kV and 35 kVA, respectively.

An analytical model for the device drain-source turn-on overvoltage in three-level active neutral point clamped (3L-ANPC) converters is established in this paper. Considering the two commutation loops in the converter, the relationship between the turn-on overvoltage and the loop inductances is evaluated. The line switching frequency device usually exhibits higher overvoltage, while the high switching frequency device is not strongly influenced by the multiple loops. A 500 kVA 3L-ANPC converter using SiC MOSFETs is tested, and the model is verified with the experimental results.

In paralleled voltage source inverters (VSI), circulating current has both high frequency and low frequency components, and its spectrum highly depends on the modulation scheme. Previous research has mostly focused on the circulating current suppression for paralleled two-level VSIs. Little literature exists on similar analysis for paralleled three-level VSIs using space vector modulation. A detailed circulating current spectrum on full frequency range has not been well developed. This paper presents an improved analytical model for three-level space vector modulation (SVM), considering the impacts of regularly sampled reference and dead time. Then, circulating harmonic currents are determined across the full frequency range for various interleaving angles of two three-level ANPC inverters. The calculated harmonics are also verified by experimental results.

With conventional voltage source gate drives (VSG), the switching speed of SiC MOSFETs is difficult to increase due to large internal gate resistance, high Miller voltage, and limited gate voltage rating. This paper analyzes the requirement of current source gate drive (CSG) for SiC MOSFETs and proposes a CSG that can improve the switching speed and reduce switching loss. With the introduction of bi-directional switches, the influence of the large internal gate resistance of the SiC MOSFET can be mitigated, and sufficient gate current can be guaranteed throughout the switching transient. Therefore, the switching time and loss is reduced. The CSG can be controlled to be a VSG during steady state so the current of the gate drive is discontinuous and the stored energy of the inductor can be returned to the power supply to reduce gate drive loss. Double pulse tests are conducted for a SiC MOSFET with both conventional VSG and the proposed CSG. Testing results show that the switching loss of the proposed CSG is less than one third of the conventional VSG at full load condition.

The four-leg topology has been applied to two-level inverters for common-mode (CM) noise elimination. To achieve zero common-mode voltage (CMV), the zero vector typically used in the two-level inverter is not allowed. As a result, the reference cannot be synthesized by nearest three vectors, which introduces a penalty in dc voltage utilization and current THD. This paper applies the fourth-leg to three-level neutral point clamped (NPC) inverter fed motor drives. Unlike the case in the two-level inverter, the reference can be synthesized by the nearest three vectors while zero CMV can be achieved at the same time in a three-level inverter with the fourth-leg. The topology and modulation are presented. The fourth-leg filter structures are investigated, and a fourth-leg filter structure which decouples the fourth-leg from the main circuit power level is proposed for high power applications. The experiment results on a three-level NPC inverter show that with the fourth-leg and presented modulation applied, the CM noise has been significantly reduced, and around 25 dB attenuation can be observed at the first noise peak in the electromagnetic interference (EMI) frequency range.

Paralleling power electronics inverters is an effective way to increase dc-ac system power level. Accurately synchronized switching action and independent closed-loop regulator are necessary to prevent circulating current in paralleled inverters. There are many challenges for the controller design, when the number of paralleled inverters is large, and control period gets short for high switching frequency applications. This paper presents a single controller design based on DSP + FPGA that is suitable for paralleling multiple inverters. A simple synchronization scheme between DSP and FPGA based on universal parallel port (UPP) is proposed to eliminate the synchronization delay among inverters, and independent control of each converter can also be implemented. The controller is built for a system consisting of 4 paralleled three-level, three-phase high frequency ANPC inverters using space vector modulation, and it can be easily adopted to other topologies and modulations. Experimental results have demonstrated the effectiveness of this controller.

This paper presents a comprehensive analytical analysis of the ac and dc side harmonics of the three-level active neutral point clamped (ANPC) inverter with space vector modulation (SVM) scheme. An analytical model to calculate the harmonics of a three-level converter with SVM is developed. The ac side output voltage harmonics and dc side current harmonics characteristics are calculated and analyzed. With the developed models, the impact of interleaving on both sides harmonics are studied which considers the modulation index, interleaving angle, and power factor. The analysis provides guideline for interleaving angle optimization to reduce the ac side power filter and dc side dc-link capacitor. The relationship between electromagnetic interference (EMI) filter corner frequency and switching frequency is also analytically derived which provides guideline for switching frequency and EMI filter design optimization. Two paralleled three-level ANPC inverters are constructed and experimental results are presented to verify the analytical analysis.

This paper presents the coupled inductor design for interleaved three-level active neutral point clamped (ANPC) inverter considering electromagnetic interference (EMI) noise reduction. Compared to two-level case, the scenarios involved in the three-level space vector modulation (SVM) are more complicated when analyzing the volt-seconds of the coupled inductor for paralleled three-level inverter. At system level, the purpose of converter interleaving is to reduce EMI noise and ripple current in most applications, and coupled inductor design should consider the needs of EMI noise reduction and EMI filter design. These issues are discussed in this paper. The relationship between circulating current and EMI noise is illustrated. EMI filter corner frequency as a function of interleaving angle is analytically derived, and optimal interleaving angle for maximum common-mode (CM) filter and differential-mode (DM) filter corner frequencies is discussed. Coupled inductor design methodology for interleaved three-level inverters with SVM is then presented. Experiments on two interleaved ANPC inverters are conducted. The results verify the coupled inductor design. With the derived optimal interleaving angle, the CM and DM EMI noise are significantly reduced.

To overcome the limitations of digital simulation (numerical oscillation, limited computing capability of processors, etc.), a converter-based hardware test-bed was developed at CURENT for real-time power grid emulation. However, distribution systems especially microgrids cannot be emulated and tested on the existing hardware test-bed. This paper develops a microgrid test-bed based on the existing hardware test-bed to enable controller testing for microgrids with dynamic boundary. The design and realization of the microgrid hardware test-bed are introduced. The experimental results of the microgrid controller tests are also provided.

The adoption of SiC devices in high power applications enables higher switching speed, which requires lower circuit parasitic inductance to reduce the voltage overshoot. This paper presents the design of a busbar for a 500 kVA three-level active neutral point clamped (ANPC) converter. The layout of the busbar is discussed in detail based on the analysis of the multiple commutation loops, magnetic canceling effect, and DC-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. The results match with each other, and the inductances of small and large loop are 6.5 nH and 17.5 nH respectively, which is significantly lower than the busbars of NPC type converters in other references.

This paper presents harmonic analysis of common-mode reduction (CMR) modulation for three-level voltage source inverters. The analytical model to calculate the harmonics of CMR modulation with arbitrary PWM sequence is developed. The impact of alternative PWM sequences of CMR modulation on harmonics is investigated. New three-state and four-state PWM sequences of CMR are proposed which spread the energy centered in the carrier frequency in the conventional CMR, and thus reduce the voltage peaks in frequency domain. Experiments are conducted on a three-level neutral point clamped inverter. Experiment results verify the developed analytical model and harmonic analysis.

High power inverters will be a key enabler for future aircraft based on hybrid electric or turbo-electric propulsion as envisioned by NASA and Boeing. Cooling a power electronics converter to low temperature, e.g. using cryogenic cooling, can significantly improve the efficiency and power density of a power conversion system. This paper presents the design of a MW cryogenically-cooled power inverter for electric aircraft applications. The power semiconductor and magnetic component characterization, inverter topology and power stage design, modulation and control, EMI noise reduction and filters design, and cooling system design are illustrated. A MW-level inverter prototype has been assembled and tested. The experimental results verify the functionality of the inverter.

The modular multilevel converter (MMC) is regarded as a competitive choice for future dc grids at high and medium voltage levels. To study the dc grid stability, a few MMC dc impedance models have been proposed, but their accuracy is limited by the assumption of ideal submodule voltage or neglecting the circulating current control. In this paper, a more accurate MMC dc impedance model is developed considering both the submodule capacitor voltage and circulating current dynamics. Simulation and experiment results indicate that the developed model matches with the actual MMC better than state-of-art models and can predict the dc system stability correctly.

Medium voltage (MV) power converters using high voltage (HV) Silicon Carbide (SiC) power semiconductors result in great benefits in weight, size, efficiency and control bandwidth. However, challenges still exist on the components design considering HV insulation and noise immunity requirements in the MV SiC based power converter. A 5-level MMC based transformer-less grid-connected dc/ac converter is developed for 13.8 kV medium voltage grid using 10 kV SiC MOSFETs. The key components, including gate driver with high dv/dt immunity and fast reliable protection, isolated power supply with low parasitic capacitance, voltage/current sensors with high noise immunity, and passives following related insulation standard are provided. A 25 kV dc-link phase-leg is demonstrated, and the experimental results are presented.

Land cover classification of satellite imagery can provide significant information for many applications, including surface analysis, environmental monitoring, building reconstruction, etc. Land cover classification has been generally performed using unmixing-based or shallow/deep learning approaches, among which the unmixing-based approaches suffer from stability issues due to the complex intrinsic properties of the data, deep learning-based approaches like 2D CNN requires large labeled training set which is often unavailable in satellite images and small ground truth collection leads to spatial discontinuities (as shown in Fig. 1), making 2D CNN approaches unviable. In this paper, we first propose a 1D convolution neural network-based framework applied to each pixel in the spectral domain where we extract descriptive local features for improved classification. Experimental results demonstrate superior classification accuracy through comparison with traditional unmixing-based and neural network methods using just limited number of training samples.

Data center energy usage is expected to grow in the coming years with the proliferation of cloud services on daily life. The increasing energy demands that data centers will place upon the power grid necessitate the development high efficiency, high power density power supplies. The LLC resonant converter has long been utilized for data center power supplies as the dc-dc transformer to step down the voltage rectified from the ac transmission system to the rack level. As more is demanded of the data center and more information must be processed, space becomes more valuable. The use of wide bandgap materials such as Gallium Nitride (GaN) allows for much faster switching which can lead to higher power density by reducing the size of passive components. However, a higher frequency can lead to much greater switching loss. Zero-voltage switching (ZVS) can be utilized in primary side devices to greatly reduce losses. The achievement of ZVS is dependent on the magnetic design of the LLC transformer. By considering the effects of device capacitance and transformer parasitic capacitance and inductance, ZVS can be achieved to negate the turn-on losses and ensure high efficiency. This paper details the analysis of ZVS for a GaN-based LLC resonant converter with two series-parallel connected transformers.

This paper details the inductor design and zero-voltage-switching (ZVS) control of a single-phase GaN-based critical-conduction-mode (CRM) totem-pole rectifier with power factor correction (PFC). A full-line-cycle ZVS strategy is derived, and an analytical converter model with ZVS margin is proposed. The boost inductor design is critical for the operation performance of the CRM totem-pole PFC. Based on analytical loss models, the inductor is designed and implemented using a toroidal powder core and litz wire to minimize converter loss and inductor size. Digital on-time control with real-time calculation and zero current detection (ZCD) is used to implement CRM. A 1.5 kW single-phase GaN-based CRM totem-pole PFC prototype is built and tested. With the on-time control, both the inductor current and the output voltage are well regulated. ZVS is realized for the whole line cycle, and the tested efficiency is 98.8% at full load.

This paper focuses on the design and testing of a half bridge submodule based on discrete 10 kV/20 A SiC MOSFETs for a modular multilevel converter (MMC). The rated dc bus voltage of the submodule is 6.5 kV, and the MOSFETs switch with dv/dt up to 100 V/ns. Design considerations and challenges for components in the submodule are presented, especially the gate driver to support the robust continuous operation and the submodule voltage sensor. Systematic testing procedures are developed to fully test the submodule up to 6.5 kV. High voltage insulation and high dv/dt are tackled throughout the design and testing. The designed submodule is validated in the continuous switching test at 6.5 kV with dv/dt up to 100 V/ns.

The paper aims to resolve the converter loss discrepancy between calculation and testing results by considering five factors: impacts of parasitic capacitance on switching loss, parameter variation of devices, time-varying power dissipation and junction temperature, thermal modeling using Finite Element Analysis, and some practical issues of the passive components. A 4.5 kW hard-switching inverter prototype using GaN devices was used as an example to demonstrate the improvement of loss model. The results show that after considering the above factors, loss discrepancy reduces from 35.7 W (35%) to 1.4 W (4%) at heavy load and, from 3.9 W (28%) to 2.6 W (less than 16%) at light load.

High-frequency soft-switched gallium-nitride (GaN) based critical conduction mode (CRM) totem-pole power factor correction (PFC) converter is one of the most potential candidates in data center power supplies. However, the high-speed cycle-by-cycle zero current detection (ZCD) brings challenges to zero-voltage-switching (ZVS) control. Current sensing delay (CSD) exists, and the ZCD circuit is sensitive to high di/dt switching noise. In this paper, mechanisms of the ZCD time error are elaborated, and impacts of the current sensing delay on converter switching frequency, inductor current, input current third harmonic distortion (THD), and power loss are analyzed. Qualification time is added within the controller for immunity to the swiching noise, and a CSD embedded converter model is proposed to compensate the ZCD time delay. Also, loss modeling of the CRM totem-pole PFC is conducted to aid in analysis of the proposed theory. A 1.5 kW single-phase CRM totem-pole PFC prototype is tested. Experimental results validiate the analysis, modeling, and the proposed compensation method for current sensing delay.

In this paper, a variable frequency soft-switching control for a three-level half bridge (TLHB) buck converter is proposed to achieve wide-range output battery charging function without losing zero voltage switching (ZVS) or high efficiency. The adopted variable frequency triangle-current-modulation (TCM) is based on dc measurement and average-model calculation, thus able to realize ZVS operation fully digitally without current zero-crossing-detection (ZCD) circuits. A top-level average current or output voltage feedback controller further ensures the desired power or output voltage regulation. Experimental results from a GaN based TLHB prototype have shown the reliable TCM control and smooth transition of ZVS operation through the charging procedure.

Virtual synchronous generator control provides a potential solution to connect power electronics interfaced sources to the power system. With its flexible control, the emulated inertia may be adaptively changed to enhance system small-signal stability. However, previously proposed methods may have adverse impact to system transient stability. This paper proposes to improve the methods by using wide-area measurements, namely center of inertia frequency. Experimental results are presented to both demonstrate the limitations of previous control schemes, and the effectiveness of the proposed one. The practical implementation of this method is discussed.

Cysticercosis is a parasitic infection caused by adult tapeworms, and it constantly plagues the livelihoods of people from subsistence farming communities in developing countries. Diagnosis of Cysticercosis typically requires both central nervous system imaging and serological testing. The most common methods in serological testing are Enzyme-linked Immunosorbent Assay (ELISA) and Enzyme Immuno-electrotransfer Blot (EITB). Both ELISA and EITB methods are excessively time-consuming and labor-intensive. Recent research indicates that a shorter assay time and/or higher sensitivity can be achieved by integrating alternate current electrokinetics (ACEK) with biosensing. However, the raw time-series data is very noisy and the size of the dataset is extremely small, which would bring two potential challenges. On one hand, traditional statistical methods cannot extract features robust enough for high sensitivity as well as high specificity. On the other hand, the small data size limits the usage of automatic feature extractors such as deep neural networks. In this paper, we propose a linear unmixing based approach by exploiting the possibility that the time-series biological signals can be represented as linear combinations of source signals. This paper makes distinctive contributions to the field of bio-signal by introducing the unmixing model from the image processing domain to the time-series domain. Experimental results on the classification of Cysticercosis using 123 samples demonstrate the robustness and superior performance of the linear unmixing method over other conventional classifiers in handling small datasets.

Identifying land-cover and specifically the type of the material that constitutes building roofs in urban areas provides important reference information for later procedures including semantic labeling, bridge masking, and 3D reconstruction. In this paper, we present a hybrid unmixing-based classification framework that integrates both class-wise unsupervised unmixing and supervised unmixing that effectively convert the classification problem from the original spectral space to the abundance space, such that the intrinsic characteristics of each material can be better represented. Experimental results demonstrate competitive performance in terms of classification accuracy. In addition, we show that the proposed approach has the capability of handling new region of interest with similar scene content but different illumination geometry and atmospheric composition, which is crucial in classification of satellite images with a limited amount of training data.

Modeling plays a vital role in the design of advanced power converters. Commonly, modeling is completed using either dedicated hand analysis, which must be completed individually for each topology, or time-stepping circuit simulations, which are insufficiently rapid for broad analysis considering a wide range of potential designs or operating points. Discrete time state-space modeling of switching converters has shown merits in rapid analysis and generality to arbitrary circuit topologies but is hampered by difficulty incorporating nonlinear elements. In this work, we investigate methods for the incorporation of nonlinear elements into a generalized discrete time state-space modeling framework and showcase the utility of the approach for use in the converter design process.

Control based modulation techniques such as Boundary Current Mode (BCM) modulation are used to achieve zero voltage switching (ZVS) and overcome the increased switching losses in power electronics operating at high frequency. A simple control approach to implementing BCM uses dual current programmed mode (DCPM) control, but this approach is highly susceptible to noise and propagation delays at high switching frequency. Propagation delays in the control network cause the inductor current to overshoot its reference by a margin which varies with the instantaneous inductor current slope. This overshoot results in increased losses and introduces low-frequency inductor current distortion, particularly in high switching frequency converters. This work addresses propagation delay challenges by tuning the current sensing circuitry to mitigate impact of sensing delay, resulting in an inherent cancellation of sensing delay without additional control complexity. This approach is simple to implement and offers a flexible current control design for BCM modulation. The operation of this proposed compensation technique is demonstrated experimentally in a GaN-based full bridge inverter.

This paper proposes an adaptive control strategy for passivity or phase compensation of inverter output admittance or impedance based on online detection of resonance frequency, so that inverters can be stably integrated into power grids with unknown system information or time-varying structures. The resonance frequency is detected by online fast Fourier transform (FFT) analysis of inverter current within the inverter controller. The passivity of output admittance of current-controlled inverters at the resonance frequency is compensated by emulating a virtual parallel resistor through an additional voltage feed-forward path with a band-pass filter. The phase of output impedance of voltage-controlled inverters at the resonance frequency is compensated by inserting a notch filter in the current feed-forward path. Experimental results validate the effectiveness of the proposed adaptive impedance compensation method in resonance damping and stable integration of inverters into unknown systems.

A microgrid with dynamic boundary can expand or shrink its boundary depending on available local distributed energy resources (DER). Compared to conventional microgrid with fixed boundary, it can lead to better DER utilization and improved reliability. Previous literature has only considered the operation of a microgrid with a single island that is energized by stable voltage sources. This paper introduces control function designs that can effectively synchronize islands inside a dynamic boundary microgrid, depending on the operation status of each voltage source inside the islands. An overview of the components and rationale within the control function designs is provided, and hardware-in-the-loop simulation results are analyzed to demonstrate the effectiveness of the control functions.

In order to enable wireless charging of mobile electronics to compete with wired alternatives, wireless receivers need to operate at power levels sufficient to accommodate fast-charging standards. The receiver efficiency, harmonic content and total volume are key design metrics for wireless receivers. In this paper, four candidate topologies are compared, under 20 W fast-changing conditions, with respect to power loss, harmonic distortion, and power density. Each of the metrics are analyzed and verified experimentally. In coordination with the transmitter, a system-level approach to minimizing distortion is presented. Finally, the multilevel switched-capacitor rectifier is demonstrated to be a good candidate for wireless fast charging of mobile devices with high efficiency, small size, and suitable structure for future integration.

For medium to high power application, due to the soft saturation and relatively higher saturation flux density, the powder and amorphous cores are commonly chosen for the DM inductors to achieve high power density in the EMI filter design. One of the issues of these materials is their permeability variation with operating current bias. Even for ac application, the three-phase currents at different switching cycles during one line cycle varies greatly, which leads to a variable DM inductance at different time intervals during one line cycle. Since the three-phase system has the unequal instantaneous currents for three phases, current-bias dependent permeability will cause the unbalanced DM inductance/impedance which converts DM noise to CM noise, also called mixed-mode (MM) noise. In this paper, the characteristics of current-bias dependent permeability are investigated for several commonly adopted DM core materials. In addition, a time domain variable inductance model considering current-bias characteristics is developed and applied to evaluate its impacts on the CM noise and the CM filter design. The phenomenon and proposed model are experimentally verified on a 10 kW three-level ANPC converter.

The accurate leakage inductance modeling of common mode chokes (CMCs) can reduce trial-and-error filter debugging efforts and help avoid the saturation issue caused by the leakage flux. However, the analytical leakage inductance model is difficult to derive due to the complex leakage flux distribution. This paper presents a data-driven approach to model the CMC leakage inductance. A large amount of the leakage inductance data is collected by sweeping the selected input variables for the 3D finite element method (FEM) simulation. Then the data is trained by Artificial Neutral Network (ANN) to regress the nonlinear relationship between the leakage inductance and selected input variables. To verify the proposed method, core ZW4310TC is selected to model the relationship between the leakage inductance and winding parameters. Three CMCs with core ZW4310TC were built with different winding parameters and their leakage inductances were measured to verify the model. Compared with a previous analytical model, the error was reduced from 42.9% to 1.3% at the case where the previous model has the worst accuracy.

Coaxial shunt resistors are very useful for measuring the ultra-fast current in wide-bandgap device switching transients. One of their major drawbacks is the relatively large parasitic inductance. The traditional coaxial shunt resistors are reviewed and the relationship between energy rating and parasitic inductance is determined. The parasitic inductance can be greatly reduced with a lower energy rating. A measurement method for characterizing their up to GHz bandwidth is also reported. Lower than expected bandwidth was observed and a fix using measured transfer characteristics is therefore described.

Zero voltage switching (ZVS) has been widely implemented to improve the efficiency and robustness of high switching frequency converters. However, once the converter loses ZVS, the abrupt increase in switching loss decreases efficiency and may damage the converter. In this paper, a voltage slope-based detection method is proposed to detect ZVS status and prevent the converter from continuously hard switching. This detection circuit converts the voltage slope of the switching node to a dc voltage, which is compared with a reference voltage for the ZVS criterion. When hard switching occurs, two actions can be chosen: either shutting down the converter or adjusting the dead time to regain ZVS. The detection is achieved with simple circuitry and little control effort. A 6.78 MHz inverter for WPT application is used to verify this detection method. Experimental results show that ZVS status is detected effectively.

Active rectifiers in wireless power transfer systems exhibit many benefits compared to diode rectifiers, including increased efficiency, controllable impedance, and regulation capability. To achieve these benefits, the receivers must synchronize their switching frequency to the transmitter to avoid sub-fundamental beat frequency oscillations. Without additional communication, the receiver must synchronize to locally-sensed signals, such as voltages and currents induced in the power stage by the transmitter. However, the waveforms in the receiver are dependent on both the transmitter and receiver operation, resulting in an internal feedback between sensing and synchronization which prohibits the use of traditional phase-locked-loop design techniques. In this digest, a discrete time state space model is developed and used to derive a small signal model of these interactions for the purpose of designing stable closed-loop synchronization control. A prototype 150 kHz wireless power transfer converter is used to experimentally validate the modeling, showcasing stable synchronization.

A multi-layer non-uniform self-resonant coil is proposed in this paper for wireless power transfer applications. Multiple layers of spiral coils are stacked up, and the capacitance between them is controlled by a dielectric material between the copper layers. The coil current is shared among all layers, and the current sharing ratio is determined by the variable-width spiral tracks. Compared with a two-layer self-resonant coil, current sharing across the multi-layer structure reduces total copper loss. The analytical model for the proposed coil is provided and used to optimize the design of the coil. Both finite-element simulation and prototype testing of a three-layer design are used to validate the model. The results confirm the predicted high quality factor series resonant behavior.

This paper presents the design and implementation of a boundary current mode (BCM) modulated GaN-based single phase inverter using a combination of bipolar and unipolar switching. Both unipolar and bipolar BCM-switched full bridge inverters are explored in detail in the context of efficiency, output current distortion and leakage current. Although the unipolar switched BCM inverter results in a higher efficiency in comparison to the bipolar switched inverter, it leads to a higher output current distortion at the low frequency zero crossing. On the other hand, the bipolar switched BCM inverter yields a low leakage current and reduced output current distortion, but exhibits lower efficiency. To overcome the low frequency zero crossing current distortion while maintaining a high efficiency, a combination of bipolar and unipolar switching in a BCM inverter is proposed. An experimental prototype has been built to validate the proposed control technique and modulation scheme. The proposed approach achieves a 2% efficiency improvement in comparison to the standard bipolar switched BCM inverter and a THD of 1.15%.

With increasing deployment of inverter-based sources in microgrids, inverter control methods are constantly being modified and improved. What remains constant, however, is the phase-locked loop (PLL). Regardless of the control technique adopted and the type of microgrid, a PLL is used to synchronize the output PWM signal of the inverter with the main grid or other inverters. But as penetration of inverter-based sources increases and grids become weaker, the impact of PLLs on controller behavior becomes more pronounced. The issues caused by these influences are described in this paper to make a case for finding a solution for inverter synchronization that better fits the needs of inverter-dominated microgrids than PLLs. Simulation results from a study of a low-voltage microgrid supported by parallel inverters are also presented to demonstrate some of these characteristics.

Many energy storage systems that use technologies such as batteries are composed of power electronics conditioning systems and battery management systems. These are often produced by multiple manufacturers and require hardware and software integration for full grid functionality. This paper proposes an agent-based framework to support the development of an energy storage system with standardized communications. This framework can be utilized with different power conversion systems with an appropriate hardware interface.

This paper proposes a simple and accurate design method for air gapped inductors. Using inductor models with fringing effect, the proposed method systematically evaluates possible combinations of cores, turn numbers, and air gap lengths within the given constraints, including core geometries and magnetic saturation. Design examples show that the proposed method reduces the number of turns as well as the core size compared to the conventional methods. The method features simplicity in both algorithm and calculation since it only requires a small number of iteration loops. Various models involved in inductor design, including inductance, flux density, loss and thermal, can be readily incorporated into the proposed method.

Sorting algorithm is required for operating modular multilevel converter (MMC) with nearest level modulation, to keep the unbalanced submodule capacitor voltage within an acceptable range. Several sorting algorithms have been proposed in previous literatures. However, very few papers discussed about how to select the execution frequency of a sorting algorithm. This paper aims to investigate on the impact of the execution frequency in sorting algorithm on the output voltage harmonics, average switching frequency, submodule capacitor voltage fluctuation of an MMC using nearest level modulation. Multiple MMC models with different number of submodules are built in MATLAB/Simulink. Three different types of sorting algorithms are implemented, and evaluated at various execution frequencies as well as different operating points. Conclusions drawn from the extensive simulations show that to select a sorting algorithm and its execution frequency, all three performance criterions should be considered simultaneous and a minimum execution frequency is always required.

The short-circuit robustness of 600 V/30 A GaN gate injection transistors (GITs) was evaluated under various operating conditions to determine the worst-case short-circuit scenario. Although a decrease in maximum short-circuit current was observed with higher bus voltage, the short-circuit withstand time decreases dramatically. At room temperature and a bus voltage of 500 V, the short-circuit withstand time is as short as 160 ns as opposed to 220 ns at 400 V. The withstand time also depends on the maximum short-circuit current and can be extended significantly by reducing the drain current during a short-circuit event. The devices were shown to withstand a short-circuit event for considerably longer period with an elevated initial junction temperature as a result of lower drain current. With short-circuit current reduced from 110 A to 70 A, the withstand time was increased from 215 ns at 25°C to over 10 μs at 150°C and Vdc= 400 V. A gate-sensing protection scheme for GaN GIT was evaluated over various operating conditions and shown to successfully protect devices in less than 150 ns after short-circuit condition up to Tj = 150°C and Vdc= 500 V.

A fast and reliable overcurrent protection scheme is crucial for the converter reliability. It is also critical for double pulse test stations where newer devices or even engineering samples are tested, and device failures can be costly. A fast overcurrent protection scheme using the direct current measurement in the double pulse test is demonstrated and 7.55 ns fault response delay time is achieved. The total fault clearing time is determined by the fault signal propagation and device switching speed. Around 100 ns and 60 ns fault clearing time is achieved for SiC and GaN devices, respectively. The much faster protection can potentially simplify the gate driver design and reduce the energy rating of the coaxial shunt resistor. Since the overcurrent detection is directly attached to the current measurement, its impact on the measurement bandwidth is also discussed.

The short-circuit robustness of 600 V/30 A GaN gate injection transistors (GITs) was evaluated under various operating conditions to determine the worst-case short-circuit scenario. Although a decrease in maximum short-circuit current was observed with higher bus voltage, the short-circuit withstand time decreases dramatically. At room temperature and a bus voltage of 500 V, the short-circuit withstand time is as short as 160 ns as opposed to 220 ns at 400 V. The withstand time also depends on the maximum short-circuit current and can be extended significantly by reducing the drain current during a short-circuit event. The devices were shown to withstand a short-circuit event for considerably longer period with an elevated initial junction temperature as a result of lower drain current. With short-circuit current reduced from 110 A to 70 A, the withstand time was increased from 215 ns at 25°C to over 10 μs at 150°C and Vdc= 400 V. A gate-sensing protection scheme for GaN GIT was evaluated over various operating conditions and shown to successfully protect devices in less than 150 ns after short-circuit condition up to Tj = 150°C and Vdc= 500 V.

A fast and reliable overcurrent protection scheme is crucial for the converter reliability. It is also critical for double pulse test stations where newer devices or even engineering samples are tested, and device failures can be costly. A fast overcurrent protection scheme using the direct current measurement in the double pulse test is demonstrated and 7.55 ns fault response delay time is achieved. The total fault clearing time is determined by the fault signal propagation and device switching speed. Around 100 ns and 60 ns fault clearing time is achieved for SiC and GaN devices, respectively. The much faster protection can potentially simplify the gate driver design and reduce the energy rating of the coaxial shunt resistor. Since the overcurrent detection is directly attached to the current measurement, its impact on the measurement bandwidth is also discussed.

Modular multilevel converters (MMCs) have been widely adopted for high voltage direct current (HVDC) applications and have been targeted for use in future dc grids as well. However, most of the MMC research is still limited to digital simulations or relied on hardware demonstrations with a specific setup and limited number of submodules (SMs). In this paper, a MMC test-bed with 10 SMs in each arm is developed that has flexible reconfiguration of the MMC topologies, switching frequencies, and passive element parameters. The MMC test-bed hardware construction, control scheme, and communication architecture are described, and typical MMC scenarios are conducted to verify its multiple functions.

One of the popular converter topologies applied in high power dc-ac applications is the three-level active neutral point clamped (ANPC). Owing to relatively low switching frequency and slow switching speed of these topologies in high power applications, the commutation loop analysis in these topologies has not been fully conducted, and the over-voltage issue of non-active switches has not been thoroughly analyzed. This paper reveals an over-voltage issue on non-active switches in three level inverters due to multi-commutation loop. The detailed mode analysis during the commutation and related over-voltage issue are given. Finally, Si-based ANPC with 140 kHz switching frequency and SiC-based ANPC converters with 280 kHz switching frequency and high switching speed are tested respectively to compare and verify the over-voltage issue for non-active switches.

This work examines the application of GaN within Class D audio by providing a side-by-side comparison of enhancement-mode GaN devices with currently available silicon MOSFETs with 60 V drain-to-source voltage ratings. GaN in Class D audio will allow for lower heat radiation, smaller circuit footprints, and longer battery life as compared to Si MOSFETs with a negligible trade-off for quality of sound.

Understanding the CM inductor core saturation mechanism and reducing core flux density is critical for CM inductor design optimization. Instead of a time domain method, this paper introduces frequency domain spectrum concept for CM inductor core saturation analysis and design optimization, which will provide designers a better understanding of CM inductor design. First, both core permeability and converter modulation index's opposite influence on DM flux density and CM flux density are identified. Then, CM flux density is further investigated based on the spectrum concept. Three components in the CM inductor which may cause large CM flux density and core saturation are summarized: (1) switching frequency related components, (2) impedance resonance frequency related components, and (3) modulation frequency related components. Each component is investigated for CM flux density reduction and filter design optimization. A connecting AC and DC side midpoint with notch filter structure is proposed to reduce modulation frequency related components. Experiment results are presented to verify the proposed concept and method.

Although SiC MOSFETs show superior switching performance compared to Si IGBTs, it is unknown whether SiC MOSFETs have the same advantage over Si super junction (SJ) MOSFETs such as CoolMOS. This paper analyzes the switching performance in different switching cell configurations and summarizes the impact factors that influence switching loss. A double pulse test is conducted for a SiC MOSFET and a CoolMOS with the same voltage and current rating. In the FET/diode cell structure, a SiC Schottky diode is used as the upper device to eliminate the reverse recovery, and the testing results show that the SiC MOSFET has 2.4 times higher switching loss than the Si CoolMOS. This can be explained by the smaller transconductance and the higher Miller voltage of the SiC MOSFET. On the other hand, the Si CooMOS has 10 times higher switching loss than the SiC MOSFET in the FET/FET cell structure because of the significant turn-on loss caused by the poor reverse recovery of its body diode.

Unlike conventional passive or active filters, an impedance balancing circuit reduces the common-mode (CM) electromagnetic interference (EMI) noise by establishing an impedance balancing bridge. The EMI noise can be significantly reduced when the impedance bridge is designed to be well balanced. This paper investigates impedance balancing circuits in Dc-fed motor drive systems where both DC input and AC output need to meet EMI standards and thus EMI filters are needed for both sides. An impedance balancing circuit is proposed to reduce both DC and AC side CM noise. Two auxiliary branches are added to the conventional passive filters to establish an impedance bridge and reduce CM noise. The design criteria are presented, and the impact of the proposed impedance balancing circuit on both sides CM noise are investigated. It shows that the proposed impedance balancing circuit can reduce DC side and AC side CM noise based on different mechanisms. The CM noise reduction performance of the proposed method does not depend on the motor and cable models. Experiment results are presented to demonstrate the feasibility and effectiveness of the proposed method.

Superconducting technologies such as motors together with the supporting cryogenic power electronic system are growing in importance in aircraft applications. It is critical to understand the influence of low temperature on filters of the power converter system in these applications. Also, it is worthwhile to investigate whether the converter system can achieve higher efficiency and high power density by utilizing the provided low temperature cooling environment. This paper conducted a comprehensive magnetic core characterization at low temperature to understand the core properties and support filter design at low temperature. The ferrite and nanocrystalline material are characterized from room temperature to cryogenic temperature in a wide range of operating frequencies. The results show that the permeability of ferrite material decreases by a factor of 7~8 and the core loss increases more than 10 times when operating at very low temperature. The permeability of nanocrystalline material decreases to 60% and the core loss increases 1.5~2.5 times when operating at very low temperature. The saturation flux density of both materials has slight increase at low temperature. Based on tested data, a case study of inductor design considering the low temperature cooling environment is presented to illustrate the influence of low temperature on inductor design.

In order to evaluate the feasibility of newly developed GaN devices in a cryogenic-cooled converter, this paper characterizes a 650 V enhancement-mode Gallium-Nitride heterojunction field-effect transistor (GaN HFET) at cryogenic temperatures. The characterization includes two parts: static and dynamic characterization. The results show that this GaN HEMT is an excellent device candidate to be applied in cryogenic-cooled applications. For example, transconductance at cryogenic temperature is 2.5 times of one at room temperature, and accordingly, peak di/dt during turn-on transients at cryogenic temperature is around 2 times of that at room temperature. Moreover, the on-resistance of the channel at cryogenic temperature is only one-fifth of that at room temperature.

Due to the low availability, high cost, and limited performance of high voltage power devices in high voltage high power applications, series-connection of low voltage switches is commonly considered. Practically, because of the dynamic voltage unbalance and the resultant reliability issue, switches in series-connection are not popular, especially for fast switching field-effect transistors such as silicon (Si) super junction MOSFETs, silicon carbide (SiC) JFETs, SiC MOSFETs, and gallium nitride (GaN) HEMTs, since their switching performance is highly sensitive to gate control, circuit parasitics, and device parameters. In the end, slight mismatch can introduce severe unbalanced voltage. This paper proposes an active voltage balancing scheme, including 1) tunable gate signal timing unit between series-connected switches with <; 1 ns precision resolution by utilizing a high resolution pulse-width modulator (HRPWM) which has existed in micro-controllers; and 2) online voltage unbalance monitor unit integrated with the gate drive as the feedback. Based on the latest generation 600-V Si CoolMOS, experimental results show that the dynamic voltage can be automatically well balanced in a wide range of operating conditions, and more importantly, the proposed scheme has no penalty for high-speed switching.

To operate a converter at cryogenic temperatures, understanding the characteristics of power semiconductor devices is critical. This paper presents the characterization of state-of-the-art 1.2 kV SiC MOSFETs from leading manufacturers at cryogenic temperatures. The testing setup consisting of a cryogenic chamber, and a liquid nitrogen Dewar is introduced. With a curve tracer and double pulse test, comprehensive characterization of the SiC MOSFETs including both static and switching performance is conducted and evaluated. Test results indicate the on-resistance increases while the breakdown voltage remains relatively constant at cryogenic temperatures. Other characteristics like threshold voltage and switching loss vary significantly at cryogenic temperatures among devices from different manufacturers.

Zero sequence circulating current (ZSCC) exists when paralleled inverters have common dc and ac sides without isolation. Most of the prior work on the ZSCC analysis and suppression depended on paralleled two-level inverters. The scenarios involved in the three-level converters are more complicated. This paper investigates the ZSCC in paralleled three-level active neutral point clamped (ANPC) inverters. The mechanisms causing potential ZSCC jump in three-level paralleled ANPC inverters are analyzed. The ZSCC patterns of different interleaved modulation schemes for three-level converters are illustrated. Then, the active vector dividing concept is extended to three-level converters, and a modulation scheme is proposed to reduce the high frequency ZSCC in three-level converters. Experiments have been conducted on two paralleled three-level inverters. The current jump in ZSCC is observed and mitigated. The ZSCC with proposed modulation scheme is reduced to less than half of the ZSCC with conventional continuous space vector modulation (CSVM) scheme.

To better utilize the existing electric power grid distribution network automation of smart switches, a microgrid can expand or shrink its electrical boundary according to available renewable generation. Previous literature only focused on the design of a microgrid with a dynamic boundary, but without considering real-time operation. This paper proposes a microgrid controller that enables operation of microgrid with dynamic boundary and can be integrated into the existing distribution automation system. The architecture of the control system is introduced, and the essential functions such as online topology assessment and synchronization are presented. Simulation results are given to demonstrate the feasibility of the proposed controller.

Switching transient overvoltage is inevitable in hard switching applications, and the faster switching speed of SiC MOSFETs suggests even worse overvoltage. This paper focuses on the turn-on overvoltage. To understand its nature, the switching transient is analyzed, and it shows the turn-on overvoltage is largely independent of load current condition. This phenomenon is verified by characterizing the turn-on overvoltage of a SiC MOFET and a SiC Schottky diode. Finally, a SPICE-based model is also built to understand the switching transient more accurately, and the modeling method can accurately predict the turn-on overvoltage and help select device voltage rating.

Dead-time, device output capacitance, and other non-ideal characteristics cause voltage error for the midpoint PWM voltage of the semiconductor phase-leg employed in a voltage-source inverter (VSI). Voltage-second balancing is a well-known concept to mitigate this distortion and improve converter power quality. This paper proposes a unique voltage-second balancing scheme for a SiC based voltage source inverter using online condition monitoring of turn-off delay time and drain-source voltage rise/fall time. This data is sent to the micro-controller to be used in an algorithm to actively adjust the duty cycle of the input PWM gate signals to match the voltage-second of the non-ideal output voltage with an ideal output voltage-second. The monitoring system also allows for this implementation to eliminate the need for precise current sensing and allows for the implementation to be load independent. Dynamic current sensing is still a developing technology, and each load has a unique effect on the output voltage distortion. Test results for a 1 kW half-bridge inverter implementing this monitoring system and voltage-second balancing scheme show a 70% enhancement on the error against the ideal fundamental current value of the output current and a 2% THD improvement on the output current low frequency harmonics.

A power converter based transmission line emulator has been developed for the hardware test-bed (HTB) platform, which emulates power systems by mimicking the system components with universal three-phase voltage source converters. In power grids, transmission line series compensation devices are utilized to enhance the power delivery capability and controllability by regulating the equivalent impedance of a transmission line. This paper proposes a method of mimicking variable capacitors and inductors to combine the series compensation device emulation into the transmission line emulator so that various power system scenarios can be studied. Simulation and experiment results verify the effectiveness of the transmission line emulation with integrated series compensation devices.

Battery energy storage systems (BESSs) are commonly used for frequency support services in power systems because they have fast response times and can frequently inject and absorb active power. Lithium-ion (Li-ion) BESSs dominate the grid energy storage market now, but Vanadium redox flow (VRB) BESSs are predicted to contend in future markets for large-scale storage systems. Previously, a Li-ion BESS emulator has been developed for a grid emulation system known as the Hardware Testbed (HTB), which consists of converters controlled to emulate different power system components. In this paper, we develop a VRB BESS emulator with a VRB-specific internal battery model and a power electronics interface similar to that of the Li-ion BESS emulator. Then, we compare the effectiveness of the VRB and Li-ion technologies for primary frequency regulation and inertia emulation applications. It is concluded that these two technologies are virtually indistinguishable from the power system's perspective when conducting these services over a short period of time.

In this paper, an extra junction capacitance and its associated switching commutation path are identified in three-level ac/dc converters, which were previously overlooked due to the off-state of the related device in half line cycle. The impact of this effect on power loss is analyzed, showing an underestimated switching loss in the traditional loss calculation of three-level converters. Through a proposed loss re-evaluation approach based on energy data of conventional double pulse tester (DPT), the corrected loss matches experimental results obtained from a 450kHz 650 V Gallium Nitride (GaN) based Vienna-type rectifier, showing 17.4% additional switching loss due to this effect. And the dominant extra switching loss is found to be Coss loss instead of overlap loss in WBG converters. Thefore, the effect is severe in high swtiching frequency high-speed wideband gap (WBG) based three-level converters.

Attenuation performance of an EMI filter can be significantly degraded by coupling, parasitics, and frequency-dependent nonlinearity of magnetic cores. In this paper, the effect due to mutual capacitive coupling in filter structures with T-shape joint is identified and investigated. Its mechanism indicates that this coupling is the dominant cause of performance degradation in T-shape filters. PCB slits and grounded shielding are proposed as two effective mitigation solutions, respectively, and are further combined to improve filter transfer gain up to 40 dB along the high frequency range. Experimental results obtained from a three-phase LCL common-mode (CM) filter verify the significant impact of this coupling and the effectiveness of the proposed mitigation methods.

In a converter based on 10 kV SiC MOSFETs, major sources of parasitic capacitance are the anti-parallel junction barrier schottky (JBS) diode, heat sink, and load inductor. A half bridge phase leg test setup is built to investigate these parasitic capacitors' impact on the switching performance at 6.25 kV. Generally these parasitic capacitors slows down both turn-on and turn-off transient and can cause significant increase in switching energy loss. The impact of the parasitic capacitor in the load inductor is analyzed, which has either very short wire or long wire in series. Switching performance of the phase leg with two different thermal designs are compared to investigate the impact of the parasitic capacitor due to the heat sink. The large parasitic capacitor due to the large drain plate of discrete 10 kV SiC MOSFET for heat dissipation can result in 44.5% increase in switching energy loss at low load current.

Data centers consume an ever-increasing amount of electricity because of the rapid growth of cloud computing and digital information storage. A high voltage point of load (HV POL) converter is proposed to convert the 400-VDC distribution voltage to 1-VDC within a single stage to increase the power conversion efficiency. A six-phase input series output parallel (ISOP) connected structure is implemented for the HV POL. The symmetrical controlled half bridge current doubler is selected as the converter topology in the ISOP structure. The full load efficiency is improved by 4% points compared with state of the art products. A voltage compensator has been designed in order to meet the strict dynamic voltage regulation requirement. A laboratory prototype has been built, and experimental results have been provided to verify the proposed HV POL with a single power conversion stage can meet the dynamic voltage regulation requirement for an on-board power supply with higher efficiency compared to the conventional architecture.

The frequency decoupling effect of the voltage source converter (VSC)-based high voltage dc (HVDC) transmission makes frequency support unavailable between two ac subsystems interconnected by the HVDC link. Recently, several algorithms have been proposed and demonstrated to improve the ac system stability by implementing inertia emulation (IE) functions in the HVDC VSC stations. However, the capability of the VSC-HVDC to achieve the IE control is not clear. According to the previous research, the IE control strategy has been studied without concerning the impact of the practical control process, which will introduce some time delay into the IE realization. In this paper, a detailed multi-terminal HVDC VSC control module, including the phase-locked loop (PLL) and low pass filter (LPF), is considered in order to analyze the multi-terminal HVDC network impact on the IE performance. The analysis indicates that the frequency performance of the ac network with IE integrated HVDC transmission can be nearly as good as that directly connected with the ac subsystem which involves a high penetration of conventional generation units, except for the short time delay introduced by the VSC control modules. The effectiveness of IE performance will be compromised if the response delay is significant. The simulation results have verified the analysis.

As wide bandgap (WBG) semiconductors are gradually adopted for high switching frequency high power-density power converter, new challenges arise from control to hardware design. In this paper, an improved input current sampling method is proposed for three-phase rectifiers to avoid sampling noises when rectifiers are operated at high speed and high switching frequency. Experimental results obtained from a 450-kHz enhancement-mode Gallium Nitride (GaN) high-electron-mobility transistor (HEMT) based three-phase three-level Vienna-type rectifier demonstrate the good performance of the sampling method.

Practical distribution system contains many nodes and short branches. As a result, a more efficient and stable distribution state estimation (DSE) algorithm is needed to properly handle the inverse operation of its large-scale ill-conditioned information matrix. This paper proposed a two-stage DSE algorithm to transform the inverse operation into addition and multiplication operations in a recursive manner. It includes pseudo measurement preprocessing in the offline stage where an approximate linear estimator is adopted to relieve most of computation burdens, and real-time correction in the online stage where a nonlinear estimator is used to update the estimation. Numerical results of the method applied to both IEEE standard test systems and an actual distribution system show the accuracy and effectiveness of the proposed algorithm.

The short circuit performance of a 3rd generation 10 kV/20 A SiC MOSFET with short channel is characterized in this paper. The platform consisting of a phase-leg configuration, which can test both hard switching fault (HSF) and fault under load (FUL) types of fault, is introduced in detail. A Si IGBT based solid state circuit breaker is developed for short circuit test. The short circuit protection having a response time of 1.5 μs is validated by the test platform. The short circuit characteristics for both the HSF and FUL types at 6 kV DC-link are presented and analyzed.

The impact of the body diode and the anti-parallel junction barrier Schottky (JBS) diode on the switching performance of the 3rd generation 10 kV SiC MOSFET from Wolfspeed/Cree is investigated in detail at various junction temperatures. The switching performance with and without the anti-parallel JBS diode is tested by specific layout design of the 10 kV MOSFET module. The body diode of the 10 kV SiC MOSFET has excellent reverse recovery performance from 25°C to 125 °C, indicating it is a suitable candidate for freewheeling diode. The application of anti-parallel JBS diode will slow down the turn-off transient and result in lower turn-off dv/dt and higher turn-off energy loss, while its impact on the turn-on transient is not significant.

The dead-time in voltage source converters can have significant impact on power quality and efficiency, and because these losses scale proportionally with switching frequency, it is important to study the impact of these losses in wide bandgap based converters, like SiC and GaN. This paper focuses on the impact of dead-time on the total loss of a 5 kW, single phase, GaN-based inverter, and an experimental model of dead-time losses for various dead-times was developed based on static and dynamic characterization results. The results show that in a GaN-based voltage source inverter (VSI), a 100 ns dead-time setting can attribute up to 30% additional switching loss and is a strong function of load current level and temperature. A comparison of losses between fixed and adaptive dead-time was studied, and an optimal fixed dead-time setting based on the analysis was implemented and verified in experiment.

In this work, a hybrid switched-capacitor/PWM converter is analyzed and designed for battery charging in mobile electronics. Operation of the converter is reviewed to construct a complete analytical loss model based on FET extracted parameters for an integrated circuit implementation. The model is validated with experimental results and compared with other converter topologies in the same application. The loss modeling is used to optimize the physical scaling of the power transistors to minimize total losses.

This paper presents a new boundary condition for designing phase legs when using the decoupling capacitance method. New SiC MOSFETs have much higher short-circuit currents-over 14X datasheet rating-then comparable Si IGBT devices. The energy draw on the decoupling capacitance due to this can be a large step input that over-voltages the device if not accounted for. Decoupling capacitance requirements have previously been based on switching conditions during normal operation and may not be sufficient for high current devices or modules. Furthermore, fast protection work has focused on lower current discrete devices whereas this issue becomes more prevalent in higher current configurations. Analysis of device over-voltage during short-circuit events is presented along with new sizing guidelines for DC link decoupling capacitance.

This paper presents the occurrence of potentially destructive oscillation in paralleled power MOSFETs during short-circuit events. Paralleling discrete power devices is desirable in many designs in order to increase power output. Short circuits cause high voltages, saturation current and local temperatures creating unstable environments within devices. Current redistribution can occur between device gates in this environment which can excite oscillation in parallel circuitry if not properly accounted for. Analysis of the phenomenon including experimental results are presented along with mitigation steps.

Resonant magnetic wireless power transfer (WPT) has potential to improve spatial freedom, allow simultaneous charging of multiple devices, and increase circuit power density. However, many obstacles must first be overcome before the benefits of this technology are fully realized. Due to the high frequency of the WPT carrier, autonomous receiver-side synchronization and control presents significant difficulties. This work addresses the control strategy of a 6.78 MHz GaN-based synchronous WPT rectifier. A zero-crossing current sensing scheme is used to both synchronize the receiver switching frequency and to enable control of its input phase. The rectifier is shown to be capable of regulating its output voltage by changing its input phase, highlighting the value of a circuit that has real-time control over the reactive part of its input impedance. The current sensing, frequency synchronization, and input phase control capabilities of the circuit are demonstrated experimentally and discussed in detail.

To overcome the increased switching losses in high frequency power electronics, control-based modulation techniques such as boundary current mode (BCM) are commonly used in full bridge inverter and rectifier topologies to guarantee zero voltage switching (ZVS). Traditionally, in order to implement BCM modulation, a combination of current programmed mode (CPM) control and model-based techniques are used. The former is highly susceptible to noise and sensing delay, while the latter is subject to modeling error. In this work, a dual-current programmed mode (DCPM) control circuit for BCM operation is designed and implemented. The proposed control network achieves better noise immunity and low propagation delay at high frequency while regulating peak and valley currents in each period. The operation of this control scheme is demonstrated experimentally using a GaN-based half bridge inverter prototype.

Middle-point inductance Lmiddle can be introduced in power module designs with P-cell/N-cell concept. In this paper, the effect of middle-point inductance on switching transients is analyzed first using frequency domain analysis. Then a dedicated multiple-chip power module is fabricated with the capability of varying Lmiddle. Extensive switching tests are conducted to evaluate the device's switching performance at different values of Lmiddle. Experiment result shows that the active MOSFET's turn-on loss will decrease at higher values of Lmiddle while its turn-off loss will increase. Detailed analysis of this loss variation is presented. In addition to switching loss variation, it is also observed that different voltage stresses are imposed on the active switch and anti-parallel diode. Specifically, in the case of lower MOSFET's turn-off, the maximum voltage of lower MOSFET increases as Lmiddle goes up; however, the peak voltage of anti-parallel diode decreases significantly. The analysis and experiment results will provide design guidelines for multiple-chip power module package design with P-cell/N-cell concept.

With the development of power electronics, three-phase voltage source inverters(VSls) are widely used in industry application. In this paper a SiC device based EV battery charger consisting of dual active bridge(DAB) and three-phase four-wire VSI is built. In order to undertake the unbalanced load, an independently controlled neutral module(ICNM) has been adopted for the VSI control to form the neutral line and provide the path for the zero-sequence current. Split DC-bus capacitors with the fourth leg are equipped to the conventional VSI. Meanwhile, the control performance is improved by paralleling virtual resistors to the load, namely, notch-filter-incorporated capacitor voltage feedback control(NF-CVFC), which not only enhances the quality of the output voltage but also ensures the system stability. Finally, a 10kW prototype is built and tested. Experimental results verified the proposed control strategy and the practical feasibility.

Wide-Bandgap devices are believed to be promising candidates for the next-generation power electronics converter. However, the prohibitive cost and limited variety are still the main constrains before being widely used. One possible solution to mitigate these issues is hybrid switches, a combination of Si MOSFETs and WBG devices. To maximize merits of both GaN HEMT and Si MOSFET, this paper proposes a hybrid switch consisting of two GaN HEMTs and two Si MOSFETs. For such a design, a robust gate-drive loop is critical to secure the safe operation of all switches. As an instructive work, this paper presents a comprehensive analysis of the switching transient process and its impact on the gate-drive loop, practical tuning tips of gate-drive loop design are also given based on the simulation and experimental results. A 400V/ 80A full bridge prototype is developed to validate our design. Experimental result shows that, with enhanced gate-drive loop, we can continuously turn off 400V/80A@100kHz and 400V/40A@300kHz with only one GaN device paralleled to two commercial Si MOSFETs.

A planar coil structure that exhibits a series self-resonant behavior is developed for wireless power transfer systems which use magnetic resonant coupling. The proposed structure uses two thin, planar, spiral tracks separated by one layer of dielectric. By connecting to alternate ends of each track, the coil shows a series LC impedance, which is often necessary for voltage source inverters. An analytical model for the inductance, capacitance and resistance is used to develop a geometric design method that minimizes resistance given a set of application constraints. Experimental coils made with an FR4 PCB and an Teflon-ceramic PCB verify the proposed structure and modeling.

A single-stage transmitter is reviewed which directly converts a utility ac input to high frequency (6.78 MHz) ac output for wireless power transfer applications. Compared with a two-stage transmitter implementation, this single-stage transmitter obtains high power efficiency with reduced component-count. In this paper, a method is proposed to enable constant current at the output of the single-stage transmitter to accommodate multiple receivers. First, the constant output voltage transmitter is obtained by implementing closed-loop control and a model-based modulation scheme. Then, an impedance matching network is implemented at the output of transmitter to convert the constant voltage to constant current. This feature allows a single transmitter to charge multiple receivers simultaneously. The control methodology is verified using both simulation and a laboratory prototype.

A single-stage transmitter is reviewed, which directly converts a utility ac input to high frequency (6.78 MHz) ac output for wireless power transmission. By integrating two stages (totem-pole PFC rectifier and full bridge inverter) into a single stage, the topology achieves high efficiency and reduced component count. In this paper, a simple auxiliary circuit is added to allow the single-stage transmitter to operate in two modes. At heavy load, the transmitter operates as a totem-pole rectifier with PFC and achieves low distortion of the input current. At light load, the circuit operates as a voltage-doubler rectifier (VDR), extending the ZVS range of the transmitter. As a result, hard switching is avoided and efficiency is improved at light load. This improved single-stage transmitter is verified by a 100 W, GaN-based laboratory prototype.

The call for higher power and larger spatial freedom has driven the operating frequency of wireless power transfer (WPT) systems into the MHz range. Previous system design methods focus on designing the coils to attain high quality factor while remaining resonant around the working frequency and subsequently designing switching circuit hardware and operating point to minimize the system power loss. This sequential design method over-simplifies the system, neglecting inter-dependencies between system components, which leads to suboptimal designs. This paper presents a system design method that co-optimizes coils, power stages, and circuit operation for maximum overall efficiency, based on accurate models of converters and WPT system. The system model and the importance of co-design are verified by a 6.78 MHz WPT prototype.

In mobile electronics applications, the high conduction loss on the ac-dc rectifier and the coil is a barrier to the application of wireless charging. In this paper, a wireless charging architecture employing a 7-level switched-capacitor (SC) ac-dc rectifier is investigated, showing a substantial reduction of the conduction losses on the transmitter, the coil and the receiver. The proposed SC rectifier also features a multilevel design with good scalability to accommodate different power ratings, and potentially reduce the harmonic contents of the input voltage. The principle and operation are verified using a 7-level, 20 W, 5-9 Vdc output, 150 kHz prototype. The measured peak dc-to-load system efficiency is above 90%. The high-power density design without bulky magnetic components is suitable for the implementation in low-profile mobile electronics.

This paper presents a modeling approach for dual active bridge (DAB) converter in electric vehicle (EV) applications which considers the magnetizing inductance effect of the high-frequency transformer. A Typical DAB transformer has very high magnetizing inductance compared to the leakage inductance. As a result, the magnetizing current can be neglected. However, for integrated and hybrid converters, where the same core is used for both DC excitation and AC excitation, an air gap is used to prevent core saturation. In such applications, the effect of magnetizing inductance needs to be considered for DAB converter modeling. For accurate estimation of the DAB converter, a loss model considering magnetizing inductance is developed in this paper. Finite element analysis (FEA) is performed to model the transformer to evaluate the proximity loss and fringe induced eddy current loss mechanisms. An experimental prototype of the DAB converter is developed to verify the proposed model. Experimental waveforms are presented and compared for different power level and switching frequency.

Wide bandgap (WBG) semiconductor devices and cryogenic cooling are key enablers for highly-efficient ultra-dense power electronics converters, which are critical for future more electric aircraft applications. For the development and optimization of a cryogenically-cooled converter, an understanding of power semiconductor characteristics, especially for emerging WBG devices, is critical. This paper focuses on WBG device characterization at cryogenic temperatures. First, the testing setup for cryogenic temperature characterization is introduced. Then several WBG device candidates (e.g., 1200-V SiC MOSFETs and 650-V GaN HEMTs) are characterized from room to cryogenic temperatures. The test results are presented with trends summarized and analyzed, including on-state resistance, breakdown voltage, and switching performance.

As the effort to maximize the potential of SiC devices, the Field Programmable Gate Array (FPGA) is utilized in this paper to achieve high control bandwidth (>200 kHz) when implementing the Field-oriented Control (FOC) algorithm. This can greatly enhance the high-frequency injection (HFI) sensorless control for Permanent Magnet Synchronous Motors (PMSMs) by widening the applicable speed range, for instance, increasing the injection frequency up to 2 kHz from the conventional 500Hz. To offset the cost, it is also validated that one FPGA can control two motors simultaneously.

Automated vehicles require sensors and computer processing that can perceive the surrounding environment and make real time decisions. These additional electrical loads expand the auxiliary load profile, therefore reducing the range of an automated electric vehicle compared to a standard electric vehicle. Furthermore, a fully automated vehicle must be fail-safe from sensor to vehicle control, thus demanding additional electrical loads due to redundancies in hardware throughout the vehicle. This paper presents a review of the sensors needed to make a vehicle automated, the power required for these additional auxiliary loads, and the necessary electrical architectures for increasing levels of robustness.