To support the use of SiGe BiCMOS for future mission targets such as Europa, which are subject to high radiation doses and cryogenic temperatures, SiGe HBTs were exposed to 1-MeV electrons to 5 Mrad(Si) at 300, 200, and 115 K. The presented results are the first in-situ characterization of electron irradiation at cryogenic temperatures in SiGe HBTs. Lower temperature was found to improve TID tolerance. Physical mechanisms behind this improved tolerance with cooling are examined, such as trap formation due to particle bombardment and the trapping/de-trapping of carriers at oxide/semiconductor interfaces. The results of the present work demonstrate that SiGe HBTs enjoy improved TID tolerance in addition to higher performance at cryogenic temperatures, supporting the use of SiGe BiCMOS as enabling technology platforms for space missions to harsh environments like Europa.

This article establishes an analytical model for the device drain-source overvoltage related to the two loops in three-level active neutral point clamped (3L-ANPC) converters. Taking into account the nonlinear device output capacitance, two common modulation methods are investigated in detail. The results show that the line switching frequency device usually has higher overvoltage, and the switching speed of the high switching frequency device is not strongly influenced by the multiple loops. By keeping the nonactive clamping switch off, the effect of the nonlinear device output capacitance can be significantly mitigated, which helps reduce the overvoltage. Moreover, the loop inductance can be reduced with vertical loop layout and magnetic cancellation in the printed circuit board and busbar design. A 500-kVA 3L-ANPC converter using silicon carbide mosfets was built and tested. The experimental results validate the overvoltage model of the two modulation methods as well as the busbar design. With the nonactive clamping switch off, the overvoltage of both the high and line switching frequency devices is significantly reduced, which helps achieve higher switching speed.

In order to evaluate the feasibility of newly developed gallium nitride (GaN) devices in a cryogenically cooled converter, this article characterizes a 650-V enhancement-mode GaN high-electron mobility transistor (GaN HEMT) at cryogenic temperatures. The characterization includes both static and dynamic behaviors. The results show that this GaN HEMT is an excellent device candidate to be applied in cryogenic-cooled applications. For example, transconductance at cryogenic temperature (93 K) is 2.5 times higher than one at room temperature (298 K), and accordingly, peak di/dt during turn-on transients at cryogenic temperature is around 2 times of that at room temperature. Moreover, the ON-resistance of the channel at the cryogenic temperature is only one-fifth of that at room temperature. The corresponding explanations of performance trends at cryogenic temperatures are also given from the view of semiconductor physics. In addition, several device failures were observed during the dynamic characterization of GaN HEMTs at cryogenic temperatures. The ultrafast switching speed-induced high di/dt and dv/dt at cryogenic temperatures amplify the negative effects of parasitics inside the switching loop. Based on failure waveforms, two failure modes were classified, and detailed failure mechanisms caused by ultrafast switching speed are given in this article.

To better support the superconducting propulsion system in the future aircraft applications, the technologies of high-power high switching frequency power electronics systems at cryogenic temperatures should be investigated. This article presents the development of a 40-kW cryogenically cooled three-level active neutral point clamped inverter with 3 kHz output line frequency and 140 kHz switching frequency. Si mosfets are characterized at cryogenic temperatures, and the results show that they have promising performance such as lower on-resistance and switching loss. The design of the inverter is presented in detail with the special consideration of the cryogenic temperature operation. Moreover, a packaging and integration architecture is designed and fabricated to demonstrate the feasibility and performance of the inverter in the lab. It is able to achieve no leakage with good thermal and air insulation. With the inverter and packaging, the experimental results show that the inverter operates properly at cryogenic temperatures. The loss is measured at different load conditions, and the loss analysis is given, which shows that the cryogenically cooled inverter has 30% less loss than operating at room temperature.

Paralleling three phase three-level inverters is gaining popularity in industrial applications. However, analytical models for the harmonics calculation of a three-level neutral point clamped (NPC) inverter with popular space vector modulation (SVM) are not found in the literature. Moreover, how interleaving angle impacts the dc- and ac-side harmonics and electromagnetic interference (EMI) harmonics in parallel interleaved three-level inverters and how to optimize interleaving angle to reduce these harmonics have not been discussed in the literature. Furthering previous study, this article presents the modeling, analysis, and reduction of harmonics in paralleled and interleaved three-level NPC inverters with SVM. Analytical models for harmonic calculation are developed, and the dc-side harmonics characteristics of an NPC inverter are identified. The impact of interleaving angle on the ac-side voltage and dc-link current harmonics of parallel interleaved three-level NPC inverters is comprehensively studied. The impact of switching frequency and interleaving angle on EMI harmonics is also illustrated. Optimal interleaving angle ranges to reduce these harmonics are derived analytically. The developed models and harmonic reduction analysis are verified experimentally with two paralleled and interleaved three-level NPC inverters.

In order to apply power electronics systems to applications such as superconducting systems under cryogenic temperatures, it is necessary to investigate the characteristics of different parts in the power electronics system. This article reviews the influence of cryogenic temperature on power semiconductor devices including Si and wide bandgap switches, integrated circuits, passive components, interconnection and dielectric materials, and some typical cryogenic converter systems. Also, the basic theories and principles are given to explain the trends for different aspects of cryogenically cooled converters. Based on the review, Si active power devices, bulk Complementary metal-oxide-semiconductor (CMOS) based integrated circuits, nanocrystalline and amorphous magnetic cores, NP0 ceramic and film capacitors, thin/metal film and wirewound resistors are the components suitable for cryogenic operation. Pb-rich PbSn solder or In solder, classic printed circuit boards material, most insulation papers and epoxy encapsulant are good interconnection and dielectric parts for cryogenic temperatures.

Three-level converters are more susceptible to parasitics compared with two-level converters because of their complicated structure with multiple switching loops. This paper presents the methodology of busbar layout design for three-level converters based on magnetic cancellation effect. The methodology can fit for 3L converters with symmetric and asymmetric configurations. A detailed design example is provided for a high power three-level active neutral point clamped (ANPC) converter, which includes the module selection, busbar layout, and DC-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. The results match with each other, and the inductances of short and long loops are 6.5 nH and 17.5 nH respectively, which are significantly lower than the busbars of NPC type converters in other references.

To understand the limitation of maximizing the switching speed of SiC low current discrete devices and high current power modules in hard switching applications, double pulse tests are conducted and the testing results are analyzed. For power modules, the switching speed is generally limited by the parasitics rather than the gate drive capability. For discrete SiC devices, the conventional voltage source gate drive (VSG) is not sufficient to maximize the switching speed even if the external gate resistance is minimized. The limitation of existing current source gate drives (CSG) are analyzed, and a CSG dedicated for SiC discrete devices is proposed, which can provide constant current during the switching transient regardless of the high Miller voltage and large internal gate resistance. Compared with the conventional VSG, the proposed CSG achieves 67% faster turnon time and 50% turn-off time, and 68% reduction in switching loss at full load condition.

Junction temperature is an important design/operation parameter, as well as, a significant indicator of device's health condition for power electronics converters. Compared to its silicon (Si) counterparts, it is more critical for silicon carbide (SiC) devices due to the reliability concern introduced by the immaturity of new material and packaging. This paper proposes a practical implementation using an intelligent gate drive for online junction temperature monitoring of SiC devices based on turn-off delay time as the thermo-sensitive electrical parameter. First, the sensitivity of turn-off delay time on the junction temperature for fast switching SiC devices is analyzed. A gate impedance regulation assist circuit is proposed to enhance the sensitivity by a factor of 60 and approach 736 ps/°C tested in the case study with little penalty on the power conversion performance. Next, an online monitoring unit based on gate assist circuits is developed to monitor the turn-off delay time in real time with the resolution less than 104 ps. As a result, the micro-controller is capable of “reading” junction temperature during the converter operation. Finally, a SiC-based half-bridge inverter is constructed with an intelligent gate drive consisting of the gate impedance regulation circuit and online turn-off delay time monitoring unit. Experimental results demonstrate the feasibility and accuracy of the proposed approach.

As wide-bandgap (WBG) devices and applications move from niche to mainstream, a new generation of engineers trained in this area is critical to continue the development of the field. This paper introduces a new hands-on course in characterization of WBG devices, which is an emerging and fundamental topic in WBG-based techniques. First, the lecture-simulation-experiment format based course structure and design considerations, such as safety, are presented. Then, the necessary facilities to support this hands-on course are summarized, including classroom preparation, software tools, and laboratory equipment. Afterward, the detailed course implementation flow is presented to illustrate the approach of close interaction among lecture, simulation, and experiment to maximize students' learning outcomes. Finally, grading for students and course evaluation by students are discussed, highlighting the findings and potential improvements. Detailed course materials are provided via potenntial.eecs.utk.edu/WBGLab for educational use.

Newly emerged gallium nitride (GaN) devices feature ultrafast switching speed and low on-state resistance that potentially provide significant improvements for power converters. This paper investigates the benefits of GaN devices in an LLC resonant converter and quantitatively evaluates GaN devices' capabilities to improve converter efficiency. First, the relationship of device and converter design parameters to the device loss is established based on an analytical model of LLC resonant converter operating at the resonance. Due to the low effective output capacitance of GaN devices, the GaN-based design demonstrates about 50% device loss reduction compared with the Si-based design. Second, a new perspective on the extra transformer winding loss due to the asymmetrical primary-side and secondary-side current is proposed. The device and design parameters are tied to the winding loss based on the winding loss model in the finite element analysis (FEA) simulation. Compared with the Si-based design, the winding loss is reduced by 18% in the GaN-based design. Finally, in order to verify the GaN device benefits experimentally, 400- to 12-V, 300-W, 1-MHz GaN-based and Si-based LLC resonant converter prototypes are built and tested. One percent efficiency improvement, which is 24.8% loss reduction, is achieved in the GaN-based converter.

This paper presents an intelligent gate drive for silicon carbide (SiC) devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control gate voltages and gate loop impedances of both devices in a phase-leg configuration during different switching transients. Compared to conventional gate drives, the proposed circuit has the capability of accelerating the switching speed of the phase-leg power devices and suppressing the crosstalk to below device limits. Based on Wolfspeed 1200-V SiC MOSFETs, the test results demonstrate the effectiveness of this intelligent gate drive under varying operating conditions. More importantly, the proposed intelligent gate assist circuitry is embedded into a gate drive integrated circuit, offering a simple, compact, and reliable solution for end-users to maximize benefits of SiC devices in actual power electronics applications.

With the increased cloud computing and digital information storage, the energy requirement of data centers keeps increasing. A high-voltage point of load (HV POL) with an input series output parallel structure is proposed to convert 400 to 1 VDC within a single stage to increase the power conversion efficiency. The symmetrical controlled half-bridge current doubler is selected as the converter topology in the HV POL. A load-dependent soft-switching method has been proposed with an auxiliary circuit that includes inductor, diode, and MOSFETs so that the hard-switching issue of typical symmetrical controlled half-bridge converters is resolved. The operation principles of the proposed soft-switching half-bridge current doubler have been analyzed in detail. Then, the necessity of adjusting the timing with the loading in the proposed method is analyzed based on losses, and a controller is designed to realize the load-dependent operation. A lossless RCD current sensing method is used to sense the output inductor current value in the proposed load-dependent operation. Experimental efficiency of a hardware prototype is provided to show that the proposed method can increase the converter's efficiency in both heavy- and light-load conditions.

Dead time significantly affects the reliability, power quality, and efficiency of voltage-source converters. For silicon carbide (SiC) devices, considering the high sensitivity of turn-off time to the operating conditions (> 5× difference between light load and full load) and characteristics of inductive loads (> 2× difference between motor load and inductor), as well as large additional energy loss induced by the freewheeling diode conduction during the superfluous dead time (~15% of the switching loss), then the traditional fixed dead time setting becomes inappropriate. This paper introduces an approach to adaptively regulate the dead time considering the current operating condition and load characteristics via synthesizing online monitored turn-off switching parameters in the microcontroller with an embedded preset optimization model. Based on a buck converter built with 1200-V SiC MOSFETs, the experimental results show that the proposed method is able to ensure reliability and reduce power loss by 12% at full load and 18.2% at light load (8% of the full load in this case study).

The double pulse test (DPT) is a widely accepted method to evaluate the dynamic behavior of power devices. Considering the high switching-speed capability of wide band-gap devices, the test results are very sensitive to the alignment of voltage and current (V-I) measurements. Also, because of the shoot-through current induced by Cdv/dt (i.e., cross-talk), the switching losses of the nonoperating switch device in a phase-leg must be considered in addition to the operating device. This paper summarizes the key issues of the DPT, including components and layout design, measurement considerations, grounding effects, and data processing. Additionally, a practical method is proposed for phase-leg switching loss evaluation by calculating the difference between the input energy supplied by a dc capacitor and the output energy stored in a load inductor. Based on a phase-leg power module built with 1200-V/50-A SiC MOSFETs, the test results show that this method can accurately evaluate the switching loss of both the upper and lower switches by detecting only one switching current and voltage, and it is immune to V-I timing misalignment errors.

This paper presents a comprehensive short-circuit ruggedness evaluation and numerical investigation of up-to-date commercial silicon carbide (SiC) MOSFETs. The short-circuit capability of three types of commercial 1200-V SiC MOSFETs is tested under various conditions, with case temperatures from 25 to 200 °C and dc bus voltages from 400 to 750 V. It is found that the commercial SiC MOSFETs can withstand short-circuit current for only several microseconds with a dc bus voltage of 750 V and case temperature of 200 °C. The experimental short-circuit behaviors are compared, and analyzed through numerical thermal dynamic simulation. Specifically, an electrothermal model is built to estimate the device internal temperature distribution, considering the temperature-dependent thermal properties of SiC material. Based on the temperature information, a leakage current model is derived to calculate the main leakage current components (i.e., thermal, diffusion, and avalanche generation currents). Numerical results show that the short-circuit failure mechanisms of SiC MOSFETs can be thermal generation current induced thermal runaway or high-temperature-related gate oxide damage.

Double pulse test (DPT) is a widely accepted method to evaluate the switching characteristics of semiconductor switches, including SiC devices. However, the observed switching performance of SiC devices in a PWM inverter for induction motor drives is almost always worse than the DPT characterization, with slower switching speed, more switching losses, and more serious parasitic ringing. This paper systematically investigates the factors that limit the SiC switching performance from both the motor side and inverter side, including the load characteristics of induction motor and power cable, two more phase legs for the three-phase PWM inverter in comparison with the DPT, and the parasitic capacitive coupling effect between power devices and heat sink. Based on a three-phase PWM inverter with 1200 V SiC MOSFETs, test results show that the induction motor, especially with a relatively long power cable, will significantly impact the switching performance, leading to a switching time increase by a factor of 2, switching loss increase up to 30% in comparison with that yielded from DPT, and serious parasitic ringing with 1.5 μs duration, which is more than 50 times of the corresponding switching time. In addition, the interactions among the three phase legs cannot be ignored unless the decoupling capacitors are mounted close to each phase leg to support the dc bus voltage during switching transients. Also, the coupling capacitance due to the heat sink equivalently increases the junction capacitance of power devices; however, its influence on the switching behavior in the motor drives is small considering the relatively large capacitance of the motor load.

This paper presents a board-level integrated silicon carbide (SiC) mosfet power module for high temperature and high power density application. Specifically, a silicon-on-insulator (SOI)-based gate driver capable of operating at 200 °C ambient temperature is designed and fabricated. The sourcing and sinking current capability of the gate driver are tested under various ambient temperatures. Also, a 1200 V/100 A SiC mosfet phase-leg power module is developed utilizing high temperature packaging technologies. The static characteristics, switching performance, and short-circuit behavior of the fabricated power module are fully evaluated at different temperatures. Moreover, a buck converter prototype composed of the SOI gate driver and SiC power module is built for high temperature continuous operation. The converter is operated at different switching frequencies up to 100 kHz, with its junction temperature monitored by a thermosensitive electrical parameter and compared with thermal simulation results. The experimental results from the continuous operation demonstrate the high temperature capability of the power module at a junction temperature greater than 225 °C.

This paper presents the paralleling operation of three-phase current-source rectifiers (CSRs) as the front-end power conversion stage of data center power supply systems based on 400-Vdc power delivery architecture, which has been proven to have higher efficiency than traditional ac architectures. A control algorithm of paralleled three-phase CSRs is introduced to achieve balanced outputs and individual rectifier module hot swap, which are required by power supply systems. By using silicon carbide (SiC) power semiconductors, SiC MOSFETs, and Schottky diodes, the power losses of the front-end stage are reduced, and the power supply system efficiency can be further increased. The prototype of a 19-kW front-end rectifier to convert 480 Vac,rms to 400 Vdc, based on three paralleled three-phase CSRs, is developed. Each CSR is an all-SiC converter and designed for high efficiency, and the front-end stage full-load efficiency is greater than 98% from experimental tests. The balanced outputs and individual converter hot swap are realized in the hardware prototype too.

In a phase-leg configuration, the high-switching-speed performance of silicon carbide (SiC) devices is limited by the interaction between the upper and lower devices during the switching transient (crosstalk), leading to additional switching losses and overstress of the power devices. To utilize the full potential of fast SiC devices, this paper proposes two gate assist circuits to actively suppress crosstalk on the basis of the intrinsic properties of SiC power devices. One gate assist circuit employs an auxiliary transistor in series with a capacitor to mitigate crosstalk by gate loop impedance reduction. The other gate assist circuit consists of two auxiliary transistors with a diode to actively control the gate voltage for crosstalk elimination. Based on CREE CMF20120D SiC MOSFETs, the experimental results show that both active gate drivers are effective to suppress crosstalk, enabling turn-on switching losses reduction by up to 17%, and negative spurious gate voltage minimization without the penalty of decreasing the switching speed. Furthermore, both gate assist circuits, even without a negative isolated power supply, are more effective in improving the switching behavior of SiC devices in comparison to the conventional gate driver with a -2 V turn-off gate voltage. Accordingly, the proposed active gate assist circuits are simple, efficient, and cost-effective solutions for crosstalk suppression.

This paper presents an active gate driver (AGD) for IGBT modules to improve their overall performance under normal condition as well as fault condition. Specifically, during normal switching transients, a di/dt feedback controlled current source and current sink is introduced together with a push-pull buffer for dynamic gate current control. Compared to a conventional gate drive strategy, the proposed one has the capability of reducing the switching loss, delay time, and Miller plateau duration during turn-on and turn-off transient without sacrificing current and voltage stress. Under overcurrent condition, it provides a fast protection function for IGBT modules based on the evaluation of fault current level through the di/dt feedback signal. Moreover, the AGD features flexible protection modes, which overcomes the interruption of converter operation in the event of momentary short circuits. A step-down converter is built to evaluate the performance of the proposed driving schemes under various conditions, considering variation of turn-on/off gate resistance, current levels, and short-circuit fault types. Experimental results and detailed analysis are presented to verify the feasibility of the proposed approach.

Overcurrent protection of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) remains a challenge due to lack of practical knowledge. This paper presents three overcurrent protection methods to improve the reliability and overall cost of SiC MOSFET-based converters. First, a solid-state circuit breaker (SSCB) composed primarily by a Si IGBT and a commercial gate driver IC is connected in series with the dc bus to detect and clear overcurrent faults. Second, the desaturation technique using a sensing diode to detect the drain-source voltage under overcurrent faults is implemented as well. Third, a novel active overcurrent protection scheme through dynamic evaluation of fault current level is proposed. The design considerations and potential issues of the protection methods are described and analyzed in detail. A phase-leg configuration-based step-down converter is built to evaluate the performance of the protection schemes under various conditions, considering variation of fault type, decoupling capacitance, protection circuit parameters, etc. Finally, a comparison is made in terms of fault response time, temperature-dependent characteristics, and applications to help designers select a proper protection method.

The radiation robustness of a newly designed Wilkinson analog-to-digital converter (ADC) is being investigated. The ADC is a front-end design block within a cold capable, analog sense, application-specific integrated circuit (ASIC) manufactured using the IBM 0.5 μm silicon germanium (SiGe) BiCMOS 5HP process. The ASIC is part of a next-generation, cold capable, distributed motor controller architecture, which is a candidate for the next generation of Mars rovers. Its main function is to interface with various sensor types to monitor motor health (i.e., temperature, mechanical stress, pressure). While relatively well-hardened against total ionizing dose and destructive single-event latchup, the ADC showed some SEU (SET) sensitivity that is heavily dependent on its input channel configuration. For this study, we used a combination of experiments (pulsed-laser) and Cadence mixed-mode SEE simulations to explain the heavy ion irradiation results. We concluded that ADC input impedance configuration should be carefully controlled in the design of radiation-hardened systems for space.

The low power losses of silicon carbide (SiC) devices provide new opportunities to implement an ultra high-efficiency front-end rectifier for data center power supplies based on a 400-Vdc power distribution architecture, which requires high conversion efficiency in each power conversion stage. This paper presents a 7.5-kW high-efficiency three-phase buck rectifier with 480-Vac,rms input line-to-line voltage and 400-Vdc output voltage using SiC MOSFETs and Schottky diodes. To estimate power devices' losses, which are the dominant portion of total loss, the method of device evaluation and loss calculation is proposed based on a current source topology. This method simulates the current commutation process and estimates devices' losses during switching transients considering devices with and without switching actions in buck rectifier operation. Moreover, the power losses of buck rectifiers based on different combinations of 1200-V power devices are compared. The investigation and comparison demonstrate the benefits of each combination, and the lowest total loss in the all-SiC rectifier is clearly shown. A 7.5-kW prototype of the all-SiC three-phase buck rectifier using liquid cooling is fabricated and tested, with filter design and switching frequency chosen based on loss minimization. A full-load efficiency value greater than 98.5% is achieved.

Many design techniques have been incorporated into modern CMOS design practices to improve radiation tolerance of integrated circuits. Annular-gate NMOS structures have been proven to be significantly more radiation tolerant than the standard, straight-gate variety. Many circuits can be designed using the annular-gate NMOS and the inherently radiation tolerant PMOS. Bandgap reference circuits, however, typically require p-n junction diodes. These p-n junction diodes are the dominating factor in radiation degradation in bandgap reference circuits. This paper proposes a different approach to bandgap reference design to alleviate the radiation susceptibility presented by the p-n junction diodes.

High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 °C. This new gate driver prototype has been designed and implemented in a 0.8 μm, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 °C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature (≥220 °C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 μW for operating temperature up to 200 °C.

A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a 12-bit multi-channel Wilkinson (single-slope integrating) Analog-to-Digital converter (ADC). This PWLL was designed and fabricated in a 0.5- μm Silicon Germanium (SiGe) BiCMOS process. Simulation and silicon measurement data are shown that demonstrate a large improvement in the accuracy of the PVT-compensated ADC over the uncompensated ADC.

We have described the modeling, circuit design, system integration, and measurement of a Remote Sensor Interface (Figure 20) that took place over a span of 5 years and 8 fabrication cycles. It was conceived as part of the Multi-Chip Module (MCM) shown in Figure 21, which also includes a digital control chip for clocking, programming, and read-out. Further work beyond the scope of this was performed to validate the RSI for the extreme environmental conditions of a lunar mission, and individual blocks are presently.

We have presented the architecture, simulation, packaging, and over-temperature and radiation testing of a complex, 16-channel, extreme environment capable, SiGe Remote Electronics Unit containing the Remote Sensor Interface ASIC that can serve a wide variety of space-relevant needs as designed. These include future missions to the Moon and Mars, with the additional potential to operate in other hostile environments, including lunar craters and around the Jovian moon, Europa. We have expanded on the previous introduction of the RSI to show the validity of the chip design and performance over an almost 250 K temperature range, down to 100 K, under 100 krad TID radiation exposure, with SEL immunity and operability in a high-flux SET environment.

This paper describes a highly accurate dose control circuit (DCC) for the emission of a desired number of electrons from vertically aligned carbon nanofibers (VACNFs) in a massively parallel maskless e-beam lithography system. The parasitic components within the VACNF device cause a premature termination of the electron emission, resulting in underexposure of the photoresist. In this paper, we compensate for the effects of the parasitic components and noise while reducing the area of the chip and achieving a precise count of emitted electrons from the VACNFs to obtain the optimum dose for the e-beam lithography.

This book will take you through a historical voyage to the modern wonders of electronics and nanotechnology. It will provide you with a unique perspective that is both technically and historically balanced, without the prerequisite of an electrical engineering degree.

Silicon thinned to 50 mum and less is flexible allowing the fabrication of flexible and conformable electronics. Two techniques have been developed to achieve this goal using thinned die: die flip chip bonded onto flexible substrates [polyimide and liquid crystal polymer (LCP)] and die flip chip laminated onto LCP films. A key to achieving each of these techniques is the thinning of die to a thickness of 50 mum or thinner. Conventional grinding and polishing can be used to thin to 50 mum. At 50 mum, the active die becomes flexible and must be handled by temporarily bonding it to a holder die for assembly. Both reflow solder and thermocompression assembly methods are used. In the case of solder assembly, underfill is used to reinforce the solder joints. With thermocompression bonding of the die to an LCP substrate, the LCP adheres to the die surface, eliminating the need for underfill.

In the silicon-on-insulator four-gate transistors (G4-FETs), the conducting channel can be surrounded by depletion regions induced by independent vertical metal-oxide-semiconductor gates and lateral JFET gates. This unique conduction mechanism named depletion-all-around (DAA) enables majority carriers to flow in the volume of the silicon film far from the silicon/oxide interfaces. Especially when the interfaces are driven to inversion, the control of the lateral JFET gates on the conduction is maximized, while the sensitivity of the volume channel to the oxide and interface defects is minimized. This leads to excellent analog performance, low noise, and reduced sensitivity to ionizing radiation. The G4-FET properties in DAA mode are presented from multiple perspectives: experimental results, 3-D device simulations, and analytical modeling

Radiation-induced dopant passivation is evidenced for the first time in partially-depleted SOI n-channel MOSFETs. Isochronal annealing experiments following 10 Mrad(SiO2) irradiation demonstrate that the neutralization of boron atoms in the NMOSFET body is most pronounced in the 125degC-150degC temperature range. This results in an abrupt decrease of the threshold voltage and the subthreshold swing, due to the transition of the body from partial to full depletion. The SOI four-gate transistor, inherently present in the partially-depleted MOSFET structure, is demonstrated to be a very efficient tool for monitoring dopant neutralization through irradiation and annealing. Radiation-induced dopant passivation has important consequences regarding the reliability of short-channel partially-depleted NMOSFETs.

A low-power CMOS bioluminescent bioreporter integrated circuit (BBIC) is designed and fabricated for use in electronic/biological chemical sensing. The bioreporters are placed on a CMOS integrated circuit (IC) that detects bioluminescence, performs signal processing and produces a digital output pulse with a frequency that is proportional to the concentration of the target substance. The digital output pulse that contains the sensor information can then be transmitted to a remote location either wirelessly or via a data cable. The basic building blocks of the integrated circuit are the microluminometer and the transmitter. The microluminometer includes an integrated photodetector and a signal processor and is housed in a rugged inexpensive package that can be used in many remote applications in hazardous environmental monitoring. The total power consumption of the entire signal processing circuitry including the photodiodes is 3 mW from a 3.3-V power supply. This is lowered by a factor of 3 when compared to previous versions of the BBIC. In addition, it also integrates all features of detection, processing and data transmission into one small element. The bioreporter typically contains the luxCDABE reporter genes. The close proximity of the bioreporter and the sensing element eliminates the need for complex instrumentation to channel light from the bioreporters to the microluminometer. This paper presents an integrated CMOS microluminometer realized in 0.35-mum CMOS process and optimized for the detection of low-level bioluminescence as part of the BBIC. A flow-through test system was designed to expose the BBIC system composed of the microluminometer and the bioreporter Pseudomonas fluorescens 5RL to salicylate for determination of analytical benchmark data. The results obtained from the experiment are currently being used to study enclosures and micro-environment configurations for field-deployable BBICs for environmental monitoring

Circuit simulations are used to determine the response of a pipelined analog-to-digital converter (ADC) to radiation-induced single-event transients. The ADC uses a cascade of 9 stages which each resolve 1.5 bits. Digital error correction is used to reassemble the bits and to correct for errors in the comparators and sub-DAC. A Monte-Carlo methodology is used to simulate the single-event vulnerability of the circuit. Circuit simulations are performed using the Spectre circuit simulator. Sensitive cross-sections were derived from an analysis of the simulation results. Sensitive areas were identified and hardening techniques were applied to the circuit. These techniques may be applicable to other mixed-signal and switched-capacitor circuits. A significant reduction in the sensitive cross-section was obtained by application of these hardening techniques

This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 /spl times/ 400-/spl mu/m pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1/spl deg/C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic.

Europa lies in Jupiter’s colossal radiation belt, producing radiation surface conditions that are so severe (5 Mrad[Si]) that most modern electronics would experience degradation in a matter of days. This challenge, coupled with the sub-100 K surface temperatures, leads to a very hostile environment for a viable electronic infrastructure. To help enable a future mission for landing on Europa’s surface, there must be efficient terrestrial testing facilities in place to model the effects of the environment on the requisite microelectronics.The Jet Propulsion Laboratory’s Dynamitron facility, an electrostatic particle accelerator, provides unique TID testing capabilities with high flux, high energy electrons at both room (300 K) and at cryogenic (100 K) temperatures. We have found that radiation test methods for microelectronics require additional considerations in the high flux, high energy, cryogenic environment within the chamber.This paper outlines the best practices required for success, and demonstrates the efficacy of these methods using silicon-germanium (SiGe) microelectronic devices and circuits, a leading candidate technology for Europa surface missions.

Exploration of Ocean Worlds (e.g., Europa) is especially challenging from an electronics perspective, given the combination of extreme radiation (5 Mrad TID) and low temperatures $(-180^{\circ}\mathrm{C})$ encountered on the surface. Legacy approaches (e.g., Mars rover) require placing electronics in protective “warm boxes” to ensure their robust operation, but this is not viable for Ocean Worlds given the constraints on battery life. From a mission-science perspective, it is highly desirable to utilize an electronics technology platform that possesses inherent “environmental invariance” (operates robustly in whatever environment it finds itself). The envisioned electronics platform should be commercially available, highly integrated, low-cost, support digital/analog/RF circuits, and bring compelling SWaP-C advantages. We are developing and demonstrating that advanced-node silicon-germanium (SiGe) electronics can support this vision. The SiGe NASA COLDTech team is working to demonstrate the efficacy of using SiGe technology to support NASA needs in this context (to TRL 5/6), and work to develop a design eco-system and component library for NASA utilization. Initial results are very encouraging.

This work demonstrates the first application of the super class-AB recycling folded cascode in an op-amp. Usage of adaptive biasing and local common mode feedback enhance gain-bandwidth, slew rate, and power efficiency. Class-AB control is achieved using RC lag compensation. Simulation results from layout extraction highlight the design's strengths for applications requiring high bandwidth and low power while driving capacitive loads. The op-amp is implemented in a 180nm CMOS process, occupying an area of 0.010mm² and drawing 23μA of static current. Under a capacitive load of 25pF, the design achieves an open-loop DC gain of 80.5dB, gain-bandwidth of 10.7MHz, slew rate of 202V/μs, and phase margin of 60° in the unity-gain configuration.

Low-power analog filter banks provide frequency analysis with minimal power and space requirements, making them viable solutions for integrated remote audio- and vibration-sensing applications. Compared with their digital counterparts, analog filter banks are better suited to achieve the lower power consumption necessary for IoT applications. In this work, the design and implementation of a sub-threshold complementary metal-oxide semiconductor (CMOS) integrated low-power tunable bandpass filter channel for signal spectrum analysis and signal discrimination is presented, including performance improvements to stability and precise matching between filter stages. The 8^th-order filter channel achieves an effective Q-factor of 4.5 and dynamic range of 60 dB, has an operational frequency range from 2 kHz to 100 kHz, and consumes 256 μW nominally at the highest center frequency. An integrated analog Gm-C filter topology is selected for this application. Functionally, the high-Q bandpass filter transfer function is implemented via four cascaded 2^nd-order filter cells and is fabricated in 130-nm 1.2-V CMOS technology, making it suitable for use in monolithic integrated spectral analysis (MISA) applications.

The purpose of the study presented in this paper is to extend the test period of a selected set of electronics parts at cryogenic condition to dwell period of about 24 hours to demonstrate extreme cold operational capability of these components. The parts tested are tantalum polymer, BX and P90 type ceramic capacitors, thick film resistors, analog multiplexers, a digital inverter, and a D-flip-flop. These parts were tested to assist identifying candidate components that can be used for development of a cold capable telemetry board. There are several past investigations that have shown that COTS (commercial-off-the-shelf) capacitors and resistors tested at cryogenic temperatures and frequencies up to 10MHz did not exhibit significant changes in capacitance and resistance values. Also, there are several test results for active parts. These past tests collected measurements during a temperature sweep from room temperature down to cryogenic temperature with very short dwell time at cryogenic temperature, and back to room temperature. This study extends the operational dwell time to at least 24 hours and returning to room temperature operation without significant degradation in performance for most parts. Thus, demonstrating the potential for actual operation in these extreme cold temperatures and a method for identifying the cold operability.

To further enable exploration of Cold Worlds, this paper seeks to develop a temperature-predictive universal model for CMOS Nyquist-rate commercial-off-the-shelf (COTS) analog to digital converters (ADCs). The proposed modeling methodology is designed to enable rapid model construction from readily available data sheet information without incurring extensive and costly overhead associated with data collection in order to produce a behavioral model with predictive cold temperature performance estimation. Thorough temperature characterization of two different popular architecture COTS CMOS ADCs from different manufacturers is used to add predictive temperature performance capability to this universal behavioral model. Parametric trends in the ADC transfer curve, which have been measured and established across temperature, are applied to the initial parameters of an ADC's datasheet transfer curve, allowing the initial transfer curve to evolve across temperature in an analogous fashion to what has been experimentally observed. From this simulated transfer curve, the expected output and performance of the device may be computed. The paper concludes with a comparison of part to part variations for several devices along with simulated results. It may be possible to predict a rough estimate of a part's performance beyond datasheet temperature ranges.

An analytical model for the device drain-source turn-on overvoltage in three-level active neutral point clamped (3L-ANPC) converters is established in this paper. Considering the two commutation loops in the converter, the relationship between the turn-on overvoltage and the loop inductances is evaluated. The line switching frequency device usually exhibits higher overvoltage, while the high switching frequency device is not strongly influenced by the multiple loops. A 500 kVA 3L-ANPC converter using SiC MOSFETs is tested, and the model is verified with the experimental results.

In paralleled voltage source inverters (VSI), circulating current has both high frequency and low frequency components, and its spectrum highly depends on the modulation scheme. Previous research has mostly focused on the circulating current suppression for paralleled two-level VSIs. Little literature exists on similar analysis for paralleled three-level VSIs using space vector modulation. A detailed circulating current spectrum on full frequency range has not been well developed. This paper presents an improved analytical model for three-level space vector modulation (SVM), considering the impacts of regularly sampled reference and dead time. Then, circulating harmonic currents are determined across the full frequency range for various interleaving angles of two three-level ANPC inverters. The calculated harmonics are also verified by experimental results.

With conventional voltage source gate drives (VSG), the switching speed of SiC MOSFETs is difficult to increase due to large internal gate resistance, high Miller voltage, and limited gate voltage rating. This paper analyzes the requirement of current source gate drive (CSG) for SiC MOSFETs and proposes a CSG that can improve the switching speed and reduce switching loss. With the introduction of bi-directional switches, the influence of the large internal gate resistance of the SiC MOSFET can be mitigated, and sufficient gate current can be guaranteed throughout the switching transient. Therefore, the switching time and loss is reduced. The CSG can be controlled to be a VSG during steady state so the current of the gate drive is discontinuous and the stored energy of the inductor can be returned to the power supply to reduce gate drive loss. Double pulse tests are conducted for a SiC MOSFET with both conventional VSG and the proposed CSG. Testing results show that the switching loss of the proposed CSG is less than one third of the conventional VSG at full load condition.

High power inverters will be a key enabler for future aircraft based on hybrid electric or turbo-electric propulsion as envisioned by NASA and Boeing. Cooling a power electronics converter to low temperature, e.g. using cryogenic cooling, can significantly improve the efficiency and power density of a power conversion system. This paper presents the design of a MW cryogenically-cooled power inverter for electric aircraft applications. The power semiconductor and magnetic component characterization, inverter topology and power stage design, modulation and control, EMI noise reduction and filters design, and cooling system design are illustrated. A MW-level inverter prototype has been assembled and tested. The experimental results verify the functionality of the inverter.

Paralleling power electronics inverters is an effective way to increase dc-ac system power level. Accurately synchronized switching action and independent closed-loop regulator are necessary to prevent circulating current in paralleled inverters. There are many challenges for the controller design, when the number of paralleled inverters is large, and control period gets short for high switching frequency applications. This paper presents a single controller design based on DSP + FPGA that is suitable for paralleling multiple inverters. A simple synchronization scheme between DSP and FPGA based on universal parallel port (UPP) is proposed to eliminate the synchronization delay among inverters, and independent control of each converter can also be implemented. The controller is built for a system consisting of 4 paralleled three-level, three-phase high frequency ANPC inverters using space vector modulation, and it can be easily adopted to other topologies and modulations. Experimental results have demonstrated the effectiveness of this controller.

The adoption of SiC devices in high power applications enables higher switching speed, which requires lower circuit parasitic inductance to reduce the voltage overshoot. This paper presents the design of a busbar for a 500 kVA three-level active neutral point clamped (ANPC) converter. The layout of the busbar is discussed in detail based on the analysis of the multiple commutation loops, magnetic canceling effect, and DC-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. The results match with each other, and the inductances of small and large loop are 6.5 nH and 17.5 nH respectively, which is significantly lower than the busbars of NPC type converters in other references.

The four-leg topology has been applied to two-level inverters for common-mode (CM) noise elimination. To achieve zero common-mode voltage (CMV), the zero vector typically used in the two-level inverter is not allowed. As a result, the reference cannot be synthesized by nearest three vectors, which introduces a penalty in dc voltage utilization and current THD. This paper applies the fourth-leg to three-level neutral point clamped (NPC) inverter fed motor drives. Unlike the case in the two-level inverter, the reference can be synthesized by the nearest three vectors while zero CMV can be achieved at the same time in a three-level inverter with the fourth-leg. The topology and modulation are presented. The fourth-leg filter structures are investigated, and a fourth-leg filter structure which decouples the fourth-leg from the main circuit power level is proposed for high power applications. The experiment results on a three-level NPC inverter show that with the fourth-leg and presented modulation applied, the CM noise has been significantly reduced, and around 25 dB attenuation can be observed at the first noise peak in the electromagnetic interference (EMI) frequency range.

This paper presents a comprehensive analytical analysis of the ac and dc side harmonics of the three-level active neutral point clamped (ANPC) inverter with space vector modulation (SVM) scheme. An analytical model to calculate the harmonics of a three-level converter with SVM is developed. The ac side output voltage harmonics and dc side current harmonics characteristics are calculated and analyzed. With the developed models, the impact of interleaving on both sides harmonics are studied which considers the modulation index, interleaving angle, and power factor. The analysis provides guideline for interleaving angle optimization to reduce the ac side power filter and dc side dc-link capacitor. The relationship between electromagnetic interference (EMI) filter corner frequency and switching frequency is also analytically derived which provides guideline for switching frequency and EMI filter design optimization. Two paralleled three-level ANPC inverters are constructed and experimental results are presented to verify the analytical analysis.

With the development of wide band-gap (WBG) technology, the switching speed of power semiconductor devices increases, which makes circuits more sensitive to parasitics. For three-level active neutral point clamped (3L-ANPC) converters, the over-voltage caused by additional non-active switch loop can be an issue. This paper analyzes the multiple commutation loops in 3L-ANPC converter and summarizes the impact factors of the device over-voltage. The nonlinearity of the output capacitance of the device can significantly influence the over-voltage. A simple control without introducing additional hardware circuit or complex software algorithm is proposed to attenuate the effect of the nonlinear output capacitance. Multi-pulse test is conducted for a 3L-ANPC converter built with silicon carbide (SiC) MOSFETs. With the proposed control, the testing results show that the peak drain-source voltage of both active and non-active switches is reduced by more than 20% compared to the conventional control.

This paper presents the coupled inductor design for interleaved three-level active neutral point clamped (ANPC) inverter considering electromagnetic interference (EMI) noise reduction. Compared to two-level case, the scenarios involved in the three-level space vector modulation (SVM) are more complicated when analyzing the volt-seconds of the coupled inductor for paralleled three-level inverter. At system level, the purpose of converter interleaving is to reduce EMI noise and ripple current in most applications, and coupled inductor design should consider the needs of EMI noise reduction and EMI filter design. These issues are discussed in this paper. The relationship between circulating current and EMI noise is illustrated. EMI filter corner frequency as a function of interleaving angle is analytically derived, and optimal interleaving angle for maximum common-mode (CM) filter and differential-mode (DM) filter corner frequencies is discussed. Coupled inductor design methodology for interleaved three-level inverters with SVM is then presented. Experiments on two interleaved ANPC inverters are conducted. The results verify the coupled inductor design. With the derived optimal interleaving angle, the CM and DM EMI noise are significantly reduced.

This paper presents harmonic analysis of common-mode reduction (CMR) modulation for three-level voltage source inverters. The analytical model to calculate the harmonics of CMR modulation with arbitrary PWM sequence is developed. The impact of alternative PWM sequences of CMR modulation on harmonics is investigated. New three-state and four-state PWM sequences of CMR are proposed which spread the energy centered in the carrier frequency in the conventional CMR, and thus reduce the voltage peaks in frequency domain. Experiments are conducted on a three-level neutral point clamped inverter. Experiment results verify the developed analytical model and harmonic analysis.

In this paper, we investigate and model the effects of extreme low temperature on a commercial mixed-signal device. The measured results are used to develop a black-box temperature-sensitive model of the device under test (DUT) capable of incorporating non-ideal effects on the input signal including noise via SNR and distortion via THD. The blackbox model consists of the integral non-linearity (INL) function which expresses deviation in converter decision points from their ideal location, characterized across output code and temperature. In addition, a Simulink R model of a SAR ADC is described. Results indicate additional effects beyond those caused by INL modification may be present in the output. While prior work has examined this model approach for commercial devices, it has never been used for devices operating in extreme temperatures well outside their designed operating ranges. This aspect presented some challenges during testing that had to be overcome to continue to gather useful data.

We present the development of a graphite-based sensor interfaced with a custom potentiostat circuit for electrochemical detection. Paper-based electrodes offer significant cost advantage compared to electrodes fabricated using standard clean room microfabrication techniques. The three-electrode system used in this paper does not use inks or pastes, and can be prepared easily by writing on chromatography paper with store-bought pencils. The electrode fabrication procedure is simple and uses widely available materials making them easy and usable for fabrication and use in remote areas and underdeveloped countries. The potentiostat is implemented using discrete electronics for the control amplifier and two versions of the transimpedance amplifier are presented. The system is characterized using cyclic voltammetry and amperometry. Along with a custom potentiostat, the system eliminates the need for benchtop devices and makes a system that is usable in remote and low resource locations.

Future NASA missions such as icy moons and worlds will be subject to operating in extreme cold using mixed-signal electronic components. At present, models for mixed-signal components do not include significant temperature dependence, ADCs in particular. By developing comparatively generic models that are cold-capable, the ability to integrate mixed-signal parts into a larger system greatly increases. We have focused on Analog to Digital Converters (ADCs) because of their widespread, critical usage in avionic subsystems and lack of available cold macro models. This paper provides an overview of testing and modeling of a commercial off the shelf (COTS) ADC across cryogenic temperature for the purposes of trend identification, performance prediction and reliability scoping with possible post-correction capability. The development of this model will hopefully permit greater integration of commercial components in larger avionics systems, decreasing development time while increasing flexibility of designers when trying to meet mission objectives.

Wide bandgap (WBG) semiconductor devices and cryogenic cooling are key enablers for highly-efficient ultra-dense power electronics converters, which are critical for future more electric aircraft applications. For the development and optimization of a cryogenically-cooled converter, an understanding of power semiconductor characteristics, especially for emerging WBG devices, is critical. This paper focuses on WBG device characterization at cryogenic temperatures. First, the testing setup for cryogenic temperature characterization is introduced. Then several WBG device candidates (e.g., 1200-V SiC MOSFETs and 650-V GaN HEMTs) are characterized from room to cryogenic temperatures. The test results are presented with trends summarized and analyzed, including on-state resistance, breakdown voltage, and switching performance.

Switching transient overvoltage is inevitable in hard switching applications, and the faster switching speed of SiC MOSFETs suggests even worse overvoltage. This paper focuses on the turn-on overvoltage. To understand its nature, the switching transient is analyzed, and it shows the turn-on overvoltage is largely independent of load current condition. This phenomenon is verified by characterizing the turn-on overvoltage of a SiC MOFET and a SiC Schottky diode. Finally, a SPICE-based model is also built to understand the switching transient more accurately, and the modeling method can accurately predict the turn-on overvoltage and help select device voltage rating.

In this work, a hybrid switched-capacitor/PWM converter is analyzed and designed for battery charging in mobile electronics. Operation of the converter is reviewed to construct a complete analytical loss model based on FET extracted parameters for an integrated circuit implementation. The model is validated with experimental results and compared with other converter topologies in the same application. The loss modeling is used to optimize the physical scaling of the power transistors to minimize total losses.

Dead-time, device output capacitance, and other non-ideal characteristics cause voltage error for the midpoint PWM voltage of the semiconductor phase-leg employed in a voltage-source inverter (VSI). Voltage-second balancing is a well-known concept to mitigate this distortion and improve converter power quality. This paper proposes a unique voltage-second balancing scheme for a SiC based voltage source inverter using online condition monitoring of turn-off delay time and drain-source voltage rise/fall time. This data is sent to the micro-controller to be used in an algorithm to actively adjust the duty cycle of the input PWM gate signals to match the voltage-second of the non-ideal output voltage with an ideal output voltage-second. The monitoring system also allows for this implementation to eliminate the need for precise current sensing and allows for the implementation to be load independent. Dynamic current sensing is still a developing technology, and each load has a unique effect on the output voltage distortion. Test results for a 1 kW half-bridge inverter implementing this monitoring system and voltage-second balancing scheme show a 70% enhancement on the error against the ideal fundamental current value of the output current and a 2% THD improvement on the output current low frequency harmonics.

This work examines the application of GaN within Class D audio by providing a side-by-side comparison of enhancement-mode GaN devices with currently available silicon MOSFETs with 60 V drain-to-source voltage ratings. GaN in Class D audio will allow for lower heat radiation, smaller circuit footprints, and longer battery life as compared to Si MOSFETs with a negligible trade-off for quality of sound.

Data centers consume an ever-increasing amount of electricity because of the rapid growth of cloud computing and digital information storage. A high voltage point of load (HV POL) converter is proposed to convert the 400-VDC distribution voltage to 1-VDC within a single stage to increase the power conversion efficiency. A six-phase input series output parallel (ISOP) connected structure is implemented for the HV POL. The symmetrical controlled half bridge current doubler is selected as the converter topology in the ISOP structure. The full load efficiency is improved by 4% points compared with state of the art products. A voltage compensator has been designed in order to meet the strict dynamic voltage regulation requirement. A laboratory prototype has been built, and experimental results have been provided to verify the proposed HV POL with a single power conversion stage can meet the dynamic voltage regulation requirement for an on-board power supply with higher efficiency compared to the conventional architecture.

Although SiC MOSFETs show superior switching performance compared to Si IGBTs, it is unknown whether SiC MOSFETs have the same advantage over Si super junction (SJ) MOSFETs such as CoolMOS. This paper analyzes the switching performance in different switching cell configurations and summarizes the impact factors that influence switching loss. A double pulse test is conducted for a SiC MOSFET and a CoolMOS with the same voltage and current rating. In the FET/diode cell structure, a SiC Schottky diode is used as the upper device to eliminate the reverse recovery, and the testing results show that the SiC MOSFET has 2.4 times higher switching loss than the Si CoolMOS. This can be explained by the smaller transconductance and the higher Miller voltage of the SiC MOSFET. On the other hand, the Si CooMOS has 10 times higher switching loss than the SiC MOSFET in the FET/FET cell structure because of the significant turn-on loss caused by the poor reverse recovery of its body diode.

Due to the low availability, high cost, and limited performance of high voltage power devices in high voltage high power applications, series-connection of low voltage switches is commonly considered. Practically, because of the dynamic voltage unbalance and the resultant reliability issue, switches in series-connection are not popular, especially for fast switching field-effect transistors such as silicon (Si) super junction MOSFETs, silicon carbide (SiC) JFETs, SiC MOSFETs, and gallium nitride (GaN) HEMTs, since their switching performance is highly sensitive to gate control, circuit parasitics, and device parameters. In the end, slight mismatch can introduce severe unbalanced voltage. This paper proposes an active voltage balancing scheme, including 1) tunable gate signal timing unit between series-connected switches with <; 1 ns precision resolution by utilizing a high resolution pulse-width modulator (HRPWM) which has existed in micro-controllers; and 2) online voltage unbalance monitor unit integrated with the gate drive as the feedback. Based on the latest generation 600-V Si CoolMOS, experimental results show that the dynamic voltage can be automatically well balanced in a wide range of operating conditions, and more importantly, the proposed scheme has no penalty for high-speed switching.

Understanding the CM inductor core saturation mechanism and reducing core flux density is critical for CM inductor design optimization. Instead of a time domain method, this paper introduces frequency domain spectrum concept for CM inductor core saturation analysis and design optimization, which will provide designers a better understanding of CM inductor design. First, both core permeability and converter modulation index's opposite influence on DM flux density and CM flux density are identified. Then, CM flux density is further investigated based on the spectrum concept. Three components in the CM inductor which may cause large CM flux density and core saturation are summarized: (1) switching frequency related components, (2) impedance resonance frequency related components, and (3) modulation frequency related components. Each component is investigated for CM flux density reduction and filter design optimization. A connecting AC and DC side midpoint with notch filter structure is proposed to reduce modulation frequency related components. Experiment results are presented to verify the proposed concept and method.

Superconducting technologies such as motors together with the supporting cryogenic power electronic system are growing in importance in aircraft applications. It is critical to understand the influence of low temperature on filters of the power converter system in these applications. Also, it is worthwhile to investigate whether the converter system can achieve higher efficiency and high power density by utilizing the provided low temperature cooling environment. This paper conducted a comprehensive magnetic core characterization at low temperature to understand the core properties and support filter design at low temperature. The ferrite and nanocrystalline material are characterized from room temperature to cryogenic temperature in a wide range of operating frequencies. The results show that the permeability of ferrite material decreases by a factor of 7~8 and the core loss increases more than 10 times when operating at very low temperature. The permeability of nanocrystalline material decreases to 60% and the core loss increases 1.5~2.5 times when operating at very low temperature. The saturation flux density of both materials has slight increase at low temperature. Based on tested data, a case study of inductor design considering the low temperature cooling environment is presented to illustrate the influence of low temperature on inductor design.

To operate a converter at cryogenic temperatures, understanding the characteristics of power semiconductor devices is critical. This paper presents the characterization of state-of-the-art 1.2 kV SiC MOSFETs from leading manufacturers at cryogenic temperatures. The testing setup consisting of a cryogenic chamber, and a liquid nitrogen Dewar is introduced. With a curve tracer and double pulse test, comprehensive characterization of the SiC MOSFETs including both static and switching performance is conducted and evaluated. Test results indicate the on-resistance increases while the breakdown voltage remains relatively constant at cryogenic temperatures. Other characteristics like threshold voltage and switching loss vary significantly at cryogenic temperatures among devices from different manufacturers.

Zero sequence circulating current (ZSCC) exists when paralleled inverters have common dc and ac sides without isolation. Most of the prior work on the ZSCC analysis and suppression depended on paralleled two-level inverters. The scenarios involved in the three-level converters are more complicated. This paper investigates the ZSCC in paralleled three-level active neutral point clamped (ANPC) inverters. The mechanisms causing potential ZSCC jump in three-level paralleled ANPC inverters are analyzed. The ZSCC patterns of different interleaved modulation schemes for three-level converters are illustrated. Then, the active vector dividing concept is extended to three-level converters, and a modulation scheme is proposed to reduce the high frequency ZSCC in three-level converters. Experiments have been conducted on two paralleled three-level inverters. The current jump in ZSCC is observed and mitigated. The ZSCC with proposed modulation scheme is reduced to less than half of the ZSCC with conventional continuous space vector modulation (CSVM) scheme.

Unlike conventional passive or active filters, an impedance balancing circuit reduces the common-mode (CM) electromagnetic interference (EMI) noise by establishing an impedance balancing bridge. The EMI noise can be significantly reduced when the impedance bridge is designed to be well balanced. This paper investigates impedance balancing circuits in Dc-fed motor drive systems where both DC input and AC output need to meet EMI standards and thus EMI filters are needed for both sides. An impedance balancing circuit is proposed to reduce both DC and AC side CM noise. Two auxiliary branches are added to the conventional passive filters to establish an impedance bridge and reduce CM noise. The design criteria are presented, and the impact of the proposed impedance balancing circuit on both sides CM noise are investigated. It shows that the proposed impedance balancing circuit can reduce DC side and AC side CM noise based on different mechanisms. The CM noise reduction performance of the proposed method does not depend on the motor and cable models. Experiment results are presented to demonstrate the feasibility and effectiveness of the proposed method.

One of the popular converter topologies applied in high power dc-ac applications is the three-level active neutral point clamped (ANPC). Owing to relatively low switching frequency and slow switching speed of these topologies in high power applications, the commutation loop analysis in these topologies has not been fully conducted, and the over-voltage issue of non-active switches has not been thoroughly analyzed. This paper reveals an over-voltage issue on non-active switches in three level inverters due to multi-commutation loop. The detailed mode analysis during the commutation and related over-voltage issue are given. Finally, Si-based ANPC with 140 kHz switching frequency and SiC-based ANPC converters with 280 kHz switching frequency and high switching speed are tested respectively to compare and verify the over-voltage issue for non-active switches.

In order to evaluate the feasibility of newly developed GaN devices in a cryogenic-cooled converter, this paper characterizes a 650 V enhancement-mode Gallium-Nitride heterojunction field-effect transistor (GaN HFET) at cryogenic temperatures. The characterization includes two parts: static and dynamic characterization. The results show that this GaN HEMT is an excellent device candidate to be applied in cryogenic-cooled applications. For example, transconductance at cryogenic temperature is 2.5 times of one at room temperature, and accordingly, peak di/dt during turn-on transients at cryogenic temperature is around 2 times of that at room temperature. Moreover, the on-resistance of the channel at cryogenic temperature is only one-fifth of that at room temperature.

Battery charging circuits for mobile applications, such as smart phones and tablets, require both small area and low losses. In addition, to reduce the charging time, high current is needed through the converter. In order to reduce conduction losses, low on-resistance of the switches is necessary. However, specific resistance (resistance per unit area) is a strong function of the maximum voltage blocking capability of the transistors. To maintain high efficiency and ensure device reliability, the designed breakdown voltage of the transistors needs to include some margin to account for ringing on the switching node. Bond wires add inductance to the power loop increasing the overshoot voltage. In this work the design, implementation and testing of a 40 W CMOS integrated buck converter with an on chip decoupling capacitor are presented. The design was optimized for a 5V to 4V application with a maximum of 2 W on-chip losses at 10 A with an operating frequency of 1 MHz.

This paper introduces a dead-time optimization technique for a 2-level voltage source converter (VSC) using turn-off transition monitoring. Dead-time in a VSC impacts power quality, reliability, and efficiency. Silicon carbide (SiC) based VSCs are more sensitive to dead-time from increased reverse conduction losses and turn-off time variability with operating conditions and load characteristics. An online condition monitoring system for SiC devices has been developed using gate drive assist circuits and a micro-controller. It can be leveraged to monitor turn-off time and indicate the optimal dead-time in each switching cycle of any converter operation. It can also be used to specify load current polarity, which is needed for dead-time optimization in an inverter. This is an important distinction from other inverter dead-time elimination/optimization schemes as current around the zero current crossing is hard to accurately detect. A 1kW half-bridge inverter was assembled to test the turn-off time monitoring and dead-time optimization scheme. Results show 91% reduction in reverse conduction power losses in the SiC devices compared to a set dead-time of 500ns switching at 50 kHz.

This work presents an analytical model for integrated DC-DC converters at high currents. A loss model is constructed using parameters extracted from simulation or are available in the process manual and are scaled with the size of the device. The loss model is used to compare power converter implementations for varying on-chip size and power loss goals. Buck, 3-Level Buck, and Switched-Capacitor topologies are compared using this analytical model and then implemented in a commercial CMOS process. Validation of the constructed loss model is done through hardware measurements.

While fast switching brings many benefits, it also presents unwanted ringing during switching transient. In this paper, an increasing magnitude ringing phenomenon is observed during the MOSFET turn-off transient. The unusual phenomenon is replicated in simulation and it is found the MOSFET channel is turned on again after it is turned off. The major cause to this unexpected turn on is found to be common source inductance and a moderate 3 nH one in simulation replicates the severe self-turn-on ringing observed in experiment. This paper reveals the detrimental effect of common source inductance in fast switching. Therefore, Kelvin source connection in circuit and package design is strongly recommended.

Cooling a converter to low temperatures, e.g. using cryogenic cooling, can significantly improve the efficiency and density of a power conversion system. For the development and optimization of a cryogenically-cooled converter, an understanding of power semiconductor characteristics is critical. This paper focuses on the characterization of high-voltage, high-speed switching, power semiconductors at cryogenic temperature. First, the testing setup for cryogenic temperature characterization is introduced. Three testing setups are established for cryogenic switch characterization, including: 1) on-state resistance and forward voltage drop of the body diode, 2) leakage current and breakdown voltage, and 3) switching characteristics. For each testing set up, the corresponding testing configurations, hardware setups, and practical considerations are summarized. Additionally, the test results at cryogenic temperature are illustrated and analyzed for 650-V Si CoolMOS. It is then demonstrated that when the cryogenic temperature test results are compared to that of room temperature, the device performance varies significantly; for example: on-state resistance reduces by 63%, breakdown voltage drops by 31%, switching time decreases and switching energy loss decreases by 26%. Furthermore, the peak dv/dt during transient switching at cryogenic temperature exceeds 100 V/ns which is comparable to the emerging wide bandgap Gallium Nitride devices.

The properties of silicon carbide (SiC) integrated circuit (IC) processes are discussed and nonlinear-carrier control is proposed as a controller topology that can work within the design challenges presented by SiC. A boost converter with NLC controller is demonstrated using circuit blocks built with SiC IC models.

Junction temperature is a critical indicator for health condition monitoring of power devices. Concerning the reliability of emerging silicon carbide (SiC) power semiconductors due to immaturity of new material and packaging, junction temperature measurement becomes more significant and challenging, since SiC devices have low on-state resistance, fast switching speed, and high susceptibility to noise and parasitics in circuit implementations. This paper aims at developing a practical and cost-effective approach for online junction temperature monitoring of SiC devices using turn-off delay time as the thermo-sensitive electrical parameter (TSEP). The sensitivity is analyzed for fast switching SiC devices. A gate impedance regulation assist circuit is designed to improve the sensitivity by a factor of 60 and approach hundreds of ps/°C in the case study with little penalty of the power conversion performance. Also, an online monitoring system based on three gate assist circuits is developed to monitor the turn-off delay time in real time with the resolution within hundreds of ps. In the end, the micro-controller is capable of “reading” junction temperature during the converter operation with less than 0.5 °C measurement error. Two testing platforms for calibration and online junction temperature monitoring are constructed, and experimental results demonstrate the feasibility and accuracy of the proposed approach. Furthermore, the proposed gate assist circuits for sensitivity improvement and high resolution turn-off delay time measurement are transistor based and suitable for chip level integration.

High speed switching of WBG devices causes their switching behavior to be highly susceptible to the parasitics in the circuit, including inductive loads. An inductive load consisting of a motor and power cable significantly worsens the switching speed and losses of SiC MOSFETs in a PWM inverter. This paper focuses on the motor plus power cable based inductive load, and aims at mitigating its negative influence during the switching transient. An auxiliary filter is designed and inserted between the converter and inductive load so that the parasitics of the load will not be “seen” from the converter side during the switching transient. Test results with Cree 1200-V/20-A SiC MOSFETs show that the proposed auxiliary inductor enables the switching performance with a practical inductive load (e.g., motor plus cable based inductive load) to exhibit behavior close to that when the optimally-designed double pulse test load inductor is employed.

In this paper, a single stage system which converts 400 V to 1 V within one stage and performs as the high voltage point of load (HV POL) converter for data centers is proposed. A load dependent soft switching method has been proposed for half bridge current doubler with simple auxiliary circuit. The operation principles of the soft switching converter have been analyzed in detail. A lossless RCD current sensing method is used to sense the output current value to reduce the auxiliary circuit loss and turn off loss of secondary side devices as load reduces to achieve higher efficiency. Experimental efficiency has been tested to prove the proposed method can increase the converter's efficiency in both heavy and light load condition. A prototype of the half bridge current doubler circuit has been built to verify the theory.

Many intelligent gate drivers being designed for new state-of-the-art WBG devices typically only focus on protection and driving capabilities of the devices. This paper introduces an intelligent gate driver that incorporates online condition monitoring of the WBG devices. For this specific case study, three timing conditions (turn-off delay time, turn-off time, and voltage commutation time) of a silicon carbide (SiC) device are online monitored. This online monitoring system is achieved through gate driver assist circuits and a micro-controller. These conditions are then utilized to develop converter-level benefits for the converter application the SiC devices are placed in. Junction temperature monitoring is realized through turn-off delay time monitoring. Dead-time optimization is achieved with turn-off time monitoring. Dead-time compensation is obtained with turn-off time and voltage commutation time monitoring. The case study converter assembled for testing purposes is a half-bridge inverter using two SiC devices in a phase-leg configuration. All timing conditions are correctly monitored within reasonable difference of the actual condition time. A calibration curve was created to give a direct relationship between turn-off delay time and junction temperature. The half-bridge inverter can operate at 600 Vdc input and successfully obtain a junction temperature measurement through monitored td_off and the calibration curve. Furthermore, the proposed online condition monitoring system is transistor based and suitable for the chip level integration, enabling this practical approach to be cost-effective for end users.

This paper presents a gate driver integrated circuit (IC) for Silicon Carbide (SiC) devices to fully utilize their high switching speed capabilities in a phase-leg configuration. Based upon the intrinsic properties prevalent in SiC devices, gate assist circuitry is integrated into a gate driver IC to control the gate voltages seen by both devices in a phase-leg during different switching transients. Compared to a traditional gate driver IC, the proposed circuit has the potential of suppressing the cross talk seen by both devices thus increasing the overall switching speed of the phase-leg. The replacement of the conventional gate driver with an IC effectively lowers the gate impedance loop by reducing the number of on-board traces and moving essential traces to inside the chip. Therefore, larger transient currents and higher slew rates can be achieved with an IC compared to nominal commercially available gate driver devices. Meanwhile, the added functionality of cross talk suppression, not normally available in other gate drive IC designs, minimizes the spurious gate voltages from cross talk to within the required operating ranges of SiC devices.

High voltage DC (400 V) power supply architecture is becoming a standard in today's data center power supply. To further convert from 400 V to 1 V, usually several power stages are connected in series. Therefore, even if the efficiency of each power stage is high; the overall system efficiency is limited because of the multiplication of each converter's efficiency. In this paper, a single power stage system which converts 400 V to 1 V directly and performs as the high voltage point of load (HV POL) is proposed. A multi-phase interleaved phase shift pulse width modulation (PWM) DC/DC converter with input series and output parallel (ISOP) connection is selected as the power stage topology. A simplified two phase connected system is discussed in this paper. Common duty cycle control technique is used to control the ISOP connected converters. Input voltage sharing and output current sharing is analyzed with different types of mismatches in the circuit. Finally, the preliminary testing results are given.

This paper investigates the Gallium Nitride (GaN) devices benefits on the LLC resonant DC-DC converter. First, the relationship between the device parameters and converter current based on an analytical loss model of LLC resonant converter has been established. After that, the loss analysis and comparison between Si-based and GaN-based converter is presented. The GaN-based design demonstrates about 40% loss reduction compared with the Si-based design. An insight on the extra winding loss due to the asymmetrical primary side and secondary side current is presented. The extra winding loss is reduced by 18% with GaN device application. The overall loss breakdown and the experimental result show the 20% overall loss reduction of the GaN-based LLC converter compared with the Si-based LLC converter.

Four factors impact high speed switching of silicon carbide (SiC) devices in voltage source converters, including limited gate driving capability, cross-talk, parasitics associated in switching loop, and parasitics of inductive load. This paper focuses on a solution to mitigate the adverse impact of the aforementioned factors. First, an intelligent gate drive is developed for gate driving capability enhancement and cross-talk suppression. Second, placement and layout design of power devices, gate drive, and power stage board are proposed to minimize parasitics for fast switching and over-voltage mitigation. Third, an auxiliary filter is designed to mitigate the negative impact of inductive load's parasitics during the switching transient. Finally, by utilizing all techniques developed above, a three-phase voltage source inverter with Cree 1200-V/20-A SiC MOSFETs is established. Test results show that the switching behavior of SiC devices in actual three-phase voltage source inverter fed motor drives can mostly repeat the switching performance tested by the optimally-designed double pulse test.

This paper presents an active gate driver for Silicon Carbide (SiC) devices to fully utilize their potentials of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control the gate voltages and gate loop impedances of both devices in a phase-leg during different switching transients. Compared to a conventional gate driver, the proposed circuit has the capability of increasing the switching speed of the phase-leg power devices, suppressing the cross-talk to below device limits. Based on CREE's 2nd generation 1200-V SiC MOSFETs, the test results demonstrate the effectiveness of this active gate driver under various operating conditions. The switching time decreases by up to 28% during turn-on and 50% during turn-off in the prototype circuit, resulting in up to 31% reduction in switching energy loss. In addition, spurious gate voltages induced by cross-talk are limited within the required range.

In this paper, the design of a high step down ratio (66:1) phase shift full bridge (PSFB) DC/DC converter used for data center power supplies in terms of primary side MOSFETs selection is covered. A detailed analysis of the converter's operation considering the impact of the output junction capacitance of primary side MOSFETs on the current RMS value has been performed. The study shows that a smaller output junction capacitance will lead to a smaller RMS current value on both primary and secondary side. For the high step down phase shift full bridge converter, transformer winding loss is the dominant loss; the reduction of current through the transformer will lead to a higher efficiency of the whole converter. This phenomenon is observed in experimental waveforms, and its impact on the converter's efficiency is also validated through experiment.

Dead-time in the voltage source converter significantly affects the reliability, power quality and losses. For SiC devices, considering the high sensitivity of turn-off time to the operating conditions (> 5× difference between light load and full load), as well as large extra energy loss induced by reverse conduction during superfluous dead-time (~ 15% of the switching loss), traditional fixed dead-time setting becomes inappropriate. This paper introduces an approach to achieve optimum dead-time for SiC based voltage source converter. First, turn-off behaviors under various operating conditions are investigated, and the relation between optimal dead-times and load currents are established. Second, a practical method for adaptive dead-time regulation is proposed, which consists of a dead-time optimization model and two gate assist circuits to sense the voltage commutation time during turn-off transient. Via synthesizing the monitored switching condition together with the preset dead-time optimization model, the micro-controller is able to online adjust the dead-time. Finally, based on a buck converter with 1200-V SiC MOSFETs, the test results show that by means of the proposed method, the power loss decreases by 12% at full load and 18.2% at light load.

A board-level integrated silicon carbide (SiC) MOSFET power module is developed in this work for high temperature and high power density applications. Specifically, a silicon-on-insulator (SOI) based gate driver is designed, fabricated and tested at different switching frequencies and temperatures. Also, utilizing high temperature packaging technologies, a 1200 V / 100 A SiC MOSFET phase-leg power module is built. The switching performance of the fabricated power module is fully evaluated at different temperatures up to 225 °C. Moreover, a buck converter prototype incorporating the SOI gate driver and SiC power module is built for high temperature continuous operation. The converter is operated within a wide range from 10 kHz to 100 kHz, with its junction temperature monitored by a thermo-sensitive electrical parameter (TSEP). The experimental results demonstrate that the integrated power module is able to operate at a junction temperature greater of 232 °C.

High reliability of semiconductor power devices is one of the key design objectives for power conversion systems. Fast switching SiC devices are susceptible to cross-talk, and these devices also have limited over-current capability. Both of these issues significantly threaten the reliable operation of SiC-based voltage source converters. This paper proposes two gate assist circuits capable of suppressing cross-talk and preventing shoot-through faults to promote the reliable use of SiC devices within a voltage source converter. Experimental results and detailed analysis are presented to verify the feasibility of the proposed approach.

Wide band gap (WBG) power devices, such as Silicon Carbide (SiC) and Gallium Nitride (GaN) devices, have been innovatively applied in the data center power converters, which are based on the high voltage DC (HVDC) power distribution architecture, to evaluate the potential efficiency improvement. For the front-end AC-DC rectifier, a buck rectifier using SiC devices was implemented. The SiC devices were tested at first to obtain the static and switching characteristics. The number of devices in parallel, the switching frequency and the input/output filters were investigated. A prototype of 7.5 kW, 3 phase 480 VAC input, 400 VDC output front-end rectifier was built and tested. The peak efficiency reaches up to 98.55%, and the full load efficiency is 98.54%. For the intermediate DC-DC bus converter, the impact of the GaN devices on the LLC resonant converter efficiency was evaluated and compared with the Si counterparts. Based on the device loss analysis and the FEA simulation on the transformer winding loss, the GaN devices exhibited the reduced device loss, and also the capabilities to reduce the transformer winding loss. A 300 W, 400 VDC input, 12 VDC output GaN device based DC-DC bus converter was built and tested by 96.3% peak efficiency and 96.1% full load efficiency.

This paper presents a board-level integrated silicon carbide (SiC) MOSFET power module for high temperature and high power density applications. Specifically, a silicon-on-insulator (SOI) based gate driver capable of operating at 200°C ambient temperature is designed and fabricated. The sourcing and sinking current capability of the gate driver are tested under various ambient temperatures. Also, a 1200 V/100 A SiC MOSFET phase-leg power module is developed utilizing high temperature packaging technologies. The static characteristics, switching performance, and short-circuit behavior of the fabricated power module are fully evaluated at different temperatures. Moreover, a buck converter prototype composed of the SOI gate driver and SiC power module is built for high temperature continuous operation. The converter is operated at different switching frequencies up to 100 kHz, with its junction temperature monitored by a thermo-sensitive electrical parameter (TSEP) and compared with thermal simulation results. The experimental results from the continuous operation demonstrate the high temperature capability of the power module at a junction temperature greater than 225°C.

Double pulse test (DPT) is a widely accepted method to evaluate the switching characteristics of semiconductor switches, including SiC devices. However, the observed switching performance of SiC devices in a PWM inverter for induction motor drives (IMD) is almost always worse than the DPT characterization, with slower switching speed, more switching losses, and more serious parasitic ringing. This paper systematically investigates the factors that limit the SiC switching performance from both the motor side and inverter side, including the load characteristics of induction motor/power cable, two more phase-legs for the three-phase PWM inverter as compared to the DPT, and the parasitic capacitive coupling effect between power devices and heat sink. Based on the three-phase PWM inverter with 1200 V SiC MOSFETs, the test results show that the induction motor, especially with a relatively long power cable, will significantly impact the switching performance, leading to switching time increase by a factor of 2, switching loss increase up to 30%, and serious parasitic ringing with 1.5 μs duration as compared to that tested by DPT. In addition, the interactions among the three phase-legs cannot be ignored unless the decoupling capacitors are mounted close to each phase-leg to support the dc bus voltage during switching transients. Also, the coupling capacitance induced by the heat sink equivalently increases the junction capacitance of power devices. However, its influence on the switching behavior in the motor drives is small considering the relatively large capacitance of the motor load.

This paper focuses on understanding the key impacting factors for switching speed of wide bandgap (WBG) devices in a voltage source converter. First, the constraints and challenges of WBG devices during fast switching transients are summarized. Special attention is given to the transient gate-source and drain-source voltages. Second, the impacts of major components in voltage source converter, including gate drivers, parasitics, inductive loads, and cooling systems, on the switching performance of power devices are systematically investigated. The critical parameters for each component are highlighted. Finally, design criteria are suggested to maximize switching speed of WBG devices.

Gallium Nitride High Electron Mobility Transistor (GaN HEMT) is an emerging wide band gap power device in recent years. Using a cascoded structure, the GaN HEMT can be combined with a low voltage MOSFET to make the combination behave as a normally-off device. This paper investigates the soft-switching behavior of cascode GaN HEMT in the phase-leg structure. The analysis reveals some internal device behaviors during the soft-switching transition, which are not found in the non-cascode device. Due to the internal feedback of the cascode structure, the channel current of the internal GaN HEMT drops to zero quickly, leading to extremely low turn-off loss. However, it has been found that there are switching energy loss dissipated in the internal GaN HEMT during the turn-on transient, although the external waveforms of the cascode GaN HEMT exhibit zero voltage switching. The fundamental reason is that ratio of the sum of MOSFET output capacitance and internal GaN HEMT input capacitance to the internal GaN HEMT output capacitance is quite low. Based on the simulation, by adding additional capacitance on the gate source terminals of internal GaN HEMT, these losses can be mitigated. Experimental tests using a commercially available GaN device are presented which show nearly 400 mW of loss at 1 MHz switching frequency in four different load current conditions.

This paper investigates the effects of ringing on the switching losses of wide band-gap (WBG) devices in a phase-leg configuration. An analytical switching loss model considering the parasitic inductance, stray resistance, devices' junction capacitances, and reverse recovery characteristics of the freewheeling diode is derived to identify the switching energy dissipation induced by damping ringing. This part of energy is found to be at most the reverse recovery energy and the energy stored in the parasitics, which is a small portion of the total switching energy. But the parasitic ringing causes interference between two devices in a phase-leg (i.e., cross talk). It is observed that during the turn-on transient of one device, the resonance among parasitics results in high overshoot voltage on the complementary device in a phase-leg. It worsens the cross talk, leading to large shoot-through current and excessive switching losses. The analysis results have been verified by double pulse test with a 1200 V SiC MOSFETs based phase-leg power module.

Double pulse tester (DPT) is a widely accepted method to evaluate the switching behavior of power devices. Considering the high switching-speed capability of wide band-gap (WBG) devices, the test results become significantly sensitive to the alignment of voltage and current (V-I) measurement. Also, because of the shoot-through current induced by Cdv/dt, during the switching transient of one device, the switching losses of its complementary device in the phase-leg is non-negligible. This paper summarizes the key issues of DPT, including layout design, measurement considerations, grounding effects and data processing. Among them, the latest probes for switching waveform measurement are compared, the methods of V-I alignment are discussed, and the impact of grounding effects induced by probes on switching waveforms are investigated. Also, for the WBG devices in a phase-leg configuration, a practical method is proposed for switching loss evaluation by calculating the difference between the input energy supplied by a dc capacitor and the output energy stored in a load inductor. Based on a phase-leg power module built with 1200 V SiC MOSFETs, the test results show that regardless of V-I timing alignment, this method can accurately indicate the switching losses of both the upper and lower switches by detecting only one switching current.

The overvoltage caused by dc-link inductor current interruption is a serious problem in the current source converters. It becomes an even more challenging issue when the fast-switching SiC MOSFETs are applied as switches in these converters. The protection is required to have nanosecond-level response time to protect the devices. Addressing this challenge, this paper proposes a novel overvoltage protection scheme constituted by a diode bridge and the high-power transient-voltage-suppression (TVS) diodes. It can detect and clamp the overvoltage within less than 50 ns to protect the device from breakdown. When the energy in the inductor is small, it can be dissipated in the TVS diodes. Otherwise, a capacitor in series with a thyristor can be added to absorb the energy. The effectiveness of the protection scheme has been verified by experiments in a 7.5 kW current source rectifier built with SiC MOSFETs.

The energy efficiency of typical data centers is less than 50% because more than half of the power is consumed during power conversion, distribution, cooling, etc. In this paper, a combination of two approaches to improve power supply efficiency is implemented and experimentally verified. One approach uses a high voltage DC architecture, designed to reduce distribution loss and remove unnecessary power conversion stages. The other approach employs wide band gap (WBG) power devices, including silicon carbide (SiC) and gallium nitride (GaN) FETs and diodes, which helps to increase converter efficiency and power density. Scaled down prototypes of all power conversion stages in the data center power supply chain are designed, built, and tested. The advantages of utilizing WBG power devices are illustrated through simulations and then verified by experiment.

In this paper, a compact planar current sensor is developed to be used in active current balancing applications for parallel-connected Silicon Carbide (SiC) MOSFETs. The designed Rogowski coil allows non-intrusive current measurement with low profile, compact size, and high bandwidth. The sensor circuit design extends both lower and higher cutoff frequency of the sensor, and allows a continuous measurement of current waveforms that contain a DC component. The simulated bandwidth of the proposed current sensor is 2.66 Hz-100 MHz. The measured switching waveforms in the experiment are comparable to a 120 MHz commercial current probe.

Current unbalance in paralleled power electronic devices can affect the performance and reliability of them. In this paper, the factors causing current unbalance in parallel connected silicon carbide (SiC) MOSFETs are analyzed, and the threshold mismatch is identified as the major factor. Then the distribution and temperature dependence of SiC MOSFETs' threshold voltage are studied experimentally. Based on the analysis and study, an active current balancing (ACB) scheme is presented. The scheme directly measures the unbalance current, and eliminates it in closed loop by varying the gate delay to each device. The turn-on and turn-off current unbalance are sensed and independently compensated to yield an optimal performance at both switching transitions. The proposed scheme provides robust compensation of current unbalance in fast-switching wide-band-gap devices while keeping circuit complexity and cost low. The performance of the proposed ACB scheme is verified by both simulation and experimental results.

Energy efficiency of typical data centers is less than 50% where more than half of the power is consumed during power conversion, distribution, cooling, etc. In this paper, a single power stage architecture that converts 400 V to 1 V directly targeting high system efficiency is proposed. A phase shift full bridge (PSFB) DC/DC converter based input series and output parallel structure (ISOP) is selected due to the high input voltage and large output current operation condition. The latest Gallium Nitride (GaN) FETs are implemented in the prototype circuit because of their low output junction capacitance and zero reverse recovery charge. The high frequency planar transformer is designed correspondingly with consideration of GaN FETs on the primary side. A prototype of the PSFB converter is designed, built, and tested. Preliminary experimental results are provided to verify the design.

In this paper, an new configurable low-side resonant gate driver circuit based on 5V CMOS process is presented. This gate driver is designed for current Gallium Nitride (GaN) power transistor working up to 10 MHz switching frequency. By updating driving signals and removing off-chip resonant inductors, this gate driver can be working as a conventional non-resonant gate driver. Under resonant gate driving mode, partial of the gate driving power can be recovered to gate driver power supply. Simulation shows up to 30% of gate driving power dissipation reduction can be achieved while driving a single device compared with conventional push-pull gate drivers. We also try to implement a resonant gate driver in a resonant converter. Simulation also shows a similar gate driver power saving is also achieved in a 48-12V LLC resonant DC-DC converter.

This paper develops a three-phase front-end power conversion stage for data center power supplies based on 400 Vdc power delivery architecture, which has been proven to have higher efficiency than traditional AC architectures. The front-end stage is based on three paralleled three-phase current source rectifiers, which have several benefits for this application. A control method is introduced for paralleled three-phase current source rectifiers to achieve balanced outputs and individual rectifier module hot-swap, which are required by power supply systems. By using SiC power semiconductors, the power conversion efficiency of the front-end stage is improved and the whole efficiency of the data center power supply system can be further increased.

This paper investigates the fast switching characteristics and high temperature performance of the emerging 600 V GaN high-electron-mobility transistor (HEMT) for high efficiency / high temperature applications. First, the inherent switching performance of the GaN HEMT is demonstrated in the double pulse test. The GaN HEMT exhibits superior switching capability, with a di/dt reaching 9.6 A/ns and dv/dt reaching 140 V/ns. Then, the limitations of the fast switching capability by the device packaging and application circuit are analyzed. The interference between the current and gate through common source inductance limits the inherent switching speed. Packaging and circuit layout with small parasitics is critical in achieving fast switching. Finally, the high temperature static and switching characteristics up to 200 °C are also tested and given. The switching performance of the device is temperature insensitive.

Silicon Carbide (SiC) power devices have inherent capability for fast switching. However, in a phase-leg configuration, high dv/dt will worsen the interference between the two devices during a switching transient (i.e., cross talk), leading to slower switching speed, excessive switching losses, and overstress of power devices. Unfortunately, due to intrinsic properties, such as low threshold voltage, low maximum allowable negative gate voltage, and large internal gate resistance, SiC power devices are easily affected by cross talk. This paper proposes a novel gate assist circuit using an auxiliary transistor in series with a capacitor to mitigate cross talk. Based on CMF20120D SiC MOSFETs, the experimental results show that the new gate assist circuit is capable of reducing the turn-on switching loss up to 19.3%, and suppress the negative spurious gate voltage within the maximum allowable negative gate voltage without the penalty of further decreasing the device switching speed. Moreover, in comparison to a conventional gate drive with -2 V turn-off gate voltage, this gate assist circuit without negative isolated power supply is more effective in improving the switching behavior of power devices in a phase-leg. The proposed gate assist circuit is a cost-effective solution for cross talk mitigation.

This paper presents a new active overcurrent protection scheme for IGBT modules based on the evaluation of fault current level by measuring the induced voltage across the stray inductance between the Kelvin emitter and power emitter of IGBT modules. Compared with the commonly used desaturation protection, it provides a fast and reliable detection of fault current without any blanking time. Once a short circuit is detected, a current limiting and clamping function is activated to dynamically suppress the transient peak current, thus reducing the considerable energetic and thermal stresses induced upon the power device. Subsequently, a soft turn-off mechanism is employed aiming to reduce surge voltages induced by stray inductance under high current falling rate. Moreover, the proposed method provides flexible protection modes, which overcome the interruption of converter operation in the event of momentary short circuits. The feasibility and effectiveness of the proposed approach have been validated by simulation results with real component models in Saber. A Double Pulse Tester (DPT) based experimental test setup further verifies the proposed protection scheme.

In a phase-leg configuration, the high switching-speed performance of silicon carbide (SiC) devices is limited by the interaction between the upper and lower devices during the switching transient (cross talk), leading to additional switching losses and overstress of the power devices. To utilize the full potential of fast SiC devices, this paper proposes a gate assist circuit using two auxiliary transistors and a diode to eliminate cross talk. Based on CMF20120D SiC MOSFETs, the experimental results show that this gate assist methodology is effective to suppress cross talk under different operating conditions, enabling turn-on switching losses reduction by up to 19.6%, and negative spurious gate voltage minimization within the maximum allowable negative gate voltage of the power devices without the penalty of reduced switching speed. Moreover, in comparison to the conventional gate driver with -2 V turn-off gate voltage, this gate assist circuit without a negative isolated power supply is more effective in enhancing the switching behavior of power devices in a phase-leg. Accordingly, the proposed gate assist circuit is a cost-effective solution for cross talk suppression.

An overlap time for two commutating switches is necessary to prevent current interruption in a three-phase buck rectifier, but it may cause input current distortion. In this paper, a modified pulse-based compensation method is proposed to compensate for the overlap time. In addition to the traditional method which places the overlap time based on the voltage polarity, this new method first minimizes the overlap time to reduce its effect and then compensates the pulse width according to the sampled voltage and current. It is verified by experiments that the proposed method has better performance than the traditional method, especially when the line-to-line voltage crosses zero. Another distortion comes from the irregular pulse distribution when two sectors change in a 12-sector space vector PWM. This paper proposes two compensation methods for that scenario as well, compensating the duty cycle and increasing switching frequency near the boundaries of two sectors. It is shown through experiments that both methods can reduce the input current distortion in the buck rectifier.

This paper addresses the issues of switching behavior of a high power insulated gate bipolar transistor (IGBT) that works in hard switching conditions. First, the voltage and current switching waveforms of IGBT modules are described for an IGBT phase-leg module with an inductive load, and the associated switching losses, reverse recovery current of free-wheeling diodes, voltage overshoot, and EMI noise are analyzed. Based on the analysis, an actively controlled gate drive circuit is proposed, which provides optimization of the fast driving for low switching losses and short switching time, and slow driving for low noise and switching stress. Compared to a conventional gate drive strategy, the proposed active gate driver (AGD) has the capability of reducing the switching losses, delay time, and Miller plateau duration effectively during both turn-on and turn-off transient. Experimental results verify the validity and effectiveness of the proposed gate driving method.

Buffer circuits are widely used in high-power inverters' gate drives to get enough driving current for power modules or power transistors in parallel. In this paper, designs of buffer circuits to boost the output current for a gate driver IC are investigated. Different buffer topologies are reviewed and their individual advantages and disadvantages analyzed. Based on the analysis, three topologies, specifically the BJT emitter follower, the two NFETs totem pole, and the CMOS buffer, are chosen for further study. Optimizations are performed on these three buffers by taking the driving capability, switching speed, circuit complexity, and cost into account. After that, a test setup is built, and the driving performance of the buffers is characterized and then compared experimentally with a commercial buffer IC with a rated current of 30 A. All three proposed buffers show better performance and lower cost, which verifies the feasibility and effectiveness of the proposed optimization methods. Double pulse test results indicate that the addition of a buffer stage makes the switching performance less sensitive to the load and can achieve significant performance improvement when large or parallel power switches are to be driven.

High-temperature integrated circuits fill a need in applications where there are obvious benefits to reduced thermal management or where circuitry is placed away from temperature extremes. Examples of these applications include aerospace, automotive, power generation, and well-logging. This work focuses on automotive applications in which the growing demand for hybrid electric vehicles (HEVs), Plug-in-hybrids (PHEVs), and Fuel-cell vehicles (FCVs) has increased the need for high-temperature electronics that can operate at the extreme ambient temperatures that exist under the hood of these vehicles, which can be in excess of 150°C. Silicon carbide (SiC) and other wide-bandgap power switches that can function at these temperature extremes are now entering the market. To take full advantage of their potential, high-temperature capable circuits that can also operate in these environments are required.

In recent years, Si power MOSFET is approaching its performance limits, and Gallium Nitride (GaN) HEMT is getting mature. This paper evaluates the 600 V cascode GaN HEMT performance, and compares it with the state-of-the-art Si CoolMOS in LLC resonant converter. First, the static characterization of 600 V cascode GaN HEMT is described in different temperatures. The switching performance is tested by a double pulse tester to provide the turn-off loss reference to the design of LLC resonant converter. Second, a 400 V-12 V/300 W/1 MHz all-GaN-based converter with the 600 V cascode GaN HEMT is compared with a Si-based converter with the 600 V Si CoolMOS. The device output capacitance is a key factor in the design and loss analysis of LLC resonant converter. The design results show that the total GaN device loss of the all-GaN-based converter can be improved by 42% compared with the total Si device loss. Finally, both 400 V-12 V/300 W/1 MHz Si-based and GaN-based LLC resonant converter prototypes are tested and compared with waveforms and efficiency curves.

Transformer loss, comprised of core loss and winding loss, is a critical part in the LLC resonant converter loss. Different winding structures lead to different winding losses and winding capacitances. High winding capacitance will impact the design of the LLC resonant converter. The reason is that high winding capacitance means high winding charge, which must be moved during the dead time to realize the device zero voltage turn-on. As a result, the dead time and magnetizing current will be changed, and the converter loss will be changed as well. This paper first discusses the transformer loss including core loss and winding loss. Then, four different winding structures are analyzed based on a selected core, which show the decrease of AC resistance and the increase of winding capacitance. After that, the winding capacitance model is discussed generally. Finally, the impact of winding capacitance on the design and performance of LLC resonant converter is studied. Two 48 V-12 V, 300 W Si-based and GaN-based LLC resonant converters are designed as platforms to evaluate the impact of winding capacitance. The results indicate that the GaN-based converter is well suited to the transformer with lowest winding loss but highest winding capacitance, since the GaN device's output capacitance is much lower than that of the Si device.

Three-phase current source rectifier (CSR) is a promising solution for power supply systems as the buck-type power factor correction converter. By converter paralleling, high power rating and system redundancy can be achieved. However, asymmetrical distribution of load current among converter modules may occur, which can increase power loss or even damage devices. This paper presents the DC-link current control scheme for paralleled current source rectifiers to balance the output currents. Using a master-slave control, the balanced output current distribution and system redundancy are implemented. By correcting zero state duration based on modulation scheme, the circulating current is suppressed without introducing additional power losses, and both positive and negative DC-link currents are balanced.

This paper develops a liquid cooled high efficiency three-phase current source rectifier (CSR) for data center power supplies based on 400 Vdc architecture, using SiC MOSFETs and Schottky diodes. The 98.54% efficiency is achieved at full load. The rectifiers are paralleled to achieve high power ratings and system redundancy. The current balance and hot-swap of paralleled CSRs are realized in simulation using master-slave control. Moreover, an improved modulation scheme through adjustment of the freewheeling state is proposed and verified to effectively suppress the circulating current.

In high power applications of silicon carbide (SiC) MOSFETs where parallelism is employed, current unbalance can occur and affect the performance and reliability of the power devices. In this paper, factors which cause current unbalance in these devices are analyzed. Among them, the threshold voltage mismatch is identified as a major factor for dynamic current unbalance. The threshold distribution of SiC MOSFETs is investigated, and its effect on current balance is studied in experiments. Based on these analyses, an active current balancing scheme is proposed. It is able to sense the unbalanced current and eliminate it by actively controlling the gate drive signal to each device. The features of fine time resolution and low complexity make this scheme attractive to a wide variety of wide-band-gap device applications. Experimental and simulation results verify the feasibility and effectiveness of the proposed scheme.

Advanced power semiconductor devices, especially wide band-gap devices, have inherent capability for fast switching. However, due to the limitation of gate driver capability and the interaction between two devices in a phase-leg during switching transient (cross talk), the switching speed is slower than expected in practical use. This paper focuses on identifying the key limiting factors for switching speed. The results provide the basis for improving gate drivers, eliminating interference, and boosting switching speed. Based on the EPC2001 Gallium Nitride transistor, both simulation and experimental results verify that the limiting factors in the gate loop include the pull-up (-down) resistance of gate driver, rise (fall) time and amplitude of gate driver output voltage; among these the rise (fall) time plays the primary role. Another important limiting factor of device switching speed is the spurious gate voltage induced by cross talk between two switches in a phase-leg. This induced gate voltage is not only determined by the switch speed, but also depends on the gate loop impedance, junction capacitance, and operating conditions of the complementary device.

The issues of turn-on performance of a high power insulated gate bipolar transistor (IGBT) that works in hard switching conditions are discussed in detail. First, the turn-on delay time, switching loss, reverse recovery current of the associated free-wheeling diode, and EMI noise are analyzed for an IGBT phase-leg module with an inductive load. Based on the analysis, a novel gate drive circuit combining the slow drive requirements to minimize noise and switching stress, and the fast drive requirements for high-speed switching and low switching energy loss is proposed. Compared to a conventional gate drive circuit, the proposed gate driving strategy is able to effectively reduce the switching loss, delay time, and total switching time during the turn-on transient while the turn-off performance remains unchanged. Simulation and experimental results verify the validity and effectiveness of the proposed gate driving method.

Silicon Power MOSFETs, with more than thirty years of development, are widely accepted and applied in power converters. Gallium Nitride (GaN) power devices are commercially available in recent years [1], but the device performance and application have not been fully developed. In this paper, GaN devices are compared with state-of-art Si devices to evaluate the device impact on soft-switching DC-DC converters, like LLC resonant converter. The analytical approach of device selection and comparison are conducted and loss related device parameters are derived. Total device losses are compared between Si and GaN based on these parameters. GaN shows less loss compared with Si, yielding approximately a 20% reduction of total device loss. Two 300 W, 500 kHz, 48 V-12 V GaN-based and Si-based converter prototypes are built and tested. Since the body diode forward voltage drop of GaN device is high, the dead time is adjusted to minimize the body diode conduction period. The peak efficiency of the GaN-based converter is 97.5%, and the full load efficiency is 96.1%, which is around 0.3% higher than the Si-based converter at full load. The test results shows that, although GaN device has lower loss, the improvement of converter efficiency is not much. The reason is that the transformer loss accounts for more than 60% of total loss. Therefore, a transformer which fits the GaN device characteristic need to be further investigated.

This paper presents the characteristics of a 1200 V, 33 A SiC MOSFET and a 1200 V, 60 A SiC schottky barrier diode (SBD). The switching characteristics of the devices are tested by a double pulse test (DPT) based on a current-source structure at voltage levels up to 680 V and current up to 20 A. In addition, based on these devices, a 7.5 kW, three-phase buck rectifier for a 400 Vdc architecture data center power supply is designed. The total loss of this rectifier is calculated full load. The results show that the SiC based buck rectifier can obtain low power loss and smaller weight and volume than a Si based rectifier.

This paper presents a 7.5 kW liquid cooled three-phase buck rectifier which will be used as the front-end rectifier in 400 Vdc architecture data center power supply systems. SiC MOSFETs and SiC Schottky barrier diodes (SBDs) are used in parallel to obtain low power semiconductor losses. Input and output filters are designed and inductor core material is compared to reduce passive component losses. A low-loss modulation scheme and 28 kHz switching frequency are selected to optimize the converter design for efficiency. A prototype of the proposed rectifier is constructed and tested, and greater than 98.5% efficiency is obtained at full load.

A novel charge-recycling scheme has been designed and implemented to demonstrate the feasibility of operating digital circuits using the charge scavenged from the leakage and dynamic load currents inherent to digital logic. The proposed scheme uses capacitors to efficiently recover the ground-bound charge and to subsequently boost the capacitor voltage to power up the source circuit. This recycling methodology has been implemented on a 12-bit Gray-code counter within a 12-bit multi-channel Wilkinson ADC. The circuit has been designed in 0.5μm BiCMOS and in 90nm CMOS processes. SPICE simulation results reveal a 46-53% average reduction in the energy consumption of the counter. The total energy savings including the control generation aggregates to an average of 26-34%.

An ultra-low voltage, self-starting, switched-capacitor based charge pump is proposed for energy harvesting applications. The integrated linear charge pump topology presented in this work has been optimized for low-voltage start-up. The control signals for the charge-transfer switches (CTS), generated using two clock phases, reduce reverse currents and thus improve the efficiency of the converter. Adiabatic switching techniques have been employed to reduce the switching losses associated with the CTS gate control. This design has been implemented in a 130-nm CMOS process. Simulation results demonstrate a low startup voltage of 125 mV with efficiency of 62 % for a static current load of 0.1 μA.

The growing demand for hybrid electric vehicles (HEVs) has increased the need for high-temperature electronics that can operate at the extreme temperatures that exist under the hood. This paper presents a high-voltage, high-temperature SOI-based gate driver for SiC FET switches. The gate driver is designed and implemented on a 0.8-micron BCD on SOI process. This gate driver chip is intended to drive SiC power FETs for DC-DC converters and traction drives in HEVs. To this end, the gate driver IC has been successfully tested up to 200°C. Successful operation of the circuit at this temperature with minimal or no heat sink, and without liquid cooling, will help to achieve higher power-to-volume as well as power-to-weight ratios for the power electronics modules in HEVs.

High speed channel (HSC) resistive sensor interface is an analog sampling channel designed for measuring the resistance variations with data rate at 5 kHz. It measures the external resistance variation and digitizes the received signal using a 12-bit analog to digital converter (ADC). The HSC includes a Wheatstone bridge with programmable configurations, a high voltage cap stack sampler, a 6th order Butterworth switching capacitor filter, and a continuous time variable gain amplifier (VGA). An 8-bit voltage mode calibration digital to analog converter (DAC) is used to calibrate the common mode voltage level. An 8-bit current mode stimulus DAC is used to provide the current source to the Wheatstone bridge through a high voltage current mirror. With radiation hardening by design (RHBD), the HSC is implemented in a 0.5 μm SiGe BiCMOS technology for applications in aerospace environment under extreme temperature, radiation, pressure and vibration.

This paper presents dose control electronics and a digital addressing method for the vertically aligned carbon nanofiber (VACNF) based massively parallel maskless e-beam lithography system. The Digital Electrostatically focused e-beam Array direct-write Lithography (DEAL) developed by our research group in Oak Ridge National Laboratory incorporates digitally addressable field emission arrays (DAFEAs) of the VACNFs which function as the lithography heads during the exposure of the resist. A logic and memory control circuit (LMC) and a dose control circuit (DCC) have been designed to write a desired pattern and control the dose of electrons, respectively. This paper summarizes our previous works on different versions of the DCCs designed and optimized in the effort of obtaining a fixed and optimum dosage with the smaller circuit area.

This work describes a novel frequency based current to digital converter, which is fully realizable on a single chip. This project affords an extremely low power converter technology that is also very space efficient. The converter is completely asynchronous which yields ultra-low power during standby operation (approximately 5 nW). The input current range is programmable, and the minimum detectable current could reach the range of picoampere or even lower. System structure, operational principle, and chip test results are given in this paper.

This paper describes the design, implementation, and characterization of a monolithic charge amplification channel for use as a piezoelectric sensor front-end in extreme environment applications. 12The design leverages a 50 GHz peak-fT SiGe BiCMOS technology platform to achieve functionality across a wide-temperature range from -180°C to 120°C. As part of a much larger remote electronics unit, the channel is specified to amplify piezoelectric transducer signals with frequencies up to 5 kHz and amplitudes as low as 200 pC. Intended for use in lunar surface systems, the application requires the capability to absorb up to 100 krad(SiO2) of total ionizing dose (consistent with a typical lunar mission cycle) and be hardened against latch-up effects that cause system failure in a heavy ion radiation environment. Preliminary characterization of the channel shows the desired integration of an AC current input, programmable gain, and effective filtering at three distinct cutoff frequencies.

A 1024-channel pixel array has been constructed utilizing the perforated diode neutron detector design currently produced at Kansas State University. In this design a single pixel consists of a pn-junction diode fabricated around a single trench 4 cm long, 30 microns wide and 100 microns deep. The trench is filled with 6LiF powder to provide conversion of neutrons to energetic charged particles which can be captured in the diode depletion region. A pitch of 100 microns between pixels has been achieved and less than 120 micron spatial resolution has been demonstrated experimentally with a 32-channel prototype in previous work. Also, the first array demonstrated 12% thermal neutron counting efficiency. The 1024-channel array was produced by tiling 16 chips side-by-side, each containing 64 pixels. Signal processing is handled by 16 PATARA chips for amplification and thresholds, developed at University of Tennessee. The entire board assembly and digital communications to PC were handled by the KSU Electronics Design Laboratory utilizing a PCI card developed at ORNL.

The High Efficiency Neutron Detector Array (HENDA) project at the Spallation Neutron Source (SNS), Oak Ridge Tennessee, has driven the need for state of the art radiation detector readout electronics. Readout electronics of this class must support multi-channel inputs while providing a high level of integration and precision. The Patara II ASIC targets this need by integrating a charge sensitive front end followed by analog and digital signal processing that supports the connectivity of 64 detectors. A monolithic biasing system and digital programmability was integrated in order to reduce the amount of required external components on the end system motherboard.

This paper presents a precision control circuit for the emission of desired number of electrons from vertically aligned carbon nanofibers (VACNFs) for the realization of a massively parallel maskless e-beam lithography system.The digitally addressable field emission arrays (DAFEAs) of the VACNFs function as the lithography heads for massively parallel e-beam exposure of resist eliminating the cost of photomasks.

This work describes the development and evaluation of advanced technologies for the integration of electronic die within membrane polymers. Specifically, investigators thinned silicon die, electrically connecting them with circuits on flexible liquid crystal polymer (LCP), using gold thermo-compression flip chip bonding, and embedding them within the material. Daisy chain LCP assemblies were thermal cycled from -135 to +85degC (Mars surface conditions for motor control electronics). The LCP assembly method was further utilized to embed an operational amplifier designed for operation within the Mars surface ambient. The embedded op-amp assembly was evaluated with respect to the influence of temperature on the operational characteristics of the device. Applications for this technology range from multifunctional, large area, flexible membrane structures to small-scale, flexible circuits that can be fit into tight spaces for flex to fit applications.

Integrated microbatteries are being currently developed to act as a ldquomicropowerrdquo source in microsatellites. They help provide localized current capacities or embedded power supplies at the chip level, for space exploration. These power cells are designed to be rechargeable. This research paper aims at presenting charging these power cells using pulsing algorithms developed at MRCI with an on chip pulse charger controller.

In recent years increasing demand for hybrid electric vehicle has generated the need for reliable and low-cost high-temperature electronics which can operate at the extreme temperatures that exists under the hood. A high-voltage and high-temperature gate-driver integrated circuit for SiC FET switches is designed and implemented in a 0.8-micron Silicon-on-Insulator high-voltage process. First prototype chip has been successfully tested up to 200degC ambient temperature without any heat sink or cooling mechanism. This gate-driver chip is intended to drive SiC power FETs of the DC-DC converters in a hybrid electric vehicle. The converter modules along with the gate-driver chip will be placed very close to the engine where the temperature can reach up to 175degC. Successful operation of the chip at this temperature with or without minimal heat sink and without liquid cooling will help achieve greater power-to-volume as well as power-to-weight ratios for the power electronics module. A second prototype has also been designed with more robust features.

A instrumentation channel has been designed, implemented and tested in a 0.5-mum SiGe BiCMOS process. The circuit features a reconfigurable Wheatstone bridge network that interfaces a range of external sensors to signal processing circuits. Also, analog sampling has been implemented in the channel using a flying capacitor configuration. Measurement results show the instrumentation channel supports input signals up to 200 Hz.

A multichannel low power analog-to-digital converter (ADC) designed, fabricated and tested in 0.5-mum Silicon Germanium BiCMOS process is reported. The 12-bit ADC features 8 input channels, each having a 10-Ksps sampling rate and an input voltage range of 1.2 V. The ADC architecture, comprised of a ramp generator, comparators, and a Gray code counter, is discussed along with design details of the primary blocks. Measurement data shows a differential nonlinearity of less than 0.5 LSB and an approximate accuracy of 10 bits.

A Sensor Control Chip (SCC) that can drive a 20 V adjustable output voltage swing and a maximum output current of 100 mA has been developed to provide the required clock and bias signals for the Large Synoptic Survey Telescope’s CCD imagers. The prototype chip has been fabricated in a 0.8-µm BCD-SOI process, and is designed to operate down to 175K. The circuit consists of current steering DACs followed by transimpedence operational amplifiers to control the rail voltages of the clock signals and bias voltages. The clocks are input to the SCC through LVDS receivers and converted internally to the required amplitude for driving the CCD. Design techniques will be presented along with room temperature and operational temperature test results obtained from prototype chips.

In this paper, we present a methodology for design and qualification of microelectronics for low temperature applications, which has enabled the successful infusion of a custom designed Operational Amplifier into flight mission. The Op-Amp was designed to target a wide temperature range of -150degC to +125degC for at least 5 years operation for Mars Mission. The design and qualification methodology developed have provided the critical path for the technology infusion.

A highly integrated system-on-chip is currently in development. Based on the flight-proven RAD6000™ microprocessor, this mixed-signal microcontroller supports a wide variety of standard digital interfaces commonly used in spacecraft avionics. Multiple analog input and output channels are also provided. This paper will discuss the RAD6000mc architecture, porting of the RAD6000 processor into a reusable core, development of the analog circuitry and analog control interface core, and various applications for which the RAD6000MC is well matched.

A data acquisition system is being developed for use on the NASA Lunar-Mars series of missions. The unit will accept inputs from multiple types of sensors, employing three types of input channels that each incorporate programmable elements to accommodate a wider variety of input signals. Based in part on a subsystem called the remote health node (RHN) that was originally developed during the 1990s for use on the now-defunct NASA X-33 "space plane", the remote electronics unit (REU) is being developed using a 0.5 micron silicon germanium (SiGe) BiCMOS technology from IBM with a circuit library that has been designed to operate normally across a temperature range from -180 degrees C up through +125 degrees C.

A case study is presented applying a design-for-reliability methodology to design, fabricate and qualify a quad rail-to-rail operational amplifier for the wide temperature range operation of -140degC to +125degC to for space applications. The design-for-reliability approach was developed and implemented from transistor level up to board/system level, along with a comprehensive qualification procedure for the wide temperature range. The quad op-amp is used for a flight mission and available from a commercial production line.

A high-voltage and high-temperature gate-driver chip for SiC FET switches is designed and fabricated using 0.8- micron, 2-poly and 3-metal BCD on SOI process. It can generate output voltage swing from -5 V to 30 V and can operate up to 175degC ambient temperature. This gate-driver chip is intended to drive SiC power FETs in DC-DC converters in a hybrid electric vehicle. The converter modules along with the gate-driver chip will be placed very close to the engine where the temperature can reach up to 175degC. Successful operation of the chip at this temperature without heat sink and liquid cooling will help to achieve greater power-to-volume as well as power-to-weight ratios for the power electronics module. Initial test results presented in this paper also validate the simulation.

The next generations of Martian rovers are to examine the polar regions where temperatures are extremely low and the absence of an earth-like atmosphere results in a plethora of radiation issues including Analogue Single Event Transients. To this end, a radiation-hardened, temperature compensated CMOS Single-On-Insulator operational amplifier was designed and fabricated using Honeywell's SOI V process. Broad beam heavy-ion tests at the University of Texas A&M were performed to ascertain the duration and severity of any SET's for low and high gain application. Ambiguity regarding the location of transient formation required the use of an ion microbeam to confirm a region of major concern in the internal bias circuitry.

The effects of proton irradiation on the performance of key devices and mixed-signal circuits fabricated in a SiGe BiCMOS IC design platform and intended for emerging lunar missions are presented. High-voltage (HV) transistors, SiGe bandgap reference (BGR) circuits, a general-purpose high input impedance operational amplifier (op amp), and a 12-bit digital-to-analog converter (DAC) are investigated. The circuits were designed and implemented in a first-generation SiGe BiCMOS technology and were irradiated with 63 MeV protons. The degradation due to proton fluence in each device and circuit was found to be minor, suggesting that SiGe HBT BiCMOS technology could be a robust platform for building electronic components intended for operation under extreme environments.

Field emission (FE) of electrons from nanostructured graphitic carbon-based materials has been an area of intense investigation in recent years. Each field emitting device has control gates and an electron emitting cathode, which emits electron when a sufficient voltage is applied at the gate electrode. Recently, a technique for fabricating gated cathode structures that uses a single in situ grown vertically aligned carbon nanofiber (VACNF) as a FE element has been reported. This paper presents digitally addressable VACNFs for implementation of massively parallel maskless lithography.

A novel voltage-controlled negative differential resistance device, using complementary SOI four-gate transistors (G4-FETs) is presented. Innovative LC oscillator and Schmitt trigger circuits based on the G4-FET NDR device are experimentally demonstrated

Novel G4-FET based logic-circuits (adjustable-threshold inverter, real-time reconfigurable logic gates and DRAM cell) are experimentally demonstrated. The independent action of the four gates helps minimize the required transistor count per logic function while enhancing design flexibility

This paper discusses the complete integration of the prototype digital electrostatic focused e-beam array direct-write lithography (DEAL) device with the dose control circuitry (DCC). The DCC regulates charge emission from the vertically aligned carbon nanofibers (VACNFs) and prevents resists from being over exposed during the e-beam lithography process. The emission of electrons from the VACNF tip requires relatively high voltage. The I-V characteristic of a typical VACNF based device is presented with threshold voltage of ~75 V. The DCC built using a standard 5 V digital CMOS process cannot handle such voltage levels

This paper presents a survivability and reliability investigation for integrated actuator and brushless motor drive electronics packaging and components under an extreme low temperature and high thermal cycle environment. A universal brushless motor drive electronics assembly has been designed, built, and thermal cycle tested for use in Mars, Moon, and asteroid type cold environments without the need for any active thermal control. The assembly uses electronic part types and chip-on-board electronic packaging technology that allow operation at temperatures down to -180degC. The thermal cycle capability of the assembly has been demonstrated to be in excess of 2010 cycles from -120degC to 85degC, over a 210degC total temperature swing. Future space missions will require electronic and actuator systems on a planet, asteroid or Moon surface to function beyond the established reliability limits of currently used components and materials systems. In support of this target application, the Jet Propulsion Laboratory (JPL) has performed a series of experiments to test the reliability of actuators, sensors, electronic components, and electronic packaging designs to provide input to the detailed flight design of a universal brushless motor drive electronics and integrated actuator assembly. These experiments started with the use of a chip-on-board electronic packaging strategy due to its inherent advantage of improved high functionality with minimal circuit board area compared with standard packaged electronic components. Initial electronic packaging experiments were comprised of various sized chip devices with gold wire bonds. The second phase of electronic packaging experiments conducted at JPL consisted of power devices with large diameter wire bonds as well as various surface mount resistor devices. Full factorial experiments were designed to find the most reliable combinations of substrate type, component attach method and encapsulation. The surviving material combinations after a minimum of 1500 thermal cycles were utilized to form the basis of the packaging and electronic component detailed design approach used in the universal brushless motor drive electronics design. Electrical failures were defined as open circuits. A failure analysis procedure was applied by defining the failure mechanism and applying a risk mitigation. After 1500 cycles, the packaged assembles were cycled to exceed 2010 cycles and additional material considerations were made. In addition, selected components were functionally tested over the temperature range of +100degC to -180degC and cold soaked at -150degC for 1000 hours for reliability. A design for reliability method was also developed at the component and circuit level for electronics operating at extreme low temperatures

A prototype neutron detector array has been developed for the Spallation Neutron Source (SNS). The High Efficiency Neutron Detector Array (HENDA) will be the highest spatial resolution neutron detecting linear array available anywhere. The front-end electronics have been developed on a prototype chip, Patara, from a TSMC 0.35-micron fabrication. The Patara chip is a 16-channel preamp/shaper/blr for high-efficiency solid-state neutron detectors. It features a regulated cascode preamplifier with adjustable gain, digitally adjustable leakage current compensation and active feedback reset network with matching pole/zero cancellation network, and an input pulse polarity adjustment. The shaper has a five-pole semi-Gaussian response utilizing two pairs of current-input complex-conjugate poles with gated baseline restoration. The system dissipates 3.7 mW/channel. Measurements indicate an overall gain of 9.7 mV/fC and 5.65 mV/fC for full- and half-gain settings, 270 nanosecond full-width half-maximum (FWHM) output, and 550 RMS electrons input noise for a 5 pF detector capacitance.

Bioluminescent bioreporter integrated circuits (BBICs) are hybrid microluminometer/whole-cell reporter sensor devices for monitoring target chemical and biological agents. The integrated circuit portion of the biosensor consists of a 0.35mum complementary metal oxide semiconductor (CMOS) photodiode capable of low level light detection within an approximate 2.25 mm2 footprint. Interfaced to it is a population of bioreporter microorganisms genetically engineered to specifically and reproducibly respond to desired analytes through autonomous, quantitative emission of luxCDABE-based bioluminescent light signals. The microluminometer chip detects these signals, processes them, and communicates the results either through cable or wireless interconnects for distributed biosensing. In addition, BBIC chips can be outfitted with auxiliary functions such as time stamping, positional sensing, or temperature measurement to provide a more thorough profile of the environment in which it is operating. Our existing laboratory set-up places the BBIC in-line with a liquid or air flow-through system for continuous online monitoring. A remote BBIC has also been developed for static monitoring in either liquid or vapor phase. Detection limits for tested bioreporters approach part-per-billion levels with response times of less than one hour. In progress evolution of BBIC design using nanostructured arrays of vertically aligned carbon nanofibers may permit multiplexed detection of chemical and biological agents in a single chip format

We investigate, for the first time, the design and implementation of a high-slew rate op-amp in SiGe BiCMOS technology capable of operation across very wide temperature ranges, and down to deep cryogenic temperatures. We achieve the first monolithic op-amp (for any material system) capable of operating reliably down to 4.3 K. Two variants of the SiGe BiCMOS op-amp were implemented using alternative biasing schemes, and the effects of temperature on these biasing schemes, and their impact on the overall op-amp performance, is investigated

An integrated CMOS microluminometer for detection of very low-level bioluminescence is presented. Signal processing is accomplished with a current-to-frequency converter circuit. Photodiode, integrator, voltage reference circuit and noise are analyzed in detail in this paper. The biosensor chip was fabricated using a standard 0.35mum CMOS process and dissipate 3 mW for 3.3 V power supply. Test results are given to prove the concept

We present the first investigation of the optimal implementation of SiGe BiCMOS precision voltage references for extreme temperature range applications (+120 degC to -180 degC and below). We have developed and fabricated two unique Ge profiles optimized specifically for cryogenic operation, and for the first time compare the impact of Ge profile shape on precision voltage reference performance down to -180 degC. Our best case reference achieves a 28.1 ppm/ degC temperature coefficient over +27 degC to -180 degC, more than adequate for the intended lunar electronics applications

We report a biosensor using genetically-engineered whole-cell bioreporters on integrated circuit for low-level chemical sensing. The bioluminescent bioreporters are bacteria that can be genetically altered to achieve bioluminescence when in contact with a targeted substance. The bioreporters are placed on a microluminometer. The microluminometer includes integrated photodetector and signal processor and is realized on a standard CMOS process. The bioluminescent bioreporter integrated circuit (BBIC) can detect luminescence from as few as 5000 fully induced pseudomonas fluorescene 5RL bacteria cell.

This paper presents a prototype implementation of a circuit that can control charge emission from the vertically aligned carbon nanofibers (VACNF), for use in the implementation of digital electrostatic e-beam array lithography (DEAL). This lithography technique can be used to fabricate ultra-small feature size devices, while cutting down the manufacturing costs of photomasks. These VACNF's are found to be quite robust for use as micro-fabricated field emission devices. The all inverter based dose control circuit (DCC) presented in this paper was fabricated using a standard 0.5 /spl mu/m CMOS process to improve the dose-rate accuracy, when using these VACNF's for etching in maskless lithography. Simulation and measurement results are compared and analyzed, and future work for improving the design is discussed.

Prototype field emission devices have been fabricated in the 300-1000 eV range using vertically aligned carbon nanofibers as the field emitter. The devices are fabricated using a self-aligned process for the extraction gate opening and the focus grid opening is defined lithographically. Field emission tests of the completed devices are carried out in a vacuum chamber with a phosphor anode and show that the emission follows Fowler-Nordheim characteristics. A technique to selectively grow fibers with W in digitally addressable field-emission array (DAFEA) prototype devices is demonstrated by nanoscale electron beam induced deposition (EBID). A non-organometallic precursor, WF/sub 6/, is used to deposited metallic W fibers. Vacuum electrical testing revels that electrons are successfully extracted from the W nanofiber tip and have been used to draw lines in PMMA coated glass substrates in the DEAL lithography testbed. This growth technique can be used to repair DAFEA emitters thus providing a means to produce a reliable massive parallel e-beam write head.

Silicon-on-insulator MESFETs have been manufactured using a commercial SOI CMOS process and their electrical characteristics measured from room temperature up to 200deg C. No modifications were made to the CMOS process flow. The prototype devices use a CoSi2 gate material and the gate current follows the expected Shottky diode behavior. At room temperature a 0.6 mum gate length device has a threshold voltage of -0.8 V with an off-state drain current of approximately 5 nA. The device shows an attractive family of I-V curves up to 200deg C. For higher temperatures the reverse diode current makes it hard to switch the device off. Numerical simulations of a similar device with a higher barrier height PtSi gate show reasonable behavior up to 300degC

Commercial-off-the-shelf electronic components (COTS) offer a very low cost and attractive solution for construction of electronic systems for Mars missions, including the actuator electronic systems for the Mars Rovers. One issue with using COTS lies in the difference between their specified operating temperature range (-55/spl deg/C to125/spl deg/C for military components) and the temperatures observed at the surface of Mars (-120/spl deg/C to 20/spl deg/C). To compensate for the difference between these temperatures, most of the electronics are placed in a central warm-electronics-box or WEB. In some cases, such as the distributed control system for the actuators, the electronic assemblies that are to be placed on or near the motors are outside of the central WEB. The experimental search consists of two steps. First, a short functional/non-functional test at -120/spl deg/C is used to identify and narrow down the number of candidate COTS that can work at very cold temperatures. More extensive characterization of the parts that passes the short test is performed to determine the operating margins and estimate the thermal cycle life capability for the COTS parts. Finally, the operating margins of the COTS parts are published as a set of specifications.