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Ben Blalock

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Office: Min Kao 503
E-mail:
ude.ktu@kcolalbb
Phone: 865-974-0927
Fax: 865-974-5483
Address: Min H. Kao Building, Suite 503
1520 Middle Drive
Knoxville, TN 37996-2250


Biography

Benjamin J. Blalock is the Blalock-Kennedy-Pierce Professor in the Department of Electrical Engineering and Computer Science at the University of Tennessee where he directs the Integrated Circuits and Systems Laboratory (ICASL).

He received his B.S. degree in electrical engineering from the University of Tennessee, Knoxville, in 1991 and the M.S. and Ph.D. degrees, also in electrical engineering, from the Georgia Institute of Technology, Atlanta, in 1993 and 1996 respectively.

Dr. Blalock has received numerous teaching and research awards at UT. His research focus at UT includes analog integrated circuit design for extreme environments (both wide temperature and radiation) on CMOS and SiGe BiCMOS, high-temperature/high-voltage gate drive circuits for power electronics, multi-channel monolithic instrumentation systems, mixed-signal/mixed-voltage circuit design for systems-on-a-chip, and analog circuit techniques for sub 100-nm CMOS.

Dr. Blalock has co-authored over 100 refereed papers. During the 2007 IEEE Nuclear Science and Radiation Effects Conference (NSREC) he taught a short course on Radiation Effects on Analog Integrated Circuits and Extreme Environment Design. He has also worked as an analog IC design consultant for Cypress Semiconductor, Concorde Microsystems, and Global Power Electronics. Dr. Blalock is a senior member of the IEEE.

Publications


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Journal Papers
Title
Year
  • Zheyu Zhang; Ben Guo; Fei Fred Wang; Edward A. Jones; Leon M. Tolbert; Benjamin J. Blalock
    IEEE Transactions on Power Electronics
    2017

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    The double pulse test (DPT) is a widely accepted method to evaluate the dynamic behavior of power devices. Considering the high switching-speed capability of wide band-gap devices, the test results are very sensitive to the alignment of voltage and current (V-I) measurements. Also, because of the shoot-through current induced by Cdv/dt (i.e., cross-talk), the switching losses of the nonoperating switch device in a phase-leg must be considered in addition to the operating device. This paper summarizes the key issues of the DPT, including components and layout design, measurement considerations, grounding effects, and data processing. Additionally, a practical method is proposed for phase-leg switching loss evaluation by calculating the difference between the input energy supplied by a dc capacitor and the output energy stored in a load inductor. Based on a phase-leg power module built with 1200-V/50-A SiC MOSFETs, the test results show that this method can accurately evaluate the switching loss of both the upper and lower switches by detecting only one switching current and voltage, and it is immune to V-I timing misalignment errors.

  • Zheyu Zhang; Jeffery Dix; Fei Fred Wang; Benjamin J. Blalock; Daniel Costinett; Leon M. Tolbert
    IEEE Transactions on Power Electronics
    2017

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    This paper presents an intelligent gate drive for silicon carbide (SiC) devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control gate voltages and gate loop impedances of both devices in a phase-leg configuration during different switching transients. Compared to conventional gate drives, the proposed circuit has the capability of accelerating the switching speed of the phase-leg power devices and suppressing the crosstalk to below device limits. Based on Wolfspeed 1200-V SiC MOSFETs, the test results demonstrate the effectiveness of this intelligent gate drive under varying operating conditions. More importantly, the proposed intelligent gate assist circuitry is embedded into a gate drive integrated circuit, offering a simple, compact, and reliable solution for end-users to maximize benefits of SiC devices in actual power electronics applications.

  • Weimin Zhang; Fred Wang; Daniel J. Costinett; Leon M. Tolbert; Benjamin J. Blalock
    IEEE Transactions on Power Electronics
    2017

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    Newly emerged gallium nitride (GaN) devices feature ultrafast switching speed and low on-state resistance that potentially provide significant improvements for power converters. This paper investigates the benefits of GaN devices in an LLC resonant converter and quantitatively evaluates GaN devices' capabilities to improve converter efficiency. First, the relationship of device and converter design parameters to the device loss is established based on an analytical model of LLC resonant converter operating at the resonance. Due to the low effective output capacitance of GaN devices, the GaN-based design demonstrates about 50% device loss reduction compared with the Si-based design. Second, a new perspective on the extra transformer winding loss due to the asymmetrical primary-side and secondary-side current is proposed. The device and design parameters are tied to the winding loss based on the winding loss model in the finite element analysis (FEA) simulation. Compared with the Si-based design, the winding loss is reduced by 18% in the GaN-based design. Finally, in order to verify the GaN device benefits experimentally, 400- to 12-V, 300-W, 1-MHz GaN-based and Si-based LLC resonant converter prototypes are built and tested. One percent efficiency improvement, which is 24.8% loss reduction, is achieved in the GaN-based converter.

  • Yutian Cui; Fei Yang; Leon M. Tolbert; Daniel J. Costinett; Fred Wang; Benjamin J. Blalock
    IEEE Transactions on Power Electronics
    2017

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    With the increased cloud computing and digital information storage, the energy requirement of data centers keeps increasing. A high-voltage point of load (HV POL) with an input series output parallel structure is proposed to convert 400 to 1 VDC within a single stage to increase the power conversion efficiency. The symmetrical controlled half-bridge current doubler is selected as the converter topology in the HV POL. A load-dependent soft-switching method has been proposed with an auxiliary circuit that includes inductor, diode, and MOSFETs so that the hard-switching issue of typical symmetrical controlled half-bridge converters is resolved. The operation principles of the proposed soft-switching half-bridge current doubler have been analyzed in detail. Then, the necessity of adjusting the timing with the loading in the proposed method is analyzed based on losses, and a controller is designed to realize the load-dependent operation. A lossless RCD current sensing method is used to sense the output inductor current value in the proposed load-dependent operation. Experimental efficiency of a hardware prototype is provided to show that the proposed method can increase the converter's efficiency in both heavy- and light-load conditions.

  • Zheyu Zhang; Haifeng Lu; Daniel J. Costinett; Fred Wang; Leon M. Tolbert; Benjamin J. Blalock
    IEEE Transactions on Power Electronics
    2017

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    Dead time significantly affects the reliability, power quality, and efficiency of voltage-source converters. For silicon carbide (SiC) devices, considering the high sensitivity of turn-off time to the operating conditions (> 5× difference between light load and full load) and characteristics of inductive loads (> 2× difference between motor load and inductor), as well as large additional energy loss induced by the freewheeling diode conduction during the superfluous dead time (~15% of the switching loss), then the traditional fixed dead time setting becomes inappropriate. This paper introduces an approach to adaptively regulate the dead time considering the current operating condition and load characteristics via synthesizing online monitored turn-off switching parameters in the microcontroller with an embedded preset optimization model. Based on a buck converter built with 1200-V SiC MOSFETs, the experimental results show that the proposed method is able to ensure reliability and reduce power loss by 12% at full load and 18.2% at light load (8% of the full load in this case study).

  • Fan Xu; Ben Guo; Zhuxian Xu; Leon M. Tolbert; Fei Wang; Benjamin J. Blalock
    IEEE Transactions on Industry Applications
    2015

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    This paper presents the paralleling operation of three-phase current-source rectifiers (CSRs) as the front-end power conversion stage of data center power supply systems based on 400-Vdc power delivery architecture, which has been proven to have higher efficiency than traditional ac architectures. A control algorithm of paralleled three-phase CSRs is introduced to achieve balanced outputs and individual rectifier module hot swap, which are required by power supply systems. By using silicon carbide (SiC) power semiconductors, SiC MOSFETs, and Schottky diodes, the power losses of the front-end stage are reduced, and the power supply system efficiency can be further increased. The prototype of a 19-kW front-end rectifier to convert 480 Vac,rms to 400 Vdc, based on three paralleled three-phase CSRs, is developed. Each CSR is an all-SiC converter and designed for high efficiency, and the front-end stage full-load efficiency is greater than 98% from experimental tests. The balanced outputs and individual converter hot swap are realized in the hardware prototype too.

  • Zhiqiang Wang; Xiaojie Shi; Leon M. Tolbert; Fei (Fred) Wang; Zhenxian Liang; Daniel Costinett; Benjamin J. Blalock
    IEEE Transactions on Power Electronics
    2015

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    This paper presents a board-level integrated silicon carbide (SiC) mosfet power module for high temperature and high power density application. Specifically, a silicon-on-insulator (SOI)-based gate driver capable of operating at 200 °C ambient temperature is designed and fabricated. The sourcing and sinking current capability of the gate driver are tested under various ambient temperatures. Also, a 1200 V/100 A SiC mosfet phase-leg power module is developed utilizing high temperature packaging technologies. The static characteristics, switching performance, and short-circuit behavior of the fabricated power module are fully evaluated at different temperatures. Moreover, a buck converter prototype composed of the SOI gate driver and SiC power module is built for high temperature continuous operation. The converter is operated at different switching frequencies up to 100 kHz, with its junction temperature monitored by a thermosensitive electrical parameter and compared with thermal simulation results. The experimental results from the continuous operation demonstrate the high temperature capability of the power module at a junction temperature greater than 225 °C.

  • Zheyu Zhang; Fred Wang; Leon M. Tolbert; Benjamin J. Blalock; Daniel J. Costinett
    IEEE Transactions on Power Electronics
    2015

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    Double pulse test (DPT) is a widely accepted method to evaluate the switching characteristics of semiconductor switches, including SiC devices. However, the observed switching performance of SiC devices in a PWM inverter for induction motor drives is almost always worse than the DPT characterization, with slower switching speed, more switching losses, and more serious parasitic ringing. This paper systematically investigates the factors that limit the SiC switching performance from both the motor side and inverter side, including the load characteristics of induction motor and power cable, two more phase legs for the three-phase PWM inverter in comparison with the DPT, and the parasitic capacitive coupling effect between power devices and heat sink. Based on a three-phase PWM inverter with 1200 V SiC MOSFETs, test results show that the induction motor, especially with a relatively long power cable, will significantly impact the switching performance, leading to a switching time increase by a factor of 2, switching loss increase up to 30% in comparison with that yielded from DPT, and serious parasitic ringing with 1.5 μs duration, which is more than 50 times of the corresponding switching time. In addition, the interactions among the three phase legs cannot be ignored unless the decoupling capacitors are mounted close to each phase leg to support the dc bus voltage during switching transients. Also, the coupling capacitance due to the heat sink equivalently increases the junction capacitance of power devices; however, its influence on the switching behavior in the motor drives is small considering the relatively large capacitance of the motor load.

  • Zheyu Zhang; Fred Wang; Leon M. Tolbert; Benjamin J. Blalock
    IEEE Transactions on Power Electronics
    2014

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    In a phase-leg configuration, the high-switching-speed performance of silicon carbide (SiC) devices is limited by the interaction between the upper and lower devices during the switching transient (crosstalk), leading to additional switching losses and overstress of the power devices. To utilize the full potential of fast SiC devices, this paper proposes two gate assist circuits to actively suppress crosstalk on the basis of the intrinsic properties of SiC power devices. One gate assist circuit employs an auxiliary transistor in series with a capacitor to mitigate crosstalk by gate loop impedance reduction. The other gate assist circuit consists of two auxiliary transistors with a diode to actively control the gate voltage for crosstalk elimination. Based on CREE CMF20120D SiC MOSFETs, the experimental results show that both active gate drivers are effective to suppress crosstalk, enabling turn-on switching losses reduction by up to 17%, and negative spurious gate voltage minimization without the penalty of decreasing the switching speed. Furthermore, both gate assist circuits, even without a negative isolated power supply, are more effective in improving the switching behavior of SiC devices in comparison to the conventional gate driver with a -2 V turn-off gate voltage. Accordingly, the proposed active gate assist circuits are simple, efficient, and cost-effective solutions for crosstalk suppression.

  • Benjamin M. McCue; Benjamin J. Blalock; Charles L. Britton; Jeff Potts; James Kemerling; Kiyosi Isihara; Matthew T. Leines
    IEEE Transactions on Nuclear Science
    2013

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    Many design techniques have been incorporated into modern CMOS design practices to improve radiation tolerance of integrated circuits. Annular-gate NMOS structures have been proven to be significantly more radiation tolerant than the standard, straight-gate variety. Many circuits can be designed using the annular-gate NMOS and the inherently radiation tolerant PMOS. Bandgap reference circuits, however, typically require p-n junction diodes. These p-n junction diodes are the dominating factor in radiation degradation in bandgap reference circuits. This paper proposes a different approach to bandgap reference design to alleviate the radiation susceptibility presented by the p-n junction diodes.

  • Ryan M. Diestelhorst; Troy D. England; Richard Berger; Ray Garbos; Chandradevi Ulaganathan; Ben Blalock; Kimberly Cornett; Alan Mantooth; Xueyang Geng; Foster Dai; Wayne Johnson; Jim Holmes; Mike Alles; Robert Reed; Patrick McCluskey; Mohammad Mojarradi; Leora Peltz; Robert Frampton; Cliff Eckert; John D. Cressler
    IEEE Aerospace and Electronic Systems Magazine
    2012

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    We have described the modeling, circuit design, system integration, and measurement of a Remote Sensor Interface (Figure 20) that took place over a span of 5 years and 8 fabrication cycles. It was conceived as part of the Multi-Chip Module (MCM) shown in Figure 21, which also includes a digital control chip for clocking, programming, and read-out. Further work beyond the scope of this was performed to validate the RSI for the extreme environmental conditions of a lunar mission, and individual blocks are presently.

  • K. V. Tham; C. Ulaganathan; N. Nambiar; R. L. Greenwell; C. L. Britton; M. N. Ericson; J. Holleman; B. J. Blalock
    IEEE Transactions on Nuclear Science
    2012

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    A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a 12-bit multi-channel Wilkinson (single-slope integrating) Analog-to-Digital converter (ADC). This PWLL was designed and fabricated in a 0.5- μm Silicon Germanium (SiGe) BiCMOS process. Simulation and silicon measurement data are shown that demonstrate a large improvement in the accuracy of the PVT-compensated ADC over the uncompensated ADC.

  • T. D. England; R. M. Diestelhorst; E. W. Kenyon; J. D. Cressler; V. Ramachandran; M. Alles; R. Reed; R. Berger; R. Garbos; B. Blalock; A. Mantooth; M. Barlow; F. Dai; W. Johnson; C. Ellis; J. Holmes; C. Webber; P. McCluskey; M. Mojarradi; L. Peltz; R. Frampton; C. Eckert
    IEEE Aerospace and Electronic Systems Magazine
    2012

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    We have presented the architecture, simulation, packaging, and over-temperature and radiation testing of a complex, 16-channel, extreme environment capable, SiGe Remote Electronics Unit containing the Remote Sensor Interface ASIC that can serve a wide variety of space-relevant needs as designed. These include future missions to the Moon and Mars, with the additional potential to operate in other hostile environments, including lunar craters and around the Jovian moon, Europa. We have expanded on the previous introduction of the RSI to show the validity of the chip design and performance over an almost 250 K temperature range, down to 100 K, under 100 krad TID radiation exposure, with SEL immunity and operability in a high-flux SET environment.

  • Mohammad A. Huque; Syed K. Islam; Leon M. Tolbert; Benjamin J. Blalock
    IEEE Transactions on Power Electronics
    2012

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    High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 °C. This new gate driver prototype has been designed and implemented in a 0.8 μm, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 °C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature (≥220 °C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 μW for operating temperature up to 200 °C.

  • Sazia A. Eliza; Syed K. Islam; Touhidur Rahman; Nora Dianne Bull; Benjamin J. Blalock; Larry R. Baylor; M. Nance Ericson; Walter L. Gardner
    IEEE Transactions on Instrumentation and Measurement
    2011

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    This paper describes a highly accurate dose control circuit (DCC) for the emission of a desired number of electrons from vertically aligned carbon nanofibers (VACNFs) in a massively parallel maskless e-beam lithography system. The parasitic components within the VACNF device cause a premature termination of the electron emission, resulting in underexposure of the photoresist. In this paper, we compensate for the effects of the parasitic components and noise while reducing the area of the chip and achieving a precise count of emitted electrons from the VACNFs to obtain the optimum dose for the e-beam lithography.

  • 2010

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    Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimising system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8--m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

  • Tan Zhang; Zhenwei Hou; R. Wayne Johnson; Linda Del Castillo; Alina Moussessian; Robert Greenwell; Benjamin J. Blalock
    IEEE Transactions on Electronics Packaging Manufacturing
    2009

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    Silicon thinned to 50 mum and less is flexible allowing the fabrication of flexible and conformable electronics. Two techniques have been developed to achieve this goal using thinned die: die flip chip bonded onto flexible substrates [polyimide and liquid crystal polymer (LCP)] and die flip chip laminated onto LCP films. A key to achieving each of these techniques is the thinning of die to a thickness of 50 mum or thinner. Conventional grinding and polishing can be used to thin to 50 mum. At 50 mum, the active die becomes flexible and must be handled by temporarily bonding it to a holder die for assembly. Both reflow solder and thermocompression assembly methods are used. In the case of solder assembly, underfill is used to reinforce the solder joints. With thermocompression bonding of the die to an LCP substrate, the LCP adheres to the die surface, eliminating the need for underfill.

  • Kerem Akarvardar; Ronald D. Schrimpf; Daniel M. Fleetwood; Sorin Cristoloveanu; Pierre Gentil; Benjamin J. Blalock
    IEEE Transactions on Nuclear Science
    2007

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    Radiation-induced dopant passivation is evidenced for the first time in partially-depleted SOI n-channel MOSFETs. Isochronal annealing experiments following 10 Mrad(SiO2) irradiation demonstrate that the neutralization of boron atoms in the NMOSFET body is most pronounced in the 125degC-150degC temperature range. This results in an abrupt decrease of the threshold voltage and the subthreshold swing, due to the transition of the body from partial to full depletion. The SOI four-gate transistor, inherently present in the partially-depleted MOSFET structure, is demonstrated to be a very efficient tool for monitoring dopant neutralization through irradiation and annealing. Radiation-induced dopant passivation has important consequences regarding the reliability of short-channel partially-depleted NMOSFETs.

  • Syed K. Islam; Rajagopal Vijayaraghavan; Mo Zhang; Steven Ripp; Sam D. Caylor; Brandon Weathers; Scott Moser; Stephen Terry; Benjamin J. Blalock; Gary S. Sayler
    IEEE Transactions on Circuits and Systems I: Regular Papers
    2007

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    A low-power CMOS bioluminescent bioreporter integrated circuit (BBIC) is designed and fabricated for use in electronic/biological chemical sensing. The bioreporters are placed on a CMOS integrated circuit (IC) that detects bioluminescence, performs signal processing and produces a digital output pulse with a frequency that is proportional to the concentration of the target substance. The digital output pulse that contains the sensor information can then be transmitted to a remote location either wirelessly or via a data cable. The basic building blocks of the integrated circuit are the microluminometer and the transmitter. The microluminometer includes an integrated photodetector and a signal processor and is housed in a rugged inexpensive package that can be used in many remote applications in hazardous environmental monitoring. The total power consumption of the entire signal processing circuitry including the photodiodes is 3 mW from a 3.3-V power supply. This is lowered by a factor of 3 when compared to previous versions of the BBIC. In addition, it also integrates all features of detection, processing and data transmission into one small element. The bioreporter typically contains the luxCDABE reporter genes. The close proximity of the bioreporter and the sensing element eliminates the need for complex instrumentation to channel light from the bioreporters to the microluminometer. This paper presents an integrated CMOS microluminometer realized in 0.35-mum CMOS process and optimized for the detection of low-level bioluminescence as part of the BBIC. A flow-through test system was designed to expose the BBIC system composed of the microluminometer and the bioreporter Pseudomonas fluorescens 5RL to salicylate for determination of analytical benchmark data. The results obtained from the experiment are currently being used to study enclosures and micro-environment configurations for field-deployable BBICs for environmental monitoring

  • Kerem Akarvardar; Sorin Cristoloveanu; Pierre Gentil; Ronald D. Schrimpf; Benjamin J. Blalock
    IEEE Transactions on Electron Devices
    2007

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    In the silicon-on-insulator four-gate transistors (G4-FETs), the conducting channel can be surrounded by depletion regions induced by independent vertical metal-oxide-semiconductor gates and lateral JFET gates. This unique conduction mechanism named depletion-all-around (DAA) enables majority carriers to flow in the volume of the silicon film far from the silicon/oxide interfaces. Especially when the interfaces are driven to inversion, the control of the lateral JFET gates on the conduction is maximized, while the sensitivity of the volume channel to the oxide and interface defects is minimized. This leads to excellent analog performance, low noise, and reduced sensitivity to ionizing radiation. The G4-FET properties in DAA mode are presented from multiple perspectives: experimental results, 3-D device simulations, and analytical modeling

  • K. Akarvardar; B. M. Dufrene; S. Cristoloveanu; P. Gentil; B. J. Blalock; M. M. Mojarradi
    IEEE Transactions on Electron Devices
    2006

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    Low-frequency noise characteristics of the silicon-on-insulator four-gate transistor [G4-field-effect transistor] are reported. The noise power spectral density as a function of biasing conditions is presented and compared for surface and volume conduction modes. It is shown that, for the same drain current, the volume of the transistor generates less noise than its surface. The possible transition from carrier-number fluctuations to mobility fluctuations as the conducting channel is moved away from the surface toward the volume is also discussed.

  • A. L. Sternberg; L. W. Massengill; M. Hale; B. Blalock
    IEEE Transactions on Nuclear Science
    2006

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    Circuit simulations are used to determine the response of a pipelined analog-to-digital converter (ADC) to radiation-induced single-event transients. The ADC uses a cascade of 9 stages which each resolve 1.5 bits. Digital error correction is used to reassemble the bits and to correct for errors in the comparators and sub-DAC. A Monte-Carlo methodology is used to simulate the single-event vulnerability of the circuit. Circuit simulations are performed using the Spectre circuit simulator. Sensitive cross-sections were derived from an analysis of the simulation results. Sensitive areas were identified and hardening techniques were applied to the circuit. These techniques may be applicable to other mixed-signal and switched-capacitor circuits. A significant reduction in the sensitive cross-section was obtained by application of these hardening techniques

  • S. C. Terry; B. J. Blalock; J. M. Rochelle; M. N. Ericson; S. D. Caylor
    IEEE Transactions on Nuclear Science
    2005

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    A custom simulation tool that combines HSPICE and MATLAB to enable time-domain noise analysis is reported. The simulation technique is based on computing the statistics of a random process by ensemble averaging and is applicable to both linear time-invariant (LTI) and linear time-variant (LTV) systems. MATLAB is used to generate a set of representative noise signals, which are imported into HSPICE for simulation. Once the simulations are complete the results are read back into MATLAB and ensemble statistics are calculated. The MATLAB-generated noise signals have a user-defined white-noise floor and flicker-noise corner frequency and thus are suitable for modeling a wide variety of electronic components, including CMOS transistors and resistors. Simulation results of the time-dependent output noise of a gated integrator and the timing resolution of a gated integrator/comparator detector are presented to highlight both the utility and the versatility of the tool.

  • B. K. Swann; B. J. Blalock; L. G. Clonts; D. M. Binkley; J. M. Rochelle; E. Breeding; K. M. Baldwin
    IEEE Journal of Solid-State Circuits
    2004

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    An integrated CMOS subnanosecond time-to-digital converter (TDC) has been developed and evaluated for positron emission tomography (PET) front-end applications. The TDC architecture combines an accurate digital counter and an analog time interpolation circuit to make the time interval measurement. The dynamic range of the TDC is programmable and can be easily extended without any timing resolution degradation. The converter was designed to operate over a reference clock frequency range of 62.5 MHz up to 100 MHz and can have a bin size as small as 312.5 ps LSB with 100-ns conversion times. Measurements indicate the TDC achieves a DNL of under ±0.20 LSB and INL less than ±0.30 LSB with an rms timing resolution of 0.312 LSB (97.5 ps), very close to the theoretical limit of 0.289 LSB (90 ps). The design is believed to be the first fully integrated CMOS subnanosecond TDC used in PET medical imaging and the first realization of a CMOS TDC that achieves an rms timing resolution below 100 ps within a 100-ns conversion time.

  • D. M. Binkley; C. E. Hopper; J. D. Cressler; M. M. Mojarradi; B. J. Blalock
    IEEE Transactions on Nuclear Science
    2004

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    Total dose and single-event radiation hardness, and operation over extreme temperatures make silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) processes leading contenders for space applications. This paper reports noise degradation of 0.35-μm partially-depleted SOI CMOS devices and a micropower, low-noise preamplifier following 63-MeV proton irradiation to 1Mrad (Si). Proton irradiation, relevant for space mission environments, was considered since it induces both ionizing and displacement damage. Preamplifier input-referred white-noise voltage was minimized at low power consumption by operating input devices in moderate inversion for high transconductance efficiency. Flicker-noise, important for gyros and other mission sensors having low-frequency outputs, was minimized by large-area pMOS input devices and careful management of noninput devices. Measured 1-Hz gate-referred, flicker-noise voltage density increased 24 and 32% for pMOS and nMOS test devices respectively following 1 Mrad (Si) irradiation. Measured 1-Hz input-referred noise voltage density increased 22% between a nonirradiated and radiated preamplifier sample, which agrees closely with the 24% increase expected since noise is dominated by pMOS input devices. Device small-signal transconductance and white-noise were largely unchanged while output conductance appeared to increase over a factor-of-three. This suggests a modest design margin is required to maintain flicker noise performance, while substantial design margin may be required to maintain open-loop voltage gain.

  • B. Dufrene; K. Akarvardar; S. Cristoloveanu; B. J. Blalock; R. Gentil; E. Kolawa; M. M. Mojarradi
    IEEE Transactions on Electron Devices
    2004

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    The four-gate silicon-on-insulator transistor (G4-FET) combines MOS and JFET actions in a single transistor to control the drain current. The various operation modes of the G4-FET are analyzed, based on the measured current-voltage, transconductance and threshold characteristics. The main parameters (threshold voltage, swing, mobility) are extracted and shown to be optimized for particular combinations of gate biasing. Numerical simulations are used to clarify the role of volume or interface conduction mechanisms. Besides excellent performance (such as subthreshold swing and transconductance) and unchallenged flexibility, the new device has the unique feature to allow independent switching by its four separate gates, which inspires many innovative applications.

  • B. K. Swann; J. M. Rochelle; D. M. Binkley; B. S. Puckett; B. J. Blalock; S. C. Terry; J. C. Moyers; J. W. Young; M. E. Casey; M. S. Musrock; J. E. Breeding
    IEEE Transactions on Nuclear Science
    2003

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    A custom mixed-signal CMOS integrated circuit has been developed for high performance positron emission tomography (PET) front-end applications. The application specific integrated circuit (ASIC) contains four differential variable-gain constant bandwidth amplifiers, which receive buffered photomultiplier tube (PMT) voltage pulses. All four amplified PMT signals are summed by adding their outputs and feeding this sum to the timing channel of the ASIC. The timing channel, which consists of a constant fraction discriminator and subnanosecond time to digital converter, offers excellent PET count rate performance and randoms noise reduction through low deadtime (100 ns) and excellent timing resolution (312.5 ps LSB). Amplified PMT signals are also distributed to energy processing channels for lowpass filtering and buffering for subsequent digitization by external ADCs. The ASIC offers substantial size, power, and cost reductions over existing PET front-end discrete designs. Fabricated in a 5 V, 0.5 μm, triple metal, double poly, n-well CMOS process, the new ASIC has a die size of 20 mm2 and dynamic power dissipation under 425 mW.

  • M. N. Ericson; C. L. Britton; J. M. Rochelle; B. J. Blalock; D. M. Binkley; A. L. Wintenberg; B. D. Williamson
    IEEE Transactions on Nuclear Science
    2003

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    This paper presents a summary of the measured noise behavior of CMOS MOSFETs fabricated in the Peregrine 0.5 μm fully depleted (FD) silicon-on-sapphire (SOS) process. SOS CMOS technology provides an alternative to standard bulk CMOS processes for high-density detector front-end electronics due to its inherent radiation tolerance. In this paper, the flicker noise behavior of SOS devices will be presented and discussed with reference to device inversion coefficient (IC). The concept of inversion coefficient will be introduced and the results of SOS device noise measurements in weak, moderate, and strong inversion will be presented and compared for devices with gate lengths of 0.5 μm to 4 μm. Details of the noise measurement system will be provided including specifics of the measurement approach and custom circuits used for device biasing. This work will provide a thorough presentation of measured SOS device flicker noise as a function of inversion coefficient. In addition, strategies for device biasing and sizing to obtain optimum flicker noise performance will be presented encouraging more widespread use of SOS integrated circuits in high-density detector applications.

  • S. C. Terry; J. M. Rochelle; D. M. Binkley; B. J. Blalock; D. P. Foty; M. Bucher
    IEEE Transactions on Nuclear Science
    2003

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    Design requirements for high-density detector front-ends and other high-performance analog systems routinely force designers to operate devices in moderate inversion. However, CMOS models have traditionally not handled this operating region very well. In this paper, the Berkeley Short-Channel IFGET Model (BSIM3V3) and EKV 2.6 MOSFET models are evaluated in terms of their ability to model low-voltage analog circuits. Simulation results for a standard 0.5 μm CMOS process are presented and compared to measured data. The data presented includes simulated and measured output conductance and transconductance efficiency for devices with channel lengths ranging from 0.5 μm to 33 μm. In addition, the models are compared in terms of their ability to handle the different operating regions of the MOS transistor (weak, moderate, and strong inversion). The results highlight the difficulty of obtaining a model that accurately predicts the operation of high-performance analog systems.

  • Ying Li; Guofu Niu; J. D. Cressler; J. Patel; M. Liu; M. M. Mojarradi; R. A. Reed; P. W. Marshall; B. J. Blalock
    IEEE Transactions on Nuclear Science
    2003

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    We investigate proton damage in SOI CMOS devices on UNIBOND using a variety of lateral bipolar operational modes. We show that the impact of interface states and oxide charge can be more clearly observed using lateral bipolar action than by using normal FET operational characteristics. We also investigate the radiation-induced interface states at the Si/buried oxide interface and oxide charges in the buried oxide of this SOI CMOS technology using the DCIV method.

  • M. Mojarradi; D. Binkley; B. Blalock; R. Andersen; N. Ulshoefer; T. Johnson; L. Del Castillo
    IEEE Transactions on Neural Systems and Rehabilitation Engineering
    2003

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    This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 × 400-μm pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1°C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic.

  • S. A. Jackson; J. C. Killens; B. J. Blalock
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
    2001

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    This paper describes a programmable current mirror comprised of single-poly floating-gate devices. By programming the threshold voltage of the floating-gate devices, a current mirror's input-output current mismatch can be trimmed at a desired current level. This programmability allows accurate drain current matching to be achieved without using large gate area devices. A prototype of the programmable current mirror fabricated in a 0.5-micron digital CMOS technology achieves 0.04% input-output current matching

  • B. J. Blalock; P. E. Allen; G. A. Rincon-Mora
    IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
    1998

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    This paper addresses the difficulty of designing 1-V capable analog circuits in standard digital complementary metal-oxide-semiconductor (CMOS) technology, Design techniques for facilitating 1-V operation are discussed and 1-V analog building block circuits are presented. Most of these circuits use the bulk-driving technique to circumvent the metal-oxide-semiconductor field-effect transistor turn-on (threshold) voltage requirement. Finally, techniques are combined within a 1-V CMOS operational amplifier with rail-to-rail input and output ranges. While consuming 300 μW, the 1-V rail-to-rail CMOS op amp achieves 1.3-MHz unity-gain frequency and 57° phase margin for a 22-pF load capacitance

Conference Papers
Title
Year
  • Ruirui Chen; Zheyu Zhang; Ren Ren; Jiahao Niu; Handong Gui; Fred Wang; Leon M. Tolbert; Daniel J. Costinett; Benjamin J. Blalock
    2018 IEEE Applied Power Electronics Conference and Exposition (APEC)
    2018

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    Unlike conventional passive or active filters, an impedance balancing circuit reduces the common-mode (CM) electromagnetic interference (EMI) noise by establishing an impedance balancing bridge. The EMI noise can be significantly reduced when the impedance bridge is designed to be well balanced. This paper investigates impedance balancing circuits in Dc-fed motor drive systems where both DC input and AC output need to meet EMI standards and thus EMI filters are needed for both sides. An impedance balancing circuit is proposed to reduce both DC and AC side CM noise. Two auxiliary branches are added to the conventional passive filters to establish an impedance bridge and reduce CM noise. The design criteria are presented, and the impact of the proposed impedance balancing circuit on both sides CM noise are investigated. It shows that the proposed impedance balancing circuit can reduce DC side and AC side CM noise based on different mechanisms. The CM noise reduction performance of the proposed method does not depend on the motor and cable models. Experiment results are presented to demonstrate the feasibility and effectiveness of the proposed method.

  • Jacob Dyer; Zheyu Zhang; Fred Wang; Daniel Costinett; Leon M. Tolbert; Benjamin J. Blalock
    2018 IEEE Applied Power Electronics Conference and Exposition (APEC)
    2018

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    Dead-time, device output capacitance, and other non-ideal characteristics cause voltage error for the midpoint PWM voltage of the semiconductor phase-leg employed in a voltage-source inverter (VSI). Voltage-second balancing is a well-known concept to mitigate this distortion and improve converter power quality. This paper proposes a unique voltage-second balancing scheme for a SiC based voltage source inverter using online condition monitoring of turn-off delay time and drain-source voltage rise/fall time. This data is sent to the micro-controller to be used in an algorithm to actively adjust the duty cycle of the input PWM gate signals to match the voltage-second of the non-ideal output voltage with an ideal output voltage-second. The monitoring system also allows for this implementation to eliminate the need for precise current sensing and allows for the implementation to be load independent. Dynamic current sensing is still a developing technology, and each load has a unique effect on the output voltage distortion. Test results for a 1 kW half-bridge inverter implementing this monitoring system and voltage-second balancing scheme show a 70% enhancement on the error against the ideal fundamental current value of the output current and a 2% THD improvement on the output current low frequency harmonics.

  • Yutian Cui; Leon M. Tolbert; Daniel J. Costinett; Fred Wang; Benjamin J. Blalock
    2018 IEEE Applied Power Electronics Conference and Exposition (APEC)
    2018

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    Data centers consume an ever-increasing amount of electricity because of the rapid growth of cloud computing and digital information storage. A high voltage point of load (HV POL) converter is proposed to convert the 400-VDC distribution voltage to 1-VDC within a single stage to increase the power conversion efficiency. A six-phase input series output parallel (ISOP) connected structure is implemented for the HV POL. The symmetrical controlled half bridge current doubler is selected as the converter topology in the ISOP structure. The full load efficiency is improved by 4% points compared with state of the art products. A voltage compensator has been designed in order to meet the strict dynamic voltage regulation requirement. A laboratory prototype has been built, and experimental results have been provided to verify the proposed HV POL with a single power conversion stage can meet the dynamic voltage regulation requirement for an on-board power supply with higher efficiency compared to the conventional architecture.

  • Zheyu Zhang; Handong Gui; Jiahao Niu; Ruirui Chen; Fred Wang; Leon M. Tolbert; Daniel J. Costinett; Benjamin J. Blalock
    2018 IEEE Applied Power Electronics Conference and Exposition (APEC)
    2018

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    Due to the low availability, high cost, and limited performance of high voltage power devices in high voltage high power applications, series-connection of low voltage switches is commonly considered. Practically, because of the dynamic voltage unbalance and the resultant reliability issue, switches in series-connection are not popular, especially for fast switching field-effect transistors such as silicon (Si) super junction MOSFETs, silicon carbide (SiC) JFETs, SiC MOSFETs, and gallium nitride (GaN) HEMTs, since their switching performance is highly sensitive to gate control, circuit parasitics, and device parameters. In the end, slight mismatch can introduce severe unbalanced voltage. This paper proposes an active voltage balancing scheme, including 1) tunable gate signal timing unit between series-connected switches with <; 1 ns precision resolution by utilizing a high resolution pulse-width modulator (HRPWM) which has existed in micro-controllers; and 2) online voltage unbalance monitor unit integrated with the gate drive as the feedback. Based on the latest generation 600-V Si CoolMOS, experimental results show that the dynamic voltage can be automatically well balanced in a wide range of operating conditions, and more importantly, the proposed scheme has no penalty for high-speed switching.

  • Gabriel Gabian; Jordan Gamble; Benjamin Blalock; Daniel Costinett
    2018 IEEE Applied Power Electronics Conference and Exposition (APEC)
    2018

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    In this work, a hybrid switched-capacitor/PWM converter is analyzed and designed for battery charging in mobile electronics. Operation of the converter is reviewed to construct a complete analytical loss model based on FET extracted parameters for an integrated circuit implementation. The model is validated with experimental results and compared with other converter topologies in the same application. The loss modeling is used to optimize the physical scaling of the power transistors to minimize total losses.

  • Ruirui Chen; Zheyu Zhang; Ren Ren; Jiahao Niu; Handong Gui; Fred Wang; Leon M. Tolbert; Daniel J. Costinett; Benjamin J. Blalock
    2018 IEEE Applied Power Electronics Conference and Exposition (APEC)
    2018

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    Understanding the CM inductor core saturation mechanism and reducing core flux density is critical for CM inductor design optimization. Instead of a time domain method, this paper introduces frequency domain spectrum concept for CM inductor core saturation analysis and design optimization, which will provide designers a better understanding of CM inductor design. First, both core permeability and converter modulation index's opposite influence on DM flux density and CM flux density are identified. Then, CM flux density is further investigated based on the spectrum concept. Three components in the CM inductor which may cause large CM flux density and core saturation are summarized: (1) switching frequency related components, (2) impedance resonance frequency related components, and (3) modulation frequency related components. Each component is investigated for CM flux density reduction and filter design optimization. A connecting AC and DC side midpoint with notch filter structure is proposed to reduce modulation frequency related components. Experiment results are presented to verify the proposed concept and method.

  • Jacob Dyer; Zheyu Zhang; Fred Wang; Daniel Costinett; Leon M. Tolbert; Benjamin J. Blalock
    2017 IEEE 5th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)
    2017

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    This paper introduces a dead-time optimization technique for a 2-level voltage source converter (VSC) using turn-off transition monitoring. Dead-time in a VSC impacts power quality, reliability, and efficiency. Silicon carbide (SiC) based VSCs are more sensitive to dead-time from increased reverse conduction losses and turn-off time variability with operating conditions and load characteristics. An online condition monitoring system for SiC devices has been developed using gate drive assist circuits and a micro-controller. It can be leveraged to monitor turn-off time and indicate the optimal dead-time in each switching cycle of any converter operation. It can also be used to specify load current polarity, which is needed for dead-time optimization in an inverter. This is an important distinction from other inverter dead-time elimination/optimization schemes as current around the zero current crossing is hard to accurately detect. A 1kW half-bridge inverter was assembled to test the turn-off time monitoring and dead-time optimization scheme. Results show 91% reduction in reverse conduction power losses in the SiC devices compared to a set dead-time of 500ns switching at 50 kHz.

  • Zheyu Zhang; Craig Timms; Jingyi Tang; Ruirui Chen; Jordan Sangid; Fred Wang; Leon M. Tolbert; Benjamin J. Blalock; Daniel J. Costinett
    2017 IEEE Applied Power Electronics Conference and Exposition (APEC)
    2017

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    Cooling a converter to low temperatures, e.g. using cryogenic cooling, can significantly improve the efficiency and density of a power conversion system. For the development and optimization of a cryogenically-cooled converter, an understanding of power semiconductor characteristics is critical. This paper focuses on the characterization of high-voltage, high-speed switching, power semiconductors at cryogenic temperature. First, the testing setup for cryogenic temperature characterization is introduced. Three testing setups are established for cryogenic switch characterization, including: 1) on-state resistance and forward voltage drop of the body diode, 2) leakage current and breakdown voltage, and 3) switching characteristics. For each testing set up, the corresponding testing configurations, hardware setups, and practical considerations are summarized. Additionally, the test results at cryogenic temperature are illustrated and analyzed for 650-V Si CoolMOS. It is then demonstrated that when the cryogenic temperature test results are compared to that of room temperature, the device performance varies significantly; for example: on-state resistance reduces by 63%, breakdown voltage drops by 31%, switching time decreases and switching energy loss decreases by 26%. Furthermore, the peak dv/dt during transient switching at cryogenic temperature exceeds 100 V/ns which is comparable to the emerging wide bandgap Gallium Nitride devices.

  • Wen Zhang; Zheyu Zhang; Fred Wang; Daniel Costinett; Leon Tolbert; Benjamin Blalock
    2017 IEEE Applied Power Electronics Conference and Exposition (APEC)
    2017

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    While fast switching brings many benefits, it also presents unwanted ringing during switching transient. In this paper, an increasing magnitude ringing phenomenon is observed during the MOSFET turn-off transient. The unusual phenomenon is replicated in simulation and it is found the MOSFET channel is turned on again after it is turned off. The major cause to this unexpected turn on is found to be common source inductance and a moderate 3 nH one in simulation replicates the severe self-turn-on ringing observed in experiment. This paper reveals the detrimental effect of common source inductance in fast switching. Therefore, Kelvin source connection in circuit and package design is strongly recommended.

  • Gabriel Gabian; Jordan Gamble; Benjamin Blalock; Daniel Costinett
    2017 IEEE 18th Workshop on Control and Modeling for Power Electronics (COMPEL)
    2017

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    This work presents an analytical model for integrated DC-DC converters at high currents. A loss model is constructed using parameters extracted from simulation or are available in the process manual and are scaled with the size of the device. The loss model is used to compare power converter implementations for varying on-chip size and power loss goals. Buck, 3-Level Buck, and Switched-Capacitor topologies are compared using this analytical model and then implemented in a commercial CMOS process. Validation of the constructed loss model is done through hardware measurements.

  • Zheyu Zhang; Fred Wang; Daniel J. Costinett; Leon M. Tolbert; Benjamin J. Blalock; Xuanlyu Wu
    2016 IEEE Energy Conversion Congress and Exposition (ECCE)
    2016

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    Junction temperature is a critical indicator for health condition monitoring of power devices. Concerning the reliability of emerging silicon carbide (SiC) power semiconductors due to immaturity of new material and packaging, junction temperature measurement becomes more significant and challenging, since SiC devices have low on-state resistance, fast switching speed, and high susceptibility to noise and parasitics in circuit implementations. This paper aims at developing a practical and cost-effective approach for online junction temperature monitoring of SiC devices using turn-off delay time as the thermo-sensitive electrical parameter (TSEP). The sensitivity is analyzed for fast switching SiC devices. A gate impedance regulation assist circuit is designed to improve the sensitivity by a factor of 60 and approach hundreds of ps/°C in the case study with little penalty of the power conversion performance. Also, an online monitoring system based on three gate assist circuits is developed to monitor the turn-off delay time in real time with the resolution within hundreds of ps. In the end, the micro-controller is capable of “reading” junction temperature during the converter operation with less than 0.5 °C measurement error. Two testing platforms for calibration and online junction temperature monitoring are constructed, and experimental results demonstrate the feasibility and accuracy of the proposed approach. Furthermore, the proposed gate assist circuits for sensitivity improvement and high resolution turn-off delay time measurement are transistor based and suitable for chip level integration.

  • Jacob Dyer; Zheyu Zhang; Fred Wang; Daniel Costinett; Leon M. Tolbert; Benjamin J. Blalock
    2016 IEEE 4th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)
    2016

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    Many intelligent gate drivers being designed for new state-of-the-art WBG devices typically only focus on protection and driving capabilities of the devices. This paper introduces an intelligent gate driver that incorporates online condition monitoring of the WBG devices. For this specific case study, three timing conditions (turn-off delay time, turn-off time, and voltage commutation time) of a silicon carbide (SiC) device are online monitored. This online monitoring system is achieved through gate driver assist circuits and a micro-controller. These conditions are then utilized to develop converter-level benefits for the converter application the SiC devices are placed in. Junction temperature monitoring is realized through turn-off delay time monitoring. Dead-time optimization is achieved with turn-off time monitoring. Dead-time compensation is obtained with turn-off time and voltage commutation time monitoring. The case study converter assembled for testing purposes is a half-bridge inverter using two SiC devices in a phase-leg configuration. All timing conditions are correctly monitored within reasonable difference of the actual condition time. A calibration curve was created to give a direct relationship between turn-off delay time and junction temperature. The half-bridge inverter can operate at 600 Vdc input and successfully obtain a junction temperature measurement through monitored td_off and the calibration curve. Furthermore, the proposed online condition monitoring system is transistor based and suitable for the chip level integration, enabling this practical approach to be cost-effective for end users.

  • Yang Xue; Zhiqiang Wang; Leon M. Tolbert; Benjamin J. Blalock
    2013 IEEE Transportation Electrification Conference and Expo (ITEC)
    2013

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    Buffer circuits are widely used in high-power inverters' gate drives to get enough driving current for power modules or power transistors in parallel. In this paper, designs of buffer circuits to boost the output current for a gate driver IC are investigated. Different buffer topologies are reviewed and their individual advantages and disadvantages analyzed. Based on the analysis, three topologies, specifically the BJT emitter follower, the two NFETs totem pole, and the CMOS buffer, are chosen for further study. Optimizations are performed on these three buffers by taking the driving capability, switching speed, circuit complexity, and cost into account. After that, a test setup is built, and the driving performance of the buffers is characterized and then compared experimentally with a commercial buffer IC with a rated current of 30 A. All three proposed buffers show better performance and lower cost, which verifies the feasibility and effectiveness of the proposed optimization methods. Double pulse test results indicate that the addition of a buffer stage makes the switching performance less sensitive to the load and can achieve significant performance improvement when large or parallel power switches are to be driven.

  • Zhiqiang Wang; Xiaojie Shi; Yang Xue; Leon M. Tolbert; Benjamin J. Blalock; Fred Wang
    2013 IEEE Energy Conversion Congress and Exposition
    2013

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    Overcurrent protection of silicon carbide (SiC) MOSFETs remains a challenge due to lack of practical knowledge. This paper presents two overcurrent protection methods to improve the reliability and overall cost of the SiC MOSFET based converter. First, a solid state circuit breaker (SSCB) composed primarily by a Si IGBT and a commercial gate driver IC is connected in series with the DC bus to detect and clear overcurrent faults. Second, the desaturation technique using a sensing diode to detect the drain-source voltage under overcurrent faults is implemented as well. The design considerations and potential issues of the protection methods are described and analyzed in detail. A phase-leg configuration based step-down converter is built to evaluate the performance of the proposed protection schemes under various conditions, considering variation of fault type, decoupling capacitance, protection circuit parameters, etc. Finally, a comparison is made in terms of fault response time, temperature dependent characteristics, and applications to help designers select a proper protection method.

  • Zhiqiang Wang; Xiaojie Shi; Leon M. Tolbert; Benjamin J. Blalock
    2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)
    2013

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    This paper addresses the issues of switching behavior of a high power insulated gate bipolar transistor (IGBT) that works in hard switching conditions. First, the voltage and current switching waveforms of IGBT modules are described for an IGBT phase-leg module with an inductive load, and the associated switching losses, reverse recovery current of free-wheeling diodes, voltage overshoot, and EMI noise are analyzed. Based on the analysis, an actively controlled gate drive circuit is proposed, which provides optimization of the fast driving for low switching losses and short switching time, and slow driving for low noise and switching stress. Compared to a conventional gate drive strategy, the proposed active gate driver (AGD) has the capability of reducing the switching losses, delay time, and Miller plateau duration effectively during both turn-on and turn-off transient. Experimental results verify the validity and effectiveness of the proposed gate driving method.

  • Zhiqiang Wang; Xiaojie Shi; Leon M. Tolbert; Benjamin J. Blalock; Madhu Chinthavali
    2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)
    2013

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    This paper presents a new active overcurrent protection scheme for IGBT modules based on the evaluation of fault current level by measuring the induced voltage across the stray inductance between the Kelvin emitter and power emitter of IGBT modules. Compared with the commonly used desaturation protection, it provides a fast and reliable detection of fault current without any blanking time. Once a short circuit is detected, a current limiting and clamping function is activated to dynamically suppress the transient peak current, thus reducing the considerable energetic and thermal stresses induced upon the power device. Subsequently, a soft turn-off mechanism is employed aiming to reduce surge voltages induced by stray inductance under high current falling rate. Moreover, the proposed method provides flexible protection modes, which overcome the interruption of converter operation in the event of momentary short circuits. The feasibility and effectiveness of the proposed approach have been validated by simulation results with real component models in Saber. A Double Pulse Tester (DPT) based experimental test setup further verifies the proposed protection scheme.

  • Fan Xu; Ben Guo; Zhuxian Xu; Leon M. Tolbert; Fred Wang; Ben J. Blalock
    2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)
    2013

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    This paper develops a liquid cooled high efficiency three-phase current source rectifier (CSR) for data center power supplies based on 400 Vdc architecture, using SiC MOSFETs and Schottky diodes. The 98.54% efficiency is achieved at full load. The rectifiers are paralleled to achieve high power ratings and system redundancy. The current balance and hot-swap of paralleled CSRs are realized in simulation using master-slave control. Moreover, an improved modulation scheme through adjustment of the freewheeling state is proposed and verified to effectively suppress the circulating current.

  • R. L. Greenwell; B. M. McCue; L. M. Tolbert; B. J. Blalock; S. K. Islam
    2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)
    2013

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    High-temperature integrated circuits fill a need in applications where there are obvious benefits to reduced thermal management or where circuitry is placed away from temperature extremes. Examples of these applications include aerospace, automotive, power generation, and well-logging. This work focuses on automotive applications in which the growing demand for hybrid electric vehicles (HEVs), Plug-in-hybrids (PHEVs), and Fuel-cell vehicles (FCVs) has increased the need for high-temperature electronics that can operate at the extreme ambient temperatures that exist under the hood of these vehicles, which can be in excess of 150°C. Silicon carbide (SiC) and other wide-bandgap power switches that can function at these temperature extremes are now entering the market. To take full advantage of their potential, high-temperature capable circuits that can also operate in these environments are required.

  • Weimin Zhang; Zhuxian Xu; Zheyu Zhang; Fred Wang; Leon M. Tolbert; Benjamin J. Blalock
    2013 IEEE Energy Conversion Congress and Exposition
    2013

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    In recent years, Si power MOSFET is approaching its performance limits, and Gallium Nitride (GaN) HEMT is getting mature. This paper evaluates the 600 V cascode GaN HEMT performance, and compares it with the state-of-the-art Si CoolMOS in LLC resonant converter. First, the static characterization of 600 V cascode GaN HEMT is described in different temperatures. The switching performance is tested by a double pulse tester to provide the turn-off loss reference to the design of LLC resonant converter. Second, a 400 V-12 V/300 W/1 MHz all-GaN-based converter with the 600 V cascode GaN HEMT is compared with a Si-based converter with the 600 V Si CoolMOS. The device output capacitance is a key factor in the design and loss analysis of LLC resonant converter. The design results show that the total GaN device loss of the all-GaN-based converter can be improved by 42% compared with the total Si device loss. Finally, both 400 V-12 V/300 W/1 MHz Si-based and GaN-based LLC resonant converter prototypes are tested and compared with waveforms and efficiency curves.

  • Yang Xue; Junjie Lu; Zhiqiang Wang; Leon M. Tolbert; Benjamin J. Blalock; Fred Wang
    2013 IEEE Energy Conversion Congress and Exposition
    2013

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    In high power applications of silicon carbide (SiC) MOSFETs where parallelism is employed, current unbalance can occur and affect the performance and reliability of the power devices. In this paper, factors which cause current unbalance in these devices are analyzed. Among them, the threshold voltage mismatch is identified as a major factor for dynamic current unbalance. The threshold distribution of SiC MOSFETs is investigated, and its effect on current balance is studied in experiments. Based on these analyses, an active current balancing scheme is proposed. It is able to sense the unbalanced current and eliminate it by actively controlling the gate drive signal to each device. The features of fine time resolution and low complexity make this scheme attractive to a wide variety of wide-band-gap device applications. Experimental and simulation results verify the feasibility and effectiveness of the proposed scheme.

  • Zheyu Zhang; Fred Wang; Leon M. Tolbert; Benjamin J. Blalock
    2013 IEEE Energy Conversion Congress and Exposition
    2013

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    In a phase-leg configuration, the high switching-speed performance of silicon carbide (SiC) devices is limited by the interaction between the upper and lower devices during the switching transient (cross talk), leading to additional switching losses and overstress of the power devices. To utilize the full potential of fast SiC devices, this paper proposes a gate assist circuit using two auxiliary transistors and a diode to eliminate cross talk. Based on CMF20120D SiC MOSFETs, the experimental results show that this gate assist methodology is effective to suppress cross talk under different operating conditions, enabling turn-on switching losses reduction by up to 19.6%, and negative spurious gate voltage minimization within the maximum allowable negative gate voltage of the power devices without the penalty of reduced switching speed. Moreover, in comparison to the conventional gate driver with -2 V turn-off gate voltage, this gate assist circuit without a negative isolated power supply is more effective in enhancing the switching behavior of power devices in a phase-leg. Accordingly, the proposed gate assist circuit is a cost-effective solution for cross talk suppression.

  • Weimin Zhang; Yu Long; Yutian Cui; Fred Wang; Leon M. Tolbert; Benjamin J. Blalock; Stephan Henning; Justin Moses; Robert Dean
    2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)
    2013

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    Transformer loss, comprised of core loss and winding loss, is a critical part in the LLC resonant converter loss. Different winding structures lead to different winding losses and winding capacitances. High winding capacitance will impact the design of the LLC resonant converter. The reason is that high winding capacitance means high winding charge, which must be moved during the dead time to realize the device zero voltage turn-on. As a result, the dead time and magnetizing current will be changed, and the converter loss will be changed as well. This paper first discusses the transformer loss including core loss and winding loss. Then, four different winding structures are analyzed based on a selected core, which show the decrease of AC resistance and the increase of winding capacitance. After that, the winding capacitance model is discussed generally. Finally, the impact of winding capacitance on the design and performance of LLC resonant converter is studied. Two 48 V-12 V, 300 W Si-based and GaN-based LLC resonant converters are designed as platforms to evaluate the impact of winding capacitance. The results indicate that the GaN-based converter is well suited to the transformer with lowest winding loss but highest winding capacitance, since the GaN device's output capacitance is much lower than that of the Si device.

  • Zheyu Zhang; Fred Wang; Leon M. Tolbert; Benjamin J. Blalock
    2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)
    2013

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    Silicon Carbide (SiC) power devices have inherent capability for fast switching. However, in a phase-leg configuration, high dv/dt will worsen the interference between the two devices during a switching transient (i.e., cross talk), leading to slower switching speed, excessive switching losses, and overstress of power devices. Unfortunately, due to intrinsic properties, such as low threshold voltage, low maximum allowable negative gate voltage, and large internal gate resistance, SiC power devices are easily affected by cross talk. This paper proposes a novel gate assist circuit using an auxiliary transistor in series with a capacitor to mitigate cross talk. Based on CMF20120D SiC MOSFETs, the experimental results show that the new gate assist circuit is capable of reducing the turn-on switching loss up to 19.3%, and suppress the negative spurious gate voltage within the maximum allowable negative gate voltage without the penalty of further decreasing the device switching speed. Moreover, in comparison to a conventional gate drive with -2 V turn-off gate voltage, this gate assist circuit without negative isolated power supply is more effective in improving the switching behavior of power devices in a phase-leg. The proposed gate assist circuit is a cost-effective solution for cross talk mitigation.

  • Fan Xu; Ben Guo; Zhuxian Xu; Leon M. Tolbert; Fred Wang; Ben J. Blalock
    2013 IEEE Energy Conversion Congress and Exposition
    2013

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    Three-phase current source rectifier (CSR) is a promising solution for power supply systems as the buck-type power factor correction converter. By converter paralleling, high power rating and system redundancy can be achieved. However, asymmetrical distribution of load current among converter modules may occur, which can increase power loss or even damage devices. This paper presents the DC-link current control scheme for paralleled current source rectifiers to balance the output currents. Using a master-slave control, the balanced output current distribution and system redundancy are implemented. By correcting zero state duration based on modulation scheme, the circulating current is suppressed without introducing additional power losses, and both positive and negative DC-link currents are balanced.

  • Ben Guo; Fan Xu; Zheyu Zhang; Zhuxian Xu; Fred Wang; Leon M. Tolbert; Benjamin J. Blalock
    2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)
    2013

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    An overlap time for two commutating switches is necessary to prevent current interruption in a three-phase buck rectifier, but it may cause input current distortion. In this paper, a modified pulse-based compensation method is proposed to compensate for the overlap time. In addition to the traditional method which places the overlap time based on the voltage polarity, this new method first minimizes the overlap time to reduce its effect and then compensates the pulse width according to the sampled voltage and current. It is verified by experiments that the proposed method has better performance than the traditional method, especially when the line-to-line voltage crosses zero. Another distortion comes from the irregular pulse distribution when two sectors change in a 12-sector space vector PWM. This paper proposes two compensation methods for that scenario as well, compensating the duty cycle and increasing switching frequency near the boundaries of two sectors. It is shown through experiments that both methods can reduce the input current distortion in the buck rectifier.

  • Fan Xu; Ben Guo; Leon M. Tolbert; Fred Wang; Benjamin J. Blalock
    2012 IEEE Energy Conversion Congress and Exposition (ECCE)
    2012

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    This paper presents a 7.5 kW liquid cooled three-phase buck rectifier which will be used as the front-end rectifier in 400 Vdc architecture data center power supply systems. SiC MOSFETs and SiC Schottky barrier diodes (SBDs) are used in parallel to obtain low power semiconductor losses. Input and output filters are designed and inductor core material is compared to reduce passive component losses. A low-loss modulation scheme and 28 kHz switching frequency are selected to optimize the converter design for efficiency. A prototype of the proposed rectifier is constructed and tested, and greater than 98.5% efficiency is obtained at full load.

  • Fan Xu; Ben Guo; Leon M. Tolbert; Fred Wang; Ben J. Blalock
    2012 Twenty-Seventh Annual IEEE Applied Power Electronics Conference and Exposition (APEC)
    2012

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    This paper presents the characteristics of a 1200 V, 33 A SiC MOSFET and a 1200 V, 60 A SiC schottky barrier diode (SBD). The switching characteristics of the devices are tested by a double pulse test (DPT) based on a current-source structure at voltage levels up to 680 V and current up to 20 A. In addition, based on these devices, a 7.5 kW, three-phase buck rectifier for a 400 Vdc architecture data center power supply is designed. The total loss of this rectifier is calculated full load. The results show that the SiC based buck rectifier can obtain low power loss and smaller weight and volume than a Si based rectifier.

  • Zheyu Zhang; Weimin Zhang; Fred Wang; Leon M. Tolbert; Benjamin J. Blalock
    2012 IEEE Energy Conversion Congress and Exposition (ECCE)
    2012

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    Advanced power semiconductor devices, especially wide band-gap devices, have inherent capability for fast switching. However, due to the limitation of gate driver capability and the interaction between two devices in a phase-leg during switching transient (cross talk), the switching speed is slower than expected in practical use. This paper focuses on identifying the key limiting factors for switching speed. The results provide the basis for improving gate drivers, eliminating interference, and boosting switching speed. Based on the EPC2001 Gallium Nitride transistor, both simulation and experimental results verify that the limiting factors in the gate loop include the pull-up (-down) resistance of gate driver, rise (fall) time and amplitude of gate driver output voltage; among these the rise (fall) time plays the primary role. Another important limiting factor of device switching speed is the spurious gate voltage induced by cross talk between two switches in a phase-leg. This induced gate voltage is not only determined by the switch speed, but also depends on the gate loop impedance, junction capacitance, and operating conditions of the complementary device.

  • Zhiqiang Wang; Xiaojie Shi; Yang Xue; Leon M. Tolbert; Benjamin J. Blalock
    2012 IEEE 13th Workshop on Control and Modeling for Power Electronics (COMPEL)
    2012

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    The issues of turn-on performance of a high power insulated gate bipolar transistor (IGBT) that works in hard switching conditions are discussed in detail. First, the turn-on delay time, switching loss, reverse recovery current of the associated free-wheeling diode, and EMI noise are analyzed for an IGBT phase-leg module with an inductive load. Based on the analysis, a novel gate drive circuit combining the slow drive requirements to minimize noise and switching stress, and the fast drive requirements for high-speed switching and low switching energy loss is proposed. Compared to a conventional gate drive circuit, the proposed gate driving strategy is able to effectively reduce the switching loss, delay time, and total switching time during the turn-on transient while the turn-off performance remains unchanged. Simulation and experimental results verify the validity and effectiveness of the proposed gate driving method.

  • Chandradevi Ulaganathan; Benjamin J. Blalock; Jeremy Holleman; Charles L. Britton
    2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)
    2012

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    An ultra-low voltage, self-starting, switched-capacitor based charge pump is proposed for energy harvesting applications. The integrated linear charge pump topology presented in this work has been optimized for low-voltage start-up. The control signals for the charge-transfer switches (CTS), generated using two clock phases, reduce reverse currents and thus improve the efficiency of the converter. Adiabatic switching techniques have been employed to reduce the switching losses associated with the CTS gate control. This design has been implemented in a 130-nm CMOS process. Simulation results demonstrate a low startup voltage of 125 mV with efficiency of 62 % for a static current load of 0.1 μA.

  • Chandradevi Ulaganathan; Charles L. Britton; Jeremy Holleman; Benjamin J. Blalock
    Proceedings of the 19th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2012
    2012

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    A novel charge-recycling scheme has been designed and implemented to demonstrate the feasibility of operating digital circuits using the charge scavenged from the leakage and dynamic load currents inherent to digital logic. The proposed scheme uses capacitors to efficiently recover the ground-bound charge and to subsequently boost the capacitor voltage to power up the source circuit. This recycling methodology has been implemented on a 12-bit Gray-code counter within a 12-bit multi-channel Wilkinson ADC. The circuit has been designed in 0.5μm BiCMOS and in 90nm CMOS processes. SPICE simulation results reveal a 46-53% average reduction in the energy consumption of the counter. The total energy savings including the control generation aggregates to an average of 26-34%.

  • Weimin Zhang; Yu Long; Zheyu Zhang; Fred Wang; Leon M. Tolbert; Benjamin J. Blalock; Stephan Henning; Chris Wilson; Robert Dean
    2012 IEEE Energy Conversion Congress and Exposition (ECCE)
    2012

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    Silicon Power MOSFETs, with more than thirty years of development, are widely accepted and applied in power converters. Gallium Nitride (GaN) power devices are commercially available in recent years [1], but the device performance and application have not been fully developed. In this paper, GaN devices are compared with state-of-art Si devices to evaluate the device impact on soft-switching DC-DC converters, like LLC resonant converter. The analytical approach of device selection and comparison are conducted and loss related device parameters are derived. Total device losses are compared between Si and GaN based on these parameters. GaN shows less loss compared with Si, yielding approximately a 20% reduction of total device loss. Two 300 W, 500 kHz, 48 V-12 V GaN-based and Si-based converter prototypes are built and tested. Since the body diode forward voltage drop of GaN device is high, the dead time is adjusted to minimize the body diode conduction period. The peak efficiency of the GaN-based converter is 97.5%, and the full load efficiency is 96.1%, which is around 0.3% higher than the Si-based converter at full load. The test results shows that, although GaN device has lower loss, the improvement of converter efficiency is not much. The reason is that the transformer loss accounts for more than 60% of total loss. Therefore, a transformer which fits the GaN device characteristic need to be further investigated.

  • R. L. Greenwell; B. M. McCue; L. Zuo; M. A. Huque; L. M. Tolbert; B. J. Blalock; S. K. Islam
    2011 Twenty-Sixth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)
    2011

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    The growing demand for hybrid electric vehicles (HEVs) has increased the need for high-temperature electronics that can operate at the extreme temperatures that exist under the hood. This paper presents a high-voltage, high-temperature SOI-based gate driver for SiC FET switches. The gate driver is designed and implemented on a 0.8-micron BCD on SOI process. This gate driver chip is intended to drive SiC power FETs for DC-DC converters and traction drives in HEVs. To this end, the gate driver IC has been successfully tested up to 200°C. Successful operation of the circuit at this temperature with minimal or no heat sink, and without liquid cooling, will help to achieve higher power-to-volume as well as power-to-weight ratios for the power electronics modules in HEVs.

  • Xueyang Geng; Desheng Ma; Zhenqi Chen; Fa Dai; John D. Cressler; Jeremy A. Yaeger; Mohammad M. Mojarradi; Alan Mantooth; Benjamin J. Blalock; Richard W. Berger
    2011 IEEE Bipolar/BiCMOS Circuits and Technology Meeting
    2011

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    High speed channel (HSC) resistive sensor interface is an analog sampling channel designed for measuring the resistance variations with data rate at 5 kHz. It measures the external resistance variation and digitizes the received signal using a 12-bit analog to digital converter (ADC). The HSC includes a Wheatstone bridge with programmable configurations, a high voltage cap stack sampler, a 6th order Butterworth switching capacitor filter, and a continuous time variable gain amplifier (VGA). An 8-bit voltage mode calibration digital to analog converter (DAC) is used to calibrate the common mode voltage level. An 8-bit current mode stimulus DAC is used to provide the current source to the Wheatstone bridge through a high voltage current mirror. With radiation hardening by design (RHBD), the HSC is implemented in a 0.5 μm SiGe BiCMOS technology for applications in aerospace environment under extreme temperature, radiation, pressure and vibration.

  • Sazia A. Eliza; Syed K. Islam; Touhidur Rahman; Nora D. Bull; Benjamin J. Blalock; Larry R. Baylor; Milton N. Ericson; Walter L. Gardner
    International Vacuum Nanoelectronics Conference
    2010

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    This paper presents dose control electronics and a digital addressing method for the vertically aligned carbon nanofiber (VACNF) based massively parallel maskless e-beam lithography system. The Digital Electrostatically focused e-beam Array direct-write Lithography (DEAL) developed by our research group in Oak Ridge National Laboratory incorporates digitally addressable field emission arrays (DAFEAs) of the VACNFs which function as the lithography heads during the exposure of the resist. A logic and memory control circuit (LMC) and a dose control circuit (DCC) have been designed to write a desired pattern and control the dose of electrons, respectively. This paper summarizes our previous works on different versions of the DCCs designed and optimized in the effort of obtaining a fixed and optimum dosage with the smaller circuit area.

  • Xiaoyan Yu; Ethan Farquhar; Ben Blalock
    2010 53rd IEEE International Midwest Symposium on Circuits and Systems
    2010

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    This work describes a novel frequency based current to digital converter, which is fully realizable on a single chip. This project affords an extremely low power converter technology that is also very space efficient. The converter is completely asynchronous which yields ultra-low power during standby operation (approximately 5 nW). The input current range is programmable, and the minimum detectable current could reach the range of picoampere or even lower. System structure, operational principle, and chip test results are given in this paper.

  • Ryan M. Diestelhorst; Steven Finn; Laleh Najafizadeh; Desheng Ma; Pengfei Xi; Chandradevi Ulaganathan; John D. Cressler; Ben Blalock; Foster Dai; Alan Mantooth; Linda Del Castillo; Mohammad Mojarradi; Richard Berger
    2010 IEEE Aerospace Conference
    2010

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    This paper describes the design, implementation, and characterization of a monolithic charge amplification channel for use as a piezoelectric sensor front-end in extreme environment applications. 12The design leverages a 50 GHz peak-fT SiGe BiCMOS technology platform to achieve functionality across a wide-temperature range from -180°C to 120°C. As part of a much larger remote electronics unit, the channel is specified to amplify piezoelectric transducer signals with frequencies up to 5 kHz and amplitudes as low as 200 pC. Intended for use in lunar surface systems, the application requires the capability to absorb up to 100 krad(SiO2) of total ionizing dose (consistent with a typical lunar mission cycle) and be hardened against latch-up effects that cause system failure in a heavy ion radiation environment. Preliminary characterization of the channel shows the desired integration of an AC current input, programmable gain, and effective filtering at three distinct cutoff frequencies.

  • W. J. McNeil; S. L. Bellinger; T. C. Unruh; C. M. Henderson; P. B. Ugorowski; W. L. Dunn; R. D. Taylor; B. J. Blalock; C. L. Britton; D. S. McGregor
    2009 IEEE Nuclear Science Symposium Conference Record (NSS/MIC)
    2009

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    A 1024-channel pixel array has been constructed utilizing the perforated diode neutron detector design currently produced at Kansas State University. In this design a single pixel consists of a pn-junction diode fabricated around a single trench 4 cm long, 30 microns wide and 100 microns deep. The trench is filled with 6LiF powder to provide conversion of neutrons to energetic charged particles which can be captured in the diode depletion region. A pitch of 100 microns between pixels has been achieved and less than 120 micron spatial resolution has been demonstrated experimentally with a 32-channel prototype in previous work. Also, the first array demonstrated 12% thermal neutron counting efficiency. The 1024-channel array was produced by tiling 16 chips side-by-side, each containing 64 pixels. Signal processing is handled by 16 PATARA chips for amplification and thresholds, developed at University of Tennessee. The entire board assembly and digital communications to PC were handled by the KSU Electronics Design Laboratory utilizing a PCI card developed at ORNL.

  • A. G. Antonacci; J. L. Britton; S. C. Bunch; M. N. Ericson; B. J. Blalock; R. Chun; R. Greenwell; D. S. McGregor; L. Crow; L. Clonts; T. Sobering; R. Taylor; W. McNeil; S. Bellinger; C. L. Britton
    2009 IEEE Nuclear Science Symposium Conference Record (NSS/MIC)
    2009

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    The High Efficiency Neutron Detector Array (HENDA) project at the Spallation Neutron Source (SNS), Oak Ridge Tennessee, has driven the need for state of the art radiation detector readout electronics. Readout electronics of this class must support multi-channel inputs while providing a high level of integration and precision. The Patara II ASIC targets this need by integrating a charge sensitive front end followed by analog and digital signal processing that supports the connectivity of 64 detectors. A monolithic biasing system and digital programmability was integrated in order to reduce the amount of required external components on the end system motherboard.

  • Linda Del Castillo; Alina Moussessian; Mohammad Mojarradi; Elizabeth Kolawa; R. Wayne Johnson; Benjamin J. Blalock
    2009 IEEE Aerospace conference
    2009

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    This work describes the development and evaluation of advanced technologies for the integration of electronic die within membrane polymers. Specifically, investigators thinned silicon die, electrically connecting them with circuits on flexible liquid crystal polymer (LCP), using gold thermo-compression flip chip bonding, and embedding them within the material. Daisy chain LCP assemblies were thermal cycled from -135 to +85degC (Mars surface conditions for motor control electronics). The LCP assembly method was further utilized to embed an operational amplifier designed for operation within the Mars surface ambient. The embedded op-amp assembly was evaluated with respect to the influence of temperature on the operational characteristics of the device. Applications for this technology range from multifunctional, large area, flexible membrane structures to small-scale, flexible circuits that can be fit into tight spaces for flex to fit applications.

  • S. K. Islam; S. A. Eliza; N. D. Bull; T. Rahman; B. Blalock; L. R. Baylor; M. N. Ericson; W. L. Gardner
    2009 22nd International Vacuum Nanoelectronics Conference
    2009

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    This paper presents a precision control circuit for the emission of desired number of electrons from vertically aligned carbon nanofibers (VACNFs) for the realization of a massively parallel maskless e-beam lithography system.The digitally addressable field emission arrays (DAFEAs) of the VACNFs function as the lithography heads for massively parallel e-beam exposure of resist eliminating the cost of photomasks.

  • Vinesh Sukumar; Fadi Nessir Zghoul; Mahmoud Alahmad; Herbert Hess; Kevin Buck; Harry Li; Dave Cox; Jeremy Jackson; Stephen Terry; Ben Blalock; M. M. Mojarradi; W. C. West; J. F. Whitacre
    2009 IEEE International Symposium on Industrial Electronics
    2009

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    Integrated microbatteries are being currently developed to act as a ldquomicropowerrdquo source in microsatellites. They help provide localized current capacities or embedded power supplies at the chip level, for space exploration. These power cells are designed to be rechargeable. This research paper aims at presenting charging these power cells using pulsing algorithms developed at MRCI with an on chip pulse charger controller.

  • M. A Huque; S. K. Islam; B. J. Blalock; C. Su; R. Vijayaraghavan; L M. Tolbert
    2008 IEEE International Symposium on Industrial Electronics
    2008

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    In recent years increasing demand for hybrid electric vehicle has generated the need for reliable and low-cost high-temperature electronics which can operate at the extreme temperatures that exists under the hood. A high-voltage and high-temperature gate-driver integrated circuit for SiC FET switches is designed and implemented in a 0.8-micron Silicon-on-Insulator high-voltage process. First prototype chip has been successfully tested up to 200degC ambient temperature without any heat sink or cooling mechanism. This gate-driver chip is intended to drive SiC power FETs of the DC-DC converters in a hybrid electric vehicle. The converter modules along with the gate-driver chip will be placed very close to the engine where the temperature can reach up to 175degC. Successful operation of the chip at this temperature with or without minimal heat sink and without liquid cooling will help achieve greater power-to-volume as well as power-to-weight ratios for the power electronics module. A second prototype has also been designed with more robust features.

  • N. D. Bull; S. K. Islam; B. J. Blalock; S. Ripp; S. Moser; G. S. Sayler
    2008 IEEE International Symposium on Circuits and Systems
    2008

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    A bioluminescent bioreporter integrated circuit (BBIC) biosensor for environmental monitoring is presented. The bioluminescent bioreporters are bacteria that can be genetically altered to achieve bioluminescence when in contact with a targeted substance. The bioreporters are placed on a microluminometer. The microluminometer includes integrated photodiodes and signal processing circuits and is realized in a standard CMOS process. The BBIC can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescene 5RL bacteria and provides a integrated biosensor platform for environmental and food/water safety monitoring.

  • Neena Nambiar; Benjamin J. Blalock; Milton N. Ericson
    2008 International Conference on Signals and Electronic Systems
    2008

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    A current mode multi-channel ADC has been designed in a 0.5-mum bulk CMOS process. The ADC is capable of supporting multiple channels with an input current range of 10 muA to 80 muA. The main blocks in the ADC include a current ramp generator, multiple current comparators and a 12-bit Gray code counter. Simulation results are presented that predict 12-bit resolution, sampling rates up to 20 Ksps, and a per-channel power consumption of less than 2 mW using a Wilkinson architecture with 8 channels.

  • C. Ulaganathan; N. Nambiar; B. Prothro; R. Greenwell; S. Chen; B. J. Blalock; C. L. Britton; M. N. Ericson; H. Hoang; R. Broughton; K. Cornett; G. Fu; H. A. Mantooth; J. D. Cressler; R. W. Berger
    2008 51st Midwest Symposium on Circuits and Systems
    2008

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    A instrumentation channel has been designed, implemented and tested in a 0.5-mum SiGe BiCMOS process. The circuit features a reconfigurable Wheatstone bridge network that interfaces a range of external sensors to signal processing circuits. Also, analog sampling has been implemented in the channel using a flying capacitor configuration. Measurement results show the instrumentation channel supports input signals up to 200 Hz.

  • Yuan Chen; Mohammad Mojaradi; Nazeeh Aranki; Ehsan Kazemian; Robert Grogan; Elizabeth Kolawa; Benjamin Blalock; Robert Greenwell; Lynett Westergard
    2008 IEEE Aerospace Conference
    2008

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    In this paper, we present a methodology for design and qualification of microelectronics for low temperature applications, which has enabled the successful infusion of a custom designed Operational Amplifier into flight mission. The Op-Amp was designed to target a wide temperature range of -150degC to +125degC for at least 5 years operation for Mars Mission. The design and qualification methodology developed have provided the critical path for the technology infusion.

  • Zuoliang Ning; Benjamin J. Blalock; M. Nance Ericson; John Oliver; Richard Van Berg; Paul O'Connor; Charles L. Britton
    2008 51st Midwest Symposium on Circuits and Systems
    2008

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    A Sensor Control Chip (SCC) that can drive a 20 V adjustable output voltage swing and a maximum output current of 100 mA has been developed to provide the required clock and bias signals for the Large Synoptic Survey Telescopepsilas CCD imagers. The prototype chip has been fabricated in a 0.8-mum BCD-SOI process, and is designed to operate down to 150 K. The circuit consists of current steering DACs followed by transimpedence operational amplifiers to control the rail voltages of the clock signals and bias voltages. The clocks are input to the SCC through LVDS receivers and converted internally to the required amplitude for driving the CCD. Design techniques will be presented along with room temperature and operational temperature test results obtained from prototype chips.

  • Richard Berger; Laura Burcin; David Hutcheson; Jennifer Koehler; Marla Lassa; Myrna Milliser; David Moser; Dan Stanley; Randy Zeger; Ben Blalock; Mark Hale
    2008 IEEE Aerospace Conference
    2008

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    A highly integrated system-on-chip is currently in development. Based on the flight-proven RAD6000TM microprocessor, this mixed-signal microcontroller supports a wide variety of standard digital interfaces commonly used in spacecraft avionics. Multiple analog input and output channels are also provided.

  • Zuoliang Ning; Benjamin J. Blalock; M. Nance Ericson; John Oliver; Richard Van Berg; Paul O'Connor; Charles L. Britton
    2008 IEEE Nuclear Science Symposium Conference Record
    2008

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    A Sensor Control Chip (SCC) that can drive a 20 V adjustable output voltage swing and a maximum output current of 100 mA has been developed to provide the required clock and bias signals for the Large Synoptic Survey Telescope’s CCD imagers. The prototype chip has been fabricated in a 0.8-µm BCD-SOI process, and is designed to operate down to 175K. The circuit consists of current steering DACs followed by transimpedence operational amplifiers to control the rail voltages of the clock signals and bias voltages. The clocks are input to the SCC through LVDS receivers and converted internally to the required amplitude for driving the CCD. Design techniques will be presented along with room temperature and operational temperature test results obtained from prototype chips.

  • Yuan Chen; Mohammad Mojarradi; Lynett Westergard; Nazeeh Aranki; Elizabeth Kolawa; Benjamin Blalock
    2008 IEEE International Reliability Physics Symposium
    2008

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    A case study is presented applying a design-for-reliability methodology to design, fabricate and qualify a quad rail-to-rail operational amplifier for the wide temperature range operation of -140degC to +125degC to for space applications. The design-for-reliability approach was developed and implemented from transistor level up to board/system level, along with a comprehensive qualification procedure for the wide temperature range. The quad op-amp is used for a flight mission and available from a commercial production line.

  • N. Nambiar; C. Ulaganathan; S. Chen; M. Hale; A. Antonacci; B. J. Blalock; C. L. Britton; M. N. Ericson
    2008 51st Midwest Symposium on Circuits and Systems
    2008

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    A multichannel low power analog-to-digital converter (ADC) designed, fabricated and tested in 0.5-mum Silicon Germanium BiCMOS process is reported. The 12-bit ADC features 8 input channels, each having a 10-Ksps sampling rate and an input voltage range of 1.2 V. The ADC architecture, comprised of a ramp generator, comparators, and a Gray code counter, is discussed along with design details of the primary blocks. Measurement data shows a differential nonlinearity of less than 0.5 LSB and an approximate accuracy of 10 bits.

  • Richard Berger; Raymond Garbos; John Cressler; Mohammad Mojarradi; Leora Peltz; Ben Blalock; Wayne Johnson; Guofu Niu; Foster Dai; Alan Mantooth; Jim Holmes; Mike Alles; Patrick McClusky
    2008 IEEE Aerospace Conference
    2008

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    A data acquisition system is being developed for use on the NASA Lunar-Mars series of missions. The unit will accept inputs from multiple types of sensors, employing three types of input channels that each incorporate programmable elements to accommodate a wider variety of input signals. Based in part on a subsystem called the remote health node (RHN) that was originally developed during the 1990s for use on the now-defunct NASA X-33 "space plane", the remote electronics unit (REU) is being developed using a 0.5 micron silicon germanium (SiGe) BiCMOS technology from IBM with a circuit library that has been designed to operate normally across a temperature range from -180 degrees C up through +125 degrees C.

  • M. A Huque; R. Vijayaraghavan; M. Zhang; B. J. Blalock; L M. Tolbert; S. K. Islam
    2007 IEEE Power Electronics Specialists Conference
    2007

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    A high-voltage and high-temperature gate-driver chip for SiC FET switches is designed and fabricated using 0.8- micron, 2-poly and 3-metal BCD on SOI process. It can generate output voltage swing from -5 V to 30 V and can operate up to 175degC ambient temperature. This gate-driver chip is intended to drive SiC power FETs in DC-DC converters in a hybrid electric vehicle. The converter modules along with the gate-driver chip will be placed very close to the engine where the temperature can reach up to 175degC. Successful operation of the chip at this temperature without heat sink and liquid cooling will help to achieve greater power-to-volume as well as power-to-weight ratios for the power electronics module. Initial test results presented in this paper also validate the simulation.

  • W. J. McNeil; S. L. Bellinger; B. J. Blalock; C. L. Britton; J. L. Britton; S. C. Bunch; S. A. Cowley; C. M. Henderson; T. J. Sobering; R. D. Taylor; D. S. McGregor
    2007 IEEE Nuclear Science Symposium Conference Record
    2007

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    A. first generation 120 micron pitch pixel array system for neutron detection using the PATARA amplifier chip was assembled and tested. The pixel array was tested for neutron response and spatial resolution. Pulses from the PATARA were observed at 0.5 V in height and 500 ns wide from neutron interactions. The spatial resolution of the array was determined to be 119 micrometers. Leakage current tests and alpha particle irradiation tests were conducted for a second generation prototype silicon sensor with 175 micrometer deep perforated trench structures in each pixel. The second generation sensor incorporates several design improvements to ease fabrication.

  • Laleh Najafizadeh; Akil K. Sutton; Bongim Jun; John D. Cressler; Tuan Vo; Omeed Momeni; Mohammad Mojarradi; Chandradevi Ulaganathan; Suheng Chen; Benjamin J. Blalock; Yuan Yao; Xuefeng Yu; Foster Dai; Paul W. Marshall; Cheryl J. Marshall
    2007 9th European Conference on Radiation and Its Effects on Components and Systems
    2007

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    The effects of proton irradiation on the performance of key devices and mixed-signal circuits fabricated in a SiGe BiCMOS IC design platform and intended for emerging lunar missions are presented. High-voltage (HV) transistors, SiGe bandgap reference (BGR) circuits, a general-purpose high input impedance operational amplifier (op amp), and a 12-bit digital-to-analog converter (DAC) are investigated. The circuits were designed and implemented in a first-generation SiGe BiCMOS technology and were irradiated with 63 MeV protons. The degradation due to proton fluence in each device and circuit was found to be minor, suggesting that SiGe HBT BiCMOS technology could be a robust platform for building electronic components intended for operation under extreme environments.

  • S. A. Eliza; S. K. Islam; T. Rahman; R. Vijayaraghavan; T. Grundman; B. Blalock; S. J. Randolph; L. R. Baylor; T. S. Bigelow; W. L. Gardner; M. N. Ericson; J. A. Moore
    2007 International Semiconductor Device Research Symposium
    2007

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    Field emission (FE) of electrons from nanostructured graphitic carbon-based materials has been an area of intense investigation in recent years. Each field emitting device has control gates and an electron emitting cathode, which emits electron when a sufficient voltage is applied at the gate electrode. Recently, a technique for fabricating gated cathode structures that uses a single in situ grown vertically aligned carbon nanofiber (VACNF) as a FE element has been reported. This paper presents digitally addressable VACNFs for implementation of massively parallel maskless lithography.

  • Jamie S. Laird; Leif Scheik; Testuo Miyahira; Mohammad M. Mojarradi; Benjamin Blalock; Robert Greenwell; Gyorgy Vizkelethy; Philippe C. Adell; Farokh Irom; Barney Doyle
    2007 9th European Conference on Radiation and Its Effects on Components and Systems
    2007

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    The next generations of Martian rovers are to examine the polar regions where temperatures are extremely low and the absence of an earth-like atmosphere results in a plethora of radiation issues including Analogue Single Event Transients. To this end, a radiation-hardened, temperature compensated CMOS Single-On-Insulator operational amplifier was designed and fabricated using Honeywell's SOI V process. Broad beam heavy-ion tests at the University of Texas A&M were performed to ascertain the duration and severity of any SET's for low and high gain application. Ambiguity regarding the location of transient formation required the use of an ion microbeam to confirm a region of major concern in the internal bias circuitry.

  • T. Rahman; S. K. Islam; R. Vijayaraghavan; T. Gundman; S. A. Eliza; A. B. M. I. Hossain; B. Blalock; L. R. Baylor; T. S. Bigelow; M. N. Ericson; W. L. Gardner; J. A. Moore; S. J. Randolph
    2006 19th International Vacuum Nanoelectronics Conference
    2006

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    This paper discusses the complete integration of the prototype digital electrostatic focused e-beam array direct-write lithography (DEAL) device with the dose control circuitry (DCC). The DCC regulates charge emission from the vertically aligned carbon nanofibers (VACNFs) and prevents resists from being over exposed during the e-beam lithography process. The emission of electrons from the VACNF tip requires relatively high voltage. The I-V characteristic of a typical VACNF based device is presented with threshold voltage of ~75 V. The DCC built using a standard 5 V digital CMOS process cannot handle such voltage levels

  • K. Akarvardar; B. Blalock; S. Chen; S. Cristoloveanu; P. Gentil; M. M. Mojarradi
    2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings
    2006

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    Novel G4-FET based logic-circuits (adjustable-threshold inverter, real-time reconfigurable logic gates and DRAM cell) are experimentally demonstrated. The independent action of the four gates helps minimize the required transistor count per logic function while enhancing design flexibility

  • Laleh Najafizadeh; Chendong Zhu; Ramkumar Krithivasan; John D. Cressler; Yan Cui; Guofu Niu; Suheng Chen; Chandradevi Ulaganathan; Benjamin J. Blalock; Alvin J. Joseph
    2006 Bipolar/BiCMOS Circuits and Technology Meeting
    2006

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    We present the first investigation of the optimal implementation of SiGe BiCMOS precision voltage references for extreme temperature range applications (+120 degC to -180 degC and below). We have developed and fabricated two unique Ge profiles optimized specifically for cryogenic operation, and for the first time compare the impact of Ge profile shape on precision voltage reference performance down to -180 degC. Our best case reference achieves a 28.1 ppm/ degC temperature coefficient over +27 degC to -180 degC, more than adequate for the intended lunar electronics applications

  • K. Akarvardar; S. Chen; J. Vandersand; B. Blalock; R. Schrimpf; B. Prothro; C. Britton; S. Cristoloveanu; P. Gentil1; M. M. Mojarradi
    2006 IEEE international SOI Conferencee Proceedings
    2006

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    A novel voltage-controlled negative differential resistance device, using complementary SOI four-gate transistors (G4-FETs) is presented. Innovative LC oscillator and Schmitt trigger circuits based on the G4-FET NDR device are experimentally demonstrated

  • J. L. Britton; S. C. Bunch; C. L. Britton; B. J. Blalock; D. S. McGregor; L. Crow
    2006 IEEE Nuclear Science Symposium Conference Record
    2006

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    A prototype neutron detector array has been developed for the Spallation Neutron Source (SNS). The High Efficiency Neutron Detector Array (HENDA) will be the highest spatial resolution neutron detecting linear array available anywhere. The front-end electronics have been developed on a prototype chip, Patara, from a TSMC 0.35-micron fabrication. The Patara chip is a 16-channel preamp/shaper/blr for high-efficiency solid-state neutron detectors. It features a regulated cascode preamplifier with adjustable gain, digitally adjustable leakage current compensation and active feedback reset network with matching pole/zero cancellation network, and an input pulse polarity adjustment. The shaper has a five-pole semi-Gaussian response utilizing two pairs of current-input complex-conjugate poles with gated baseline restoration. The system dissipates 3.7 mW/channel. Measurements indicate an overall gain of 9.7 mV/fC and 5.65 mV/fC for full- and half-gain settings, 270 nanosecond full-width half-maximum (FWHM) output, and 550 RMS electrons input noise for a 5 pF detector capacitance.

  • Ramkumar Krithivasan; Yuan Lu; Laleh Najafizadeh; Chendong Zhu; John D. Cressler; Suheng Chen; Chandradevi Ulaganathan; Benjamin J. Blalock
    2006 Bipolar/BiCMOS Circuits and Technology Meeting
    2006

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    We investigate, for the first time, the design and implementation of a high-slew rate op-amp in SiGe BiCMOS technology capable of operation across very wide temperature ranges, and down to deep cryogenic temperatures. We achieve the first monolithic op-amp (for any material system) capable of operating reliably down to 4.3 K. Two variants of the SiGe BiCMOS op-amp were implemented using alternative biasing schemes, and the effects of temperature on these biasing schemes, and their impact on the overall op-amp performance, is investigated

  • Steven Ripp; Scott Moser; Brandon Weathers; Sam Caylor; Benjamin Blalock; Syed Islam; Gary Sayler
    2006 Bio Micro and Nanosystems Conference
    2006

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    Bioluminescent bioreporter integrated circuits (BBICs) are hybrid microluminometer/whole-cell reporter sensor devices for monitoring target chemical and biological agents. The integrated circuit portion of the biosensor consists of a 0.35mum complementary metal oxide semiconductor (CMOS) photodiode capable of low level light detection within an approximate 2.25 mm2 footprint. Interfaced to it is a population of bioreporter microorganisms genetically engineered to specifically and reproducibly respond to desired analytes through autonomous, quantitative emission of luxCDABE-based bioluminescent light signals. The microluminometer chip detects these signals, processes them, and communicates the results either through cable or wireless interconnects for distributed biosensing. In addition, BBIC chips can be outfitted with auxiliary functions such as time stamping, positional sensing, or temperature measurement to provide a more thorough profile of the environment in which it is operating. Our existing laboratory set-up places the BBIC in-line with a liquid or air flow-through system for continuous online monitoring. A remote BBIC has also been developed for static monitoring in either liquid or vapor phase. Detection limits for tested bioreporters approach part-per-billion levels with response times of less than one hour. In progress evolution of BBIC design using nanostructured arrays of vertically aligned carbon nanofibers may permit multiplexed detection of chemical and biological agents in a single chip format

  • S. K. Islam; W. Qu; R. Vijayaraghvan; S. C. Terry; M. Zhang; B. Blalock; S. Caylor; S. Ripp; G. S. Sayler
    2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings
    2006

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    An integrated CMOS microluminometer for detection of very low-level bioluminescence is presented. Signal processing is accomplished with a current-to-frequency converter circuit. Photodiode, integrator, voltage reference circuit and noise are analyzed in detail in this paper. The biosensor chip was fabricated using a standard 0.35mum CMOS process and dissipate 3 mW for 3.3 V power supply. Test results are given to prove the concept

  • S. K. Islam; B. Weathers; S. C. Terry; M. Zhang; B. Blalock; S. Caylor; S. Ripp; G. S. Sayler
    Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.
    2005

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    We report a biosensor using genetically-engineered whole-cell bioreporters on integrated circuit for low-level chemical sensing. The bioluminescent bioreporters are bacteria that can be genetically altered to achieve bioluminescence when in contact with a targeted substance. The bioreporters are placed on a microluminometer. The microluminometer includes integrated photodetector and signal processor and is realized on a standard CMOS process. The bioluminescent bioreporter integrated circuit (BBIC) can detect luminescence from as few as 5000 fully induced pseudomonas fluorescene 5RL bacteria cell.

  • K. Akarvardar; B. Dufrene; S. Cristoloveanu; J. A. Chroboczek; P. Gentil; B. J. Blalock; M. Mojarradi
    2005 IEEE International SOI Conference Proceedings
    2005

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    Low-frequency noise characteristics of four-gate transistors (G4-FETs) are presented distinguishing the surface conduction (MOSFET mode) and volume conduction (JFET mode). As the conducting channel moves from the surface to the bulk we observe that: (i) the noise level dramatically decreases; and (ii) the nature of the noise changes. The validity of the existing noise models for different conduction modes is discussed.

  • R. Vijayaraghavan; S. K. Islam; B. J. Blalock; V. Srinivasan
    48th Midwest Symposium on Circuits and Systems, 2005.
    2005

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    An analog programmable frequency divider (APFD) that is based on the concept of an analog counter is described. The divide ratio is set using the analog counter and a toggle flip-flop. A prototype programmable divider has been implemented in a 0.5mum standard digital CMOS process with divide ratios ranging from 16-30 in steps of 2 for a maximum input frequency of 10MHz. The divide ratio exhibits a weak logarithmic dependence on process, voltage and temperature (PVT) variations that can be addressed using resistor trimming. Simulation results have been provided that demonstrate both the functionality and feasibility of the proposed divider

  • S. Chen; J. Vandersand; B. J. Blalock; K. Akarvardar; S. Cristoloveanu; M. Mojarradi
    Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.
    2005

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    A new approach for high-voltage analog applications that utilizes SOI four-gate transistors (G4-FETs) is presented. The proposed solution achieves high-voltage operation (10 V and higher) with no additional cost of fabrication (compatible with standard SOI) and minimal added design overhead compared to their MOSFET counterparts. Measurement results of high-voltage current mirrors and differential pairs show superior HV capability with small signal performance comparable to their MOSFET counterparts. By using the high-voltage current mirror and differential pair as basic building blocks, a differential amplifier is built and tested with a 20 V supply.

  • C. S. A. Durisety; B. J. Blalock; B. M. Dufrene
    48th Midwest Symposium on Circuits and Systems, 2005.
    2005

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    This paper presents the characterization results of a single-poly floating gate device (FGD) in 0.35 mum partially-depleted silicon-on-insulator (PDSOI) technology. Programmability of threshold voltage (VTH) of these devices gives them a unique advantage in the development of post-process adjustable low offset operational amplifiers, highly accurate current mirrors, etc. This paper demonstrates a post-process trimmable current reference using these devices as resistive elements. A MATLAB model incorporating the tunneling parameters has been developed and the simulation results are found to match well with the experimental results

  • K. Akarvardar; S. Chen; B. J. Blalock; S. Cristoloveanu; P. Gentil; M. Mojarradi
    Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.
    2005

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    A novel analog multiplier using SOI four-gate transistors (G4-FETs) is presented. Thanks to the multiple inputs of the G4-FET that may be biased independently, the number of transistors in the proposed circuit is dramatically reduced, compared to conventional single-gate MOSFET based multipliers. Only four G4-FETs are needed to build the multiplier core. The circuit is feasible with a standard SOI CMOS process. Two different configurations, both based on the linear modulation of the front-gate threshold voltage by the junction-gates, are presented. This paper addresses the theoretical analysis as well as the preliminary measurement results.

  • J. Vandersand; V. Kushner; J. Yang; B. Blalock; T. Thornton
    2005 IEEE Aerospace Conference
    2005

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    Silicon-on-insulator MESFETs have been manufactured using a commercial SOI CMOS process and their electrical characteristics measured from room temperature up to 200deg C. No modifications were made to the CMOS process flow. The prototype devices use a CoSi2 gate material and the gate current follows the expected Shottky diode behavior. At room temperature a 0.6 mum gate length device has a threshold voltage of -0.8 V with an off-state drain current of approximately 5 nA. The device shows an attractive family of I-V curves up to 200deg C. For higher temperatures the reverse diode current makes it hard to switch the device off. Numerical simulations of a similar device with a higher barrier height PtSi gate show reasonable behavior up to 300degC

  • S. K. Islam; C. Durisety; R. Vijayaraghavan; H. Nguyen; B. Blalock; L. R. Baylor; W. L. Gardner
    2005 International Vacuum Nanoelectronics Conference
    2005

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    This paper presents a prototype implementation of a circuit that can control charge emission from the vertically aligned carbon nanofibers (VACNF), for use in the implementation of digital electrostatic e-beam array lithography (DEAL). This lithography technique can be used to fabricate ultra-small feature size devices, while cutting down the manufacturing costs of photomasks. These VACNF's are found to be quite robust for use as micro-fabricated field emission devices. The all inverter based dose control circuit (DCC) presented in this paper was fabricated using a standard 0.5 μm CMOS process to improve the dose-rate accuracy, when using these VACNF's for etching in maskless lithography. Simulation and measurement results are compared and analyzed, and future work for improving the design is discussed.

  • K. Akarvardar; S. Cristoloveanu; B. Dufrene; P. Gentil; R. D. Schrimpf; B. J. Blalock; J. A. Chroboczek; M. Mojarradi
    Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.
    2005

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    The low noise and radiation-hard operation of the SOI four-gate transistor (G4-FET) is experimentally demonstrated. When operated in depletion-all-around (DAA) mode, the G4-FET drain current flows in the middle of the silicon film, far from the interfaces. The influence of oxide and interface traps on the conduction channel is suppressed by biasing the front and back gates in depletion or, even better, in inversion. Systematic data show a significant reduction of low-frequency noise as well as a quasi-insensitivity to total-dose radiation effects, up to 10 Mrad. These features come along with superior static characteristics in DAA mode and are attractive for G4-FET-based analog circuits.

  • M. N. Ericson; M. Hasanuzzaman; S. C. Terry; C. L. Britton; B. Ohme; S. S. Frank; J. A. Richmond; B. J. Blalock
    2005 IEEE Aerospace Conference
    2005

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    A summary of measured small-signal parameters and low frequency noise characterized over temperature is presented for N- and P- MOSFETs fabricated in a partially depleted SOI 0.8 mum process. Small-signal dc parameters critical in analog circuit design are reported including device transconductance efficiency (gm/Id), output resistance (rds), and threshold voltage (Vt). These parameters are summarized as a function of both gate length (0.8mum, 2.0mum, 5.0mum, and 20mum) and temperature (20deg to 300degC). Noise characterization of these devices is also presented with an emphasis on flicker noise over temperature (20deg to 250degC). Data is presented in terms of both drain current and inversion coefficient, where appropriate. Use of this information provides the designer with an excellent tool for estimating analog circuit performance in applications where wide temperature range performance is required

  • L. R. Baylor; W. L. Gardner; X. Yang; R. J. Kasica; B. Blalock; C. Durisety; J. Fowlkes; D. K. Hensley; S. Islam; D. C. Joy; A. V. Melechko; P. D. Rack; S. J. Randolph; R. Rucker; D. K. Thomas; M. L. Simpson
    2005 International Vacuum Nanoelectronics Conference
    2005

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    Prototype field emission devices have been fabricated in the 300-1000 eV range using vertically aligned carbon nanofibers as the field emitter. The devices are fabricated using a self-aligned process for the extraction gate opening and the focus grid opening is defined lithographically. Field emission tests of the completed devices are carried out in a vacuum chamber with a phosphor anode and show that the emission follows Fowler-Nordheim characteristics. A technique to selectively grow fibers with W in digitally addressable field-emission array (DAFEA) prototype devices is demonstrated by nanoscale electron beam induced deposition (EBID). A non-organometallic precursor, WF6, is used to deposited metallic W fibers. Vacuum electrical testing revels that electrons are successfully extracted from the W nanofiber tip and have been used to draw lines in PMMA coated glass substrates in the DEAL lithography testbed. This growth technique can be used to repair DAFEA emitters thus providing a means to produce a reliable massive parallel e-beam write head.

  • M. M. Mojarradi; B. J. Blalock; E. Kolawa; R. W. Johnson
    Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.
    2005

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    Next generation space-based robotics systems will be constructed using distributed architectures where electronics capable of working in the extreme environments of the planets of the solar system are integrated with the sensors and actuators in plug-and-play modules and are connected through common multiple redundant data and power buses. Challenges for development of integrated circuits for these robotic systems deal with the reliable operation of these systems under extreme planetary environments. These challenges are compounded by a complementary set of packaging and assembly issues that address the reliability of the system from the mechanical point of view. Without exception integrated electronics developed for space systems will have to use existing commercial device and VLSI manufacturing technologies. Because of the severe difference between the extreme environment of the solar system planets and Earth, IC designers of space systems have to examine the performance of all the devices in the extreme environment conditions and define a new set of design rules and models that predicts the performance and life cycle of these technologies.

  • S. C. Terry; B. J. Blalock; J. M. Rochelle; M. N. Ericson; S. D. Caylor
    IEEE Symposium Conference Record Nuclear Science 2004.
    2004

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    A custom simulation tool that combines HSPICE and MATLAB to enable time-domain noise analysis is reported. The simulation technique is based on computing the statistics of a random process by ensemble averaging and is applicable to both linear time-invariant (LTI) and linear time-variant (LTV) systems. MATLAB is used to generate a set of representative noise signals, which are imported into HSPICE for simulation. Once the simulations are complete the results are read back into MATLAB and ensemble statistics are calculated. The MATLAB-generated noise signals have a user-defined white-noise floor and flicker noise corner frequency and thus are suitable for modeling a wide variety of electronic components, including CMOS transistors and resistors. Simulation results of the time-dependent output noise of a gated integrator and the timing resolution of a gated integrator/comparator detector are presented to highlight both the utility and the versatility of the tool.

  • K. Akarvardar; S. Cristoloveanu; P. Gentil; B. J. Blalock; B. Dufrene; M. M. Mojarradi
    Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)
    2004

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    Only in 4-gate SOI transistors (G4-FETs) can the channel be surrounded by depletion regions induced by independent vertical MOS gates and lateral JFET gates. The majority carriers flow in the film volume, far from interfaces and junctions. We show that inversion layers, formed at the front and back interface, enable the junction gates to have enhanced control on the volume channel. High performance is experimentally demonstrated in terms of transconductance, subthreshold swing and gm/Id ratio. The basic mechanism, which involves a specific 2D gate coupling, is explained with a simple analytical model and simulations.

  • S. C. Terry; B. J. Blalock; J. R. Jackson; Suheng Chen; C. S. A. Durisety; M. M. Mojarradi; E. A. Kolawa
    2004 IEEE Aerospace Conference Proceedings (IEEE Cat. No.04TH8720)
    2004

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    The Integrated Circuits and Systems Laboratory at the University of Tennessee is currently investigating robust CMOS analog and mixed-signal circuit design techniques for extreme environments. In this paper, we present system level and transistor level extreme environment design techniques and measurement results from several test circuits. The design techniques focus on developing high performance operational transconductance amplifiers (OTAs) and op-amps that can operate over a wide temperature range. The test circuits include a 3.3-V ping-pong op-amp, a 3.3-V rail-to-rail I/O op-amp capable of driving resistive loads, and a temperature stable voltage reference and current reference.

  • M. M. Mojarradi; R. S. Cozy; Yuan Chen; E. A. Kolawa; M. Johnson; T. McCarthy; G. C. Levanas; B. Blalock; G. Burke; L. Del Castillo; A. A. Shapiro
    2004 IEEE Aerospace Conference Proceedings (IEEE Cat. No.04TH8720)
    2004

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    Commercial-off-the-shelf electronic components (COTS) offer a very low cost and attractive solution for construction of electronic systems for Mars missions, including the actuator electronic systems for the Mars Rovers. One issue with using COTS lies in the difference between their specified operating temperature range (-55°C to125°C for military components) and the temperatures observed at the surface of Mars (-120°C to 20°C). To compensate for the difference between these temperatures, most of the electronics are placed in a central warm-electronics-box or WEB. In some cases, such as the distributed control system for the actuators, the electronic assemblies that are to be placed on or near the motors are outside of the central WEB. The experimental search consists of two steps. First, a short functional/non-functional test at -120°C is used to identify and narrow down the number of candidate COTS that can work at very cold temperatures. More extensive characterization of the parts that passes the short test is performed to determine the operating margins and estimate the thermal cycle life capability for the COTS parts. Finally, the operating margins of the COTS parts are published as a set of specifications.

  • M. N. Ericson; M. Bobrek; A. Bobrek; C. L. Britton; J. M. Rochelle; B. J. Blalock; R. L. Schultz
    2004 IEEE Aerospace Conference Proceedings (IEEE Cat. No.04TH8720)
    2004

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    A ΣΔ modulator designed specifically for extended temperature applications is reported. The design is fabricated in a 3.3-V 0.5 μm SOS-CMOS process and incorporates a 2-2 cascade architecture allowing operation as either a 2nd- or 4th-order modulator. Experimental data for both modulator configurations are presented including dynamic range (or effective resolution), signal-to-noise ratio and total harmonic distortion over a temperature range of 25°C to 225°C. The design obtains an effective resolution of ∼16 bits at 25°C and ∼12 bits at 225°C, both at a digital output rate of 2 KS/s. Specific design details associated with high temperature operation are discussed including architectural issues, device sizing, and modulator noise. In addition, a digital decimation filter designed for use with the modulator and implemented in both software and in a field programmable gate array is summarized. This paper reports the first 4th-order ΣΔ modulator fabricated in an SOI/SOS process and demonstrates the feasibility of high resolution data conversion at elevated temperatures.

  • D. M. Binkley; C. E. Hopper; B. J. Blalock; M. M. Mojarradi; J. D. Cressler; L. K. Yong
    2004 IEEE Aerospace Conference Proceedings (IEEE Cat. No.04TH8720)
    2004

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    MOS transconductance and white noise is described from weak through strong inversion to facilitate the design of a 0.35-μm, partially-depleted silicon-on-insulator (SOI) CMOS micropower, low noise preamplifier. This analysis is extended to cryogenic temperatures where MOS subthreshold slope is reduced significantly from its expected value. Transconductance and white noise for an input PMOS device in moderate inversion and non-input NMOS device in strong inversion are measured and compared to predicted values for 77-400 K. Transconductance increases, and input-referred white-noise voltage decreases at 77 K, while input-referred flicker noise remains relatively unchanged. Finally, a micropower, low-noise preamplifier is presented. The measured input-referred white noise is 69 nV/Hz12/ at 293 K dropping to 56 nV/Hz12/ at 86 K for a differential input stage bias current of 1 μA. The flicker-noise corner frequency is approximately 20 Hz, permitting use with deep space mission sensors like gyros having low frequency output signals.

  • M. N. Ericson; C. L. Britton; J. M. Rochelle; B. J. Blalock; B. D. Williamson; R. L. Greenwell; R. Schultz
    2003 IEEE International Conference on SOI
    2003

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    Extensive characterization results of MOSFET small-signal parameters over temperature (25° to 300°C) are presented for low-VT transistors fabricated in a SOS 0.5-μm process. Low-VT devices such as these are particularly useful for low-voltage, low-power (LVLP) analog applications. Small-signal dc parameters critical in analog circuit design are reported including device transconductance efficiency (gm/Id), output resistance (rds), and threshold voltage (VT). These parameters are summarized as a function of both gate length (0.5 μm to 16 μm) and temperature. Inversion coefficient representation is employed for data presentation and analysis. This work provides the most thorough presentation of SOS MOSFET dc parameters as a function of both gate length and temperature to date. In addition, this work summarizes device information essential for successful high-temperature SOS-CMOS analog circuit design.

  • Dufrene; Akarvardar; Cristoloveanu; Blalock; Fechner; Mojarradi
    2003 IEEE International Conference on SOI
    2003

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    We present the operational and performance of the 4-gate transistor (G4-FET) from the low voltage to the high voltage regime. Measured results show the complexity of threshold voltage, subthreshold swing, and breakdown voltage due to the multiple gate control utilized with the G4-FET. Devices fabricated in a 0.35 μm 3.3 V partially-depleted SOI process can achieve a breakdown voltage of 15 V, excellent subthreshold swing, and high mobility.

  • D. M. Binkley; D. H. Ihme; C. E. Hopper; B. J. Blalock; M. M. Mojarradi
    Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)
    2003

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    In this paper, we present two micropower, low-noise 0.35-μm partially depleted (PD) silicon-on-insulator (SOI) CMOS preamplifiers designed for the extreme temperature and radiation environment of deep space. PMOS input devices are used for low flicker noise, and these are operated in moderate inversion to achieve high transconductance efficiency and minimum input-referred gate white-noise voltage at low power consumption. Resistive source degeneration, using MOS devices in the deep ohmic region, reduces the effective transconductance of non-input NMOS devices and their normally high flicker noise contributions. The measured input-referred noise for a differential input preamplifier is 275 nV/√Hz at 1 Hz with a 15-Hz flicker noise corner frequency and white noise floor of 70 nV/√Hz. The measured input-referred noise for a transimpedance preamplifier is 200 nV/√Hz at 1 Hz with a 30-Hz flicker noise corner frequency and white noise floor of 35 nV/√Hz. Each preamplifier operates at a core power dissipation of 6.6 μW at a supply voltage of 3.3 V.

  • K. Akarvardar; B. Dufrene; S. Cristoloveanu; B. J. Blalock; T. Higashino; M. M. Mojarradi; E. Kolawa
    European Solid-State Device Research, 2003. ESSDERC '03. 33rd Conference on
    2003

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    Systematic measurements of four-gate SOI transistors (G/sup 4/-FET) are presented. Methods of extraction of the threshold voltage, subthreshold swing, and mobility in the linear region are discussed and results are shown. The extracted parameters demonstrate the complex dependence of the multi-gate biases, which is explained. A new extraction technique for the carrier mobility and effective width of devices with isolated multiple gates is proposed.

  • S. C. Terry; B. J. Blalock; J. R. Jackson; Suheng Chen; M. M. Mojarradi; E. A. Kolawa
    Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488)
    2003

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    The INSYTE (Integrated Circuits and Systems) Laboratory at The University of Tennessee is currently investigating robust CMOS analog and mixed-signal circuit design techniques for extreme environments. This work is being targeted for Mars surface applications where the temperature can vary from -1200□C to +20□C depending on time of day and location. In this paper we present both robust analog design techniques and measurement results from several test circuits. The design techniques focus on developing high performance OTAs and op-amps that can operate over a wide temperature range. The test circuits include a 3.3 V ping-pong op-amp and a 3.3 V rail-to-rail I/O op-amp capable of driving resistive loads.

  • Ying Li; Guofu Niu; J. D. Cressler; J. Patel; M. Liu; R. A. Reed; M. M. Mojarradi; B. J. Blalock
    2003 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2003. Digest of Papers.
    2003

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    Partially-depleted SOI CMOS devices fabricated in a 0.35 /spl mu/m technology on UNIBOND material were evaluated for electronics applications requiring robust operation under extreme environment conditions consisting of: low and/or high temperatures, and under substantial radiation exposure. The threshold voltage and effective mobility were determined across temperature for SOI CMOS. The radiation response was characterized using threshold voltage shifts of both the front-gate and back-gate transistors. These results suggest that this 0.35 /spl mu/m partially-depleted SOI CMOS technology Is suitable for operation across a wide range of extreme environment conditions consisting of: cryogenic temperatures down to 86 K, elevated temperatures up to 573 K, and under radiation exposure to 1.3 Mrad(Si) total dose.

  • D. M. Binkley; D. H. Ihme; B. J. Blalock; M. M. Mojarradi
    2003 IEEE International Conference on SOI
    2003

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    In this paper, analog circuit fabricated in SOI CMOS processes have the potential of maintaining required performance over the extreme temperature and radiation environment of deep space was studied. Low input referred white and flicker noise voltage was required to amplify signals.

  • M. N. Ericson; C. L. Britton; J. M. Rochelle; B. J. Blalock; D. M. Binkley; A. L. Wintenberg; B. D. Williamson
    2002 IEEE Nuclear Science Symposium Conference Record
    2002

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    This paper presents a summary of the measured noise behavior of CMOS MOSFETs fabricated in a 0.5 μm fully-depleted (FD) silicon-on-sapphire (SOS) process. SOS CMOS technology provides an alternative to standard bulk CMOS processes for high-density detector front-end electronics due to its inherent radiation tolerance. In this paper, the noise behavior of SOS devices will be presented and discussed with reference to device inversion coefficient (IC). The concept of inversion coefficient will be introduced and the results of SOS device noise measurements in weak, moderate, and strong inversion will be presented and compared for devices with gate lengths of 0.5 μm to 4 μm. Details of the noise measurement system will be provided including specifics of the measurement approach and custom circuits used for device biasing. This work will provide a thorough presentation of measured SOS device noise as a function of inversion coefficient. In addition, strategies for device biasing and sizing to obtain optimum noise performance will be presented encouraging more widespread use of SOS integrated circuits in high-density detector applications.

  • B. K. Swann; J. M. Rochelle; D. M. Binkley; B. S. Puckett; B. J. Blalock; S. C. Terry; J. C. Moyers; J. W. Young; M. E. Casey; M. S. Musrock; J. E. Breeding
    2002 IEEE Nuclear Science Symposium Conference Record
    2002

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    A custom mixed-signal CMOS integrated circuit has been developed for high performance PET tomograph front-end applications. The ASIC contains four differential, variable-gain, constant bandwidth, amplifiers to receive buffered PMT voltage pulses. All four amplified PMT signals are summed by adding their outputs and feeding this sum to the timing channel of the ASIC. The timing channel, which consists of a constant fraction discriminator and sub-nanosecond time to digital converter, offers excellent PET count rate performance and random noise reduction through low deadtime (100 ns) and excellent tuning resolution (312.5 ps). Amplified PMT signals are also distributed to energy processing channels for lowpass filtering, and buffering for subsequent digitization by external ADCs. The ASIC offers substantial size, power, and cost reductions over existing PET front-end discrete designs. Fabricated in a 5 V, 0.5 μm, triple metal, double poly, n-well CMOS process, the new ASIC has a die size of 20 mm2 and dynamic power dissipation under 425 mW.

  • J. W. Bruce; J. E. Creekmore; B. J. Blalock
    The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002.
    2002

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    In this paper, an area and power efficient ROM-less DDFS circuit with sinusoidal output is proposed. Sinusoidal spaced reference voltages are generated using an integrated resistor with a complex geometry. A DDFS accumulator output controls the nonlinear sinusoidal DAC directly and without the power-hungry ROM. The proposed design is independent of sheet resistance, and voltage reference power dissipation can be tailored to the application. Photolithography limitations can introduce geometry errors, thus, reference voltage errors. An adaptive design algorithm is proposed that reduces reference errors by more than an order of magnitude compared to the prior method. Finally, measurement results from a prototype 0.5 μm CMOS implementation are presented.

  • S. Cristoloveanu; B. Blalock; F. Allibert; B. Dufrene; M. Mojarradi
    32nd European Solid-State Device Research Conference
    2002

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    First Page of the Article

  • Ericson; Rochelle; Bobrek; Britton; Bobrek; Blalock; Schultz; Moore
    2002 IEEE International SOI Conference
    2002

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    A ΣΔ modulator fabricated in 0.5μm SOS-CMOS is reported. The design incorporates two 2nd-order loops allowing reconfigurability as either a 2nd-order single loop or a 4th-order 2-2 cascade. Test results of both modulator configurations over a temperature range of 25°C-200°C are presented. The modulator achieves an effective resolution of 15.5 bits at 25°C and 13.5 bits at 200°C (both at 2KS/s). Design details pertaining to topological selection and device sizing is presented with an emphasis on temperature tolerance. Results of modulator noise analysis is presented along with techniques for improving the modulator noise performance. This paper reports the first 4th-order ΣΔ modulator fabricated in an SOI/SOS process.

  • S. Terry; B. J. Blalock; L. Yong; B. Dufrene; M. Mojarradi
    2002 IEEE International SOI Conference
    2002

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    This paper describes several analog circuit primitives that utilize the body terminal as a signal port. A cascode current mirror that can operate with an input and output voltage of 200 mV, and a rail-to-rail constant transconductance gain block capable of 1 V operation are presented. These circuits have been implemented in a standard 0.35 μm partially-depleted silicon-on-insulator (PDSOI) CMOS process and should find wide application in next-generation analog circuit designs.

  • S. C. Terry; J. M. Rochelle; D. M. Binkley; B. J. Blalock; D. P. Foty; M. Bucher
    2002 IEEE Nuclear Science Symposium Conference Record
    2002

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    A BSIM3V3 and EKV model for a standard 0.5 um CMOS process has been evaluated for analog applications. Critical small-signal parameters including output conductance and transconductance efficiency were simulated for devices with gate lengths ranging from 0.5 um to 33 um. In addition, the small-signal parameters were measured on test devices with similar dimensions. The results highlight the difficulty of obtaining a model that accurately predicts the operation of low voltage analog circuits.

  • B. J. Blalock; S. Terry; B. Dufrene; C. Durisety; L. Yong; S. Cristoloveanu; M. Mojarradi
    The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002.
    2002

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    SOI technology has become the commercial technology of choice for both high performance and low power digital applications. By comparison, analog development in SOI is still in its infancy. To help emphasize analog/mixed-signal opportunities in SOI, both for circuits and new devices, this paper provides a sampling of the SOI research at the University of Tennessee. Circuit highlights include an operational amplifier with automatic offset cancellation, a VCO-based ADC, and body-driven analog circuits. The G4-FET, a four-gate transistor in SOI, is introduced. Floating-gate devices on SOI are also presented, including their application to post-process trimmable analog circuits.

  • J. Creekmore; S. Porter; J. Bruce; B. J. Blalock
    Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)
    2001

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    A design technique that uses nonlinear D/A conversion for low power, area efficient sine output direct digital frequency synthesis (DDFS) is presented. Nonlinear reference voltages are created geometrically and replace the large, power hungry ROM in conventional DDFS circuits. The proposed design is independent of sheet resistance. Finally, design equations and simulations are presented

  • J. A. Bell; J. W. Bruce; B. J. Blalock; P. A. Stubberud
    Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)
    2001

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    A high speed CMOS current mode flash analog to digital converter is proposed. The design uses a generic cell structure that decreases circuit area for large implementations of the design. A single cell is tested for design constraints, and design constraint solutions are discussed

  • S. A. Jackson; B. J. Blalock; M. M. Mojarradi; H. W. Li
    2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)
    2000

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    High-voltage transistors in SOI that coexist with traditional low-voltage transistors enable the development of mixed-voltage (high-voltage and low-voltage) systems-on-a-chip. The parasitic back-channel transistor, however, is a critical issue in these mixed-voltage single-chip systems. The presence of high-voltage can create a situation in which the parasitic back-channel device turns on and “shorts-out” the top device inducing functional failure of the system. An active substrate driver has been designed that automatically adjusts the substrate bias voltage to a level ensuring the back-channel devices remain off. The active substrate driver should also help compensate for shifts in back-channel transistor threshold voltages induced by temperature, aging, and irradiation effects

  • B. J. Blalock; H. W. Li; P. E. Allen; S. A. Jackson
    2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390)
    2000

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    This paper presents an overview of circuit topologies for achieving low-voltage analog designs using body-driving techniques. A new and novel low-voltage Class AB output stage is presented along with topologies for amplifiers and a four quadrant multiplier. A discussion of the application of body-driving in a silicon-on-insulator (SOI) technology is also included

  • B. J. Blalock; S. A. Jackson
    1999 Southwest Symposium on Mixed-Signal Design (Cat. No.99EX286)
    1999

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    A 1.2 V CMOS four-quadrant analog multiplier is presented. Using both the gate and bulk terminals of the MOSFET to achieve modulation, a simple 4-transistor multiplier core is obtained. Experimental results are given for a 0.5-μm prototype with VTn=0.7 V and VTp=-0.9 V

  • S. A. Jackson; B. J. Blalock
    1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)
    1998

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    Limited pin counts and achievable bandwidth have become a major limitation to achievable I/O speed of integrated circuits. Previously published current-mode techniques enable I/O circuits to achieve simultaneous bidirectional signaling. This maximizes data rate with minimal I/O power dissipation and minimal I/O pin count. A new I/O circuit fabricated in 2 μm CMOS is described in this work which is capable of handling both analog and digital data signals in a simultaneous bidirectional manner. Mixed-signal operation is achieved by using an analog transmitter to steer current in and out of a transmission line with a receiver amplifier recovering the receive signal

  • B. J. Blalock; P. E. Allen
    1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96
    1996

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    In this paper a folded-cascode operational transconductance amplifier (OTA) is described which operates from a one-volt supply and is compatible with standard digital CMOS technology with threshold voltages in the range of ±0.8 V. This OTA utilizes a bulk-driven new differential pair and a new bulk-driven cascode current mirror to achieve 1 V operation while providing 1 MHz gain-bandwidth product with only 120 μW power dissipation with a 10 pF load

  • B. J. Blalock; P. E. Allen
    Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on
    1995

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    A bulk-driven, MOSFET current mirror is described which is capable of operating at power supplies down to 1 V using standard CMOS technologies with threshold voltages in the range of ±0.8 V. The bulk-driven MOSFET configuration removes the requirement that the input voltage of the current mirror equal VGS>VT. At VDD/VSS of+0.75 V/-0.75 V, measurements on simple current mirrors using this new technique require only about 0.1 V across the input device of the current mirror circuit and exhibit saturation voltages on the output device of the current mirror comparable to that of standard simple current mirrors. The operation and first-order models for the bulk-driven MOSFET are presented in this paper along with the operation and experimental results of a simple, bulk-driven mirror

  • P. W. Allen; B. J. Blalock; G. A. Rincon
    Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
    1995

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    It is important to develop circuit techniques that permit existing CMOS to implement analog circuits at power supply voltages as low as 1 V. This paper describes some of these techniques and illustrates their application in the design of a CMOS op amp operating from a 1 V power supply. This opamp uses a digital 2-/spl mu/m CMOS having threshold voltages of 0.7 to 0.8 V and demonstrates performance comparable with opamps using higher power supply voltages.

  • P. E. Allen; B. J. Blalock
    [1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems
    1992

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    BiCMOS technology offers both the analog and digital designer a wide range of transistor selections which can be utilized to improve the performance of integrated circuits. The tradeoffs which occur when BiCMOS is applied to analog circuits are examined. While general guidelines are proposed the individual applications will make the tradeoffs more complex. This is illustrated by using a simple op amp to analyze the performance for various selections of transistors. It is shown that the correct selection of transistor types depends on the desired performance. This performance comparison is based on simulation results. This investigation illustrates important considerations which must be given to BiCMOS analog circuit design

  • C. D. Tudryn; B. Blalock; G. Burke; Yuan Chen; S. Cozy; R. Ghaffarian; D. Hunter; M. Johnson; E. Kolawa; Mohammad Mojarradi; D. Schatzel; A. Shapiro
    2006 IEEE Aerospace Conference
    -0 0

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    This paper presents a survivability and reliability investigation for integrated actuator and brushless motor drive electronics packaging and components under an extreme low temperature and high thermal cycle environment. A universal brushless motor drive electronics assembly has been designed, built, and thermal cycle tested for use in Mars, Moon, and asteroid type cold environments without the need for any active thermal control. The assembly uses electronic part types and chip-on-board electronic packaging technology that allow operation at temperatures down to -180degC. The thermal cycle capability of the assembly has been demonstrated to be in excess of 2010 cycles from -120degC to 85degC, over a 210degC total temperature swing. Future space missions will require electronic and actuator systems on a planet, asteroid or Moon surface to function beyond the established reliability limits of currently used components and materials systems. In support of this target application, the Jet Propulsion Laboratory (JPL) has performed a series of experiments to test the reliability of actuators, sensors, electronic components, and electronic packaging designs to provide input to the detailed flight design of a universal brushless motor drive electronics and integrated actuator assembly. These experiments started with the use of a chip-on-board electronic packaging strategy due to its inherent advantage of improved high functionality with minimal circuit board area compared with standard packaged electronic components. Initial electronic packaging experiments were comprised of various sized chip devices with gold wire bonds. The second phase of electronic packaging experiments conducted at JPL consisted of power devices with large diameter wire bonds as well as various surface mount resistor devices. Full factorial experiments were designed to find the most reliable combinations of substrate type, component attach method and encapsulation. The surviving material combination- - s after a minimum of 1500 thermal cycles were utilized to form the basis of the packaging and electronic component detailed design approach used in the universal brushless motor drive electronics design. Electrical failures were defined as open circuits. A failure analysis procedure was applied by defining the failure mechanism and applying a risk mitigation. After 1500 cycles, the packaged assembles were cycled to exceed 2010 cycles and additional material considerations were made. In addition, selected components were functionally tested over the temperature range of +100degC to -180degC and cold soaked at -150degC for 1000 hours for reliability. A design for reliability method was also developed at the component and circuit level for electronics operating at extreme low temperatures