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Ben Blalock

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Personal Photograph
Office: Min Kao 503
E-mail:
ude.ktu@kcolalbb
Phone: 865-974-0927
Fax: 865-974-5483
Address: Min H. Kao Building, Suite 503
1520 Middle Drive
Knoxville, TN 37996-2250


Biography

Benjamin J. Blalock is the Blalock-Kennedy-Pierce Professor in the Department of Electrical Engineering and Computer Science at the University of Tennessee where he directs the Integrated Circuits and Systems Laboratory (ICASL).


He received his B.S. degree in electrical engineering from the University of Tennessee, Knoxville, in 1991 and the M.S. and Ph.D. degrees, also in electrical engineering, from the Georgia Institute of Technology, Atlanta, in 1993 and 1996 respectively.


Dr. Blalock has received numerous teaching and research awards at UT. His research focus at UT includes analog integrated circuit design for extreme environments (both wide temperature and radiation) on CMOS and SiGe BiCMOS, high-temperature/high-voltage gate drive circuits for power electronics, multi-channel monolithic instrumentation systems, mixed-signal/mixed-voltage circuit design for systems-on-a-chip, and analog circuit techniques for sub 100-nm CMOS.


Dr. Blalock has co-authored over 100 refereed papers. During the 2007 IEEE Nuclear Science and Radiation Effects Conference (NSREC) he taught a short course on Radiation Effects on Analog Integrated Circuits and Extreme Environment Design. He has also worked as an analog IC design consultant for Cypress Semiconductor, Concorde Microsystems, and Global Power Electronics. Dr. Blalock is a senior member of the IEEE.

Publications

Last updated May 19, 2020.

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Journal Papers
Title
Year
  • Philippe C. Adell; Jeremy Yager; Zack Pannell; Jacob Shelton; Mohammad M. Mojarradi; Benjamin Blalock; Greg Allen; Raphael Some
    IEEE Transactions on Nuclear Science
    2014

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    The radiation robustness of a newly designed Wilkinson analog-to-digital converter (ADC) is being investigated. The ADC is a front-end design block within a cold capable, analog sense, application-specific integrated circuit (ASIC) manufactured using the IBM 0.5 μm silicon germanium (SiGe) BiCMOS 5HP process. The ASIC is part of a next-generation, cold capable, distributed motor controller architecture, which is a candidate for the next generation of Mars rovers. Its main function is to interface with various sensor types to monitor motor health (i.e., temperature, mechanical stress, pressure). While relatively well-hardened against total ionizing dose and destructive single-event latchup, the ADC showed some SEU (SET) sensitivity that is heavily dependent on its input channel configuration. For this study, we used a combination of experiments (pulsed-laser) and Cadence mixed-mode SEE simulations to explain the heavy ion irradiation results. We concluded that ADC input impedance configuration should be carefully controlled in the design of radiation-hardened systems for space.

  • Ryan M. Diestelhorst; Troy D. England; Richard Berger; Ray Garbos; Chandradevi Ulaganathan; Ben Blalock; Kimberly Cornett; Alan Mantooth; Xueyang Geng; Foster Dai; Wayne Johnson; Jim Holmes; Mike Alles; Robert Reed; Patrick McCluskey; Mohammad Mojarradi; Leora Peltz; Robert Frampton; Cliff Eckert; John D. Cressler
    IEEE Aerospace and Electronic Systems Magazine
    2012

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    We have described the modeling, circuit design, system integration, and measurement of a Remote Sensor Interface (Figure 20) that took place over a span of 5 years and 8 fabrication cycles. It was conceived as part of the Multi-Chip Module (MCM) shown in Figure 21, which also includes a digital control chip for clocking, programming, and read-out. Further work beyond the scope of this was performed to validate the RSI for the extreme environmental conditions of a lunar mission, and individual blocks are presently.

  • T.D. England; R.M. Diestelhorst; E.W. Kenyon; J.D. Cressler; V. Ramachandran; M. Alles; R. Reed; R. Berger; R. Garbos; B. Blalock; A. Mantooth; M. Barlow; F. Dai; W. Johnson; C. Ellis; J. Holmes; C. Webber; P. McCluskey; M. Mojarradi; L. Peltz; R. Frampton; C. Eckert
    IEEE Aerospace and Electronic Systems Magazine
    2012

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    We have presented the architecture, simulation, packaging, and over-temperature and radiation testing of a complex, 16-channel, extreme environment capable, SiGe Remote Electronics Unit containing the Remote Sensor Interface ASIC that can serve a wide variety of space-relevant needs as designed. These include future missions to the Moon and Mars, with the additional potential to operate in other hostile environments, including lunar craters and around the Jovian moon, Europa. We have expanded on the previous introduction of the RSI to show the validity of the chip design and performance over an almost 250 K temperature range, down to 100 K, under 100 krad TID radiation exposure, with SEL immunity and operability in a high-flux SET environment.

  • Mohammad Mojarradi; Benjamin Blalock
    IEEE Nanotechnology Magazine
    2010

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    This book will take you through a historical voyage to the modern wonders of electronics and nanotechnology. It will provide you with a unique perspective that is both technically and historically balanced, without the prerequisite of an electrical engineering degree.

  • A. L. Sternberg; L. W. Massengill; M. Hale; B. Blalock
    IEEE Transactions on Nuclear Science
    2006

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    Circuit simulations are used to determine the response of a pipelined analog-to-digital converter (ADC) to radiation-induced single-event transients. The ADC uses a cascade of 9 stages which each resolve 1.5 bits. Digital error correction is used to reassemble the bits and to correct for errors in the comparators and sub-DAC. A Monte-Carlo methodology is used to simulate the single-event vulnerability of the circuit. Circuit simulations are performed using the Spectre circuit simulator. Sensitive cross-sections were derived from an analysis of the simulation results. Sensitive areas were identified and hardening techniques were applied to the circuit. These techniques may be applicable to other mixed-signal and switched-capacitor circuits. A significant reduction in the sensitive cross-section was obtained by application of these hardening techniques

  • M. Mojarradi; D. Binkley; B. Blalock; R. Andersen; N. Ulshoefer; T. Johnson; L. Del Castillo
    IEEE Transactions on Neural Systems and Rehabilitation Engineering
    2003

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    This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 /spl times/ 400-/spl mu/m pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1/spl deg/C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic.

Conference Papers
Title
Year
  • Fred Wang; Ruirui Chen; Handong Gui; Jiahao Niu; Leon Tolbert; Daniel Costinett; Benjamin Blalock; Shengyi Liu; John Hull; John Williams; Timothy Messer; Eugene Solodovnik; Darren Paschedag; Vyacheslav Khozikov; Christopher Severns; Benjamin Choi
    2019 AIAA/IEEE Electric Aircraft Technologies Symposium (EATS)
    2019

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    High power inverters will be a key enabler for future aircraft based on hybrid electric or turbo-electric propulsion as envisioned by NASA and Boeing. Cooling a power electronics converter to low temperature, e.g. using cryogenic cooling, can significantly improve the efficiency and power density of a power conversion system. This paper presents the design of a MW cryogenically-cooled power inverter for electric aircraft applications. The power semiconductor and magnetic component characterization, inverter topology and power stage design, modulation and control, EMI noise reduction and filters design, and cooling system design are illustrated. A MW-level inverter prototype has been assembled and tested. The experimental results verify the functionality of the inverter.

  • Gabriel Gabian; Jordan Gamble; Benjamin Blalock; Daniel Costinett
    2018 IEEE Applied Power Electronics Conference and Exposition (APEC)
    2018

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    In this work, a hybrid switched-capacitor/PWM converter is analyzed and designed for battery charging in mobile electronics. Operation of the converter is reviewed to construct a complete analytical loss model based on FET extracted parameters for an integrated circuit implementation. The model is validated with experimental results and compared with other converter topologies in the same application. The loss modeling is used to optimize the physical scaling of the power transistors to minimize total losses.

  • Gabriel Gabian; Benjamin Blalock; Daniel Costinett
    2017 IEEE Applied Power Electronics Conference and Exposition (APEC)
    2017

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    Battery charging circuits for mobile applications, such as smart phones and tablets, require both small area and low losses. In addition, to reduce the charging time, high current is needed through the converter. In order to reduce conduction losses, low on-resistance of the switches is necessary. However, specific resistance (resistance per unit area) is a strong function of the maximum voltage blocking capability of the transistors. To maintain high efficiency and ensure device reliability, the designed breakdown voltage of the transistors needs to include some margin to account for ringing on the switching node. Bond wires add inductance to the power loop increasing the overshoot voltage. In this work the design, implementation and testing of a 40 W CMOS integrated buck converter with an on chip decoupling capacitor are presented. The design was optimized for a 5V to 4V application with a maximum of 2 W on-chip losses at 10 A with an operating frequency of 1 MHz.

  • Gabriel Gabian; Jordan Gamble; Benjamin Blalock; Daniel Costinett
    2017 IEEE 18th Workshop on Control and Modeling for Power Electronics (COMPEL)
    2017

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    This work presents an analytical model for integrated DC-DC converters at high currents. A loss model is constructed using parameters extracted from simulation or are available in the process manual and are scaled with the size of the device. The loss model is used to compare power converter implementations for varying on-chip size and power loss goals. Buck, 3-Level Buck, and Switched-Capacitor topologies are compared using this analytical model and then implemented in a commercial CMOS process. Validation of the constructed loss model is done through hardware measurements.

  • Wen Zhang; Zheyu Zhang; Fred Wang; Daniel Costinett; Leon Tolbert; Benjamin Blalock
    2017 IEEE Applied Power Electronics Conference and Exposition (APEC)
    2017

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    While fast switching brings many benefits, it also presents unwanted ringing during switching transient. In this paper, an increasing magnitude ringing phenomenon is observed during the MOSFET turn-off transient. The unusual phenomenon is replicated in simulation and it is found the MOSFET channel is turned on again after it is turned off. The major cause to this unexpected turn on is found to be common source inductance and a moderate 3 nH one in simulation replicates the severe self-turn-on ringing observed in experiment. This paper reveals the detrimental effect of common source inductance in fast switching. Therefore, Kelvin source connection in circuit and package design is strongly recommended.

  • Yu Long; Weimin Zhang; Benjamin Blalock; Leon Tolbert; Fred Wang
    2014 IEEE Applied Power Electronics Conference and Exposition - APEC 2014
    2014

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    In this paper, an new configurable low-side resonant gate driver circuit based on 5V CMOS process is presented. This gate driver is designed for current Gallium Nitride (GaN) power transistor working up to 10 MHz switching frequency. By updating driving signals and removing off-chip resonant inductors, this gate driver can be working as a conventional non-resonant gate driver. Under resonant gate driving mode, partial of the gate driving power can be recovered to gate driver power supply. Simulation shows up to 30% of gate driving power dissipation reduction can be achieved while driving a single device compared with conventional push-pull gate drivers. We also try to implement a resonant gate driver in a resonant converter. Simulation also shows a similar gate driver power saving is also achieved in a 48-12V LLC resonant DC-DC converter.

  • Xiaoyan Yu; Ethan Farquhar; Ben Blalock
    2010 53rd IEEE International Midwest Symposium on Circuits and Systems
    2010

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    This work describes a novel frequency based current to digital converter, which is fully realizable on a single chip. This project affords an extremely low power converter technology that is also very space efficient. The converter is completely asynchronous which yields ultra-low power during standby operation (approximately 5 nW). The input current range is programmable, and the minimum detectable current could reach the range of picoampere or even lower. System structure, operational principle, and chip test results are given in this paper.

  • Ryan M. Diestelhorst; Steven Finn; Laleh Najafizadeh; Desheng Ma; Pengfei Xi; Chandradevi Ulaganathan; John D. Cressler; Ben Blalock; Foster Dai; Alan Mantooth; Linda Del Castillo; Mohammad Mojarradi; Richard Berger
    2010 IEEE Aerospace Conference
    2010

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    This paper describes the design, implementation, and characterization of a monolithic charge amplification channel for use as a piezoelectric sensor front-end in extreme environment applications. 12The design leverages a 50 GHz peak-fT SiGe BiCMOS technology platform to achieve functionality across a wide-temperature range from -180°C to 120°C. As part of a much larger remote electronics unit, the channel is specified to amplify piezoelectric transducer signals with frequencies up to 5 kHz and amplitudes as low as 200 pC. Intended for use in lunar surface systems, the application requires the capability to absorb up to 100 krad(SiO2) of total ionizing dose (consistent with a typical lunar mission cycle) and be hardened against latch-up effects that cause system failure in a heavy ion radiation environment. Preliminary characterization of the channel shows the desired integration of an AC current input, programmable gain, and effective filtering at three distinct cutoff frequencies.

  • S.K. Islam; S.A. Eliza; N.D. Bull; T. Rahman; B. Blalock; L.R. Baylor; M.N. Ericson; W.L. Gardner
    2009 22nd International Vacuum Nanoelectronics Conference
    2009

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    This paper presents a precision control circuit for the emission of desired number of electrons from vertically aligned carbon nanofibers (VACNFs) for the realization of a massively parallel maskless e-beam lithography system.The digitally addressable field emission arrays (DAFEAs) of the VACNFs function as the lithography heads for massively parallel e-beam exposure of resist eliminating the cost of photomasks.

  • Vinesh Sukumar; Fadi Nessir Zghoul; Mahmoud Alahmad; Herbert Hess; Kevin Buck; Harry Li; Dave Cox; Jeremy Jackson; Stephen Terry; Ben Blalock; M.M. Mojarradi; W.C. West; J.F. Whitacre
    2009 IEEE International Symposium on Industrial Electronics
    2009

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    Integrated microbatteries are being currently developed to act as a ldquomicropowerrdquo source in microsatellites. They help provide localized current capacities or embedded power supplies at the chip level, for space exploration. These power cells are designed to be rechargeable. This research paper aims at presenting charging these power cells using pulsing algorithms developed at MRCI with an on chip pulse charger controller.

  • Yuan Chen; Mohammad Mojaradi; Nazeeh Aranki; Ehsan Kazemian; Robert Grogan; Elizabeth Kolawa; Benjamin Blalock; Robert Greenwell; Lynett Westergard
    2008 IEEE Aerospace Conference
    2008

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    In this paper, we present a methodology for design and qualification of microelectronics for low temperature applications, which has enabled the successful infusion of a custom designed Operational Amplifier into flight mission. The Op-Amp was designed to target a wide temperature range of -150degC to +125degC for at least 5 years operation for Mars Mission. The design and qualification methodology developed have provided the critical path for the technology infusion.

  • Richard Berger; Laura Burcin; David Hutcheson; Jennifer Koehler; Marla Lassa; Myrna Milliser; David Moser; Dan Stanley; Randy Zeger; Ben Blalock; Mark Hale
    2008 IEEE Aerospace Conference
    2008

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    A highly integrated system-on-chip is currently in development. Based on the flight-proven RAD6000™ microprocessor, this mixed-signal microcontroller supports a wide variety of standard digital interfaces commonly used in spacecraft avionics. Multiple analog input and output channels are also provided. This paper will discuss the RAD6000mc architecture, porting of the RAD6000 processor into a reusable core, development of the analog circuitry and analog control interface core, and various applications for which the RAD6000MC is well matched.

  • Richard Berger; Raymond Garbos; John Cressler; Mohammad Mojarradi; Leora Peltz; Ben Blalock; Wayne Johnson; Guofu Niu; Foster Dai; Alan Mantooth; Jim Holmes; Mike Alles; Patrick McClusky
    2008 IEEE Aerospace Conference
    2008

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    A data acquisition system is being developed for use on the NASA Lunar-Mars series of missions. The unit will accept inputs from multiple types of sensors, employing three types of input channels that each incorporate programmable elements to accommodate a wider variety of input signals. Based in part on a subsystem called the remote health node (RHN) that was originally developed during the 1990s for use on the now-defunct NASA X-33 "space plane", the remote electronics unit (REU) is being developed using a 0.5 micron silicon germanium (SiGe) BiCMOS technology from IBM with a circuit library that has been designed to operate normally across a temperature range from -180 degrees C up through +125 degrees C.

  • Yuan Chen; Mohammad Mojarradi; Lynett Westergard; Nazeeh Aranki; Elizabeth Kolawa; Benjamin Blalock
    2008 IEEE International Reliability Physics Symposium
    2008

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    A case study is presented applying a design-for-reliability methodology to design, fabricate and qualify a quad rail-to-rail operational amplifier for the wide temperature range operation of -140degC to +125degC to for space applications. The design-for-reliability approach was developed and implemented from transistor level up to board/system level, along with a comprehensive qualification procedure for the wide temperature range. The quad op-amp is used for a flight mission and available from a commercial production line.

  • Jamie S. Laird; Leif Scheik; Testuo Miyahira; Mohammad M. Mojarradi; Benjamin Blalock; Robert Greenwell; Gyorgy Vizkelethy; Philippe C. Adell; Farokh Irom; Barney Doyle
    2007 9th European Conference on Radiation and Its Effects on Components and Systems
    2007

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    The next generations of Martian rovers are to examine the polar regions where temperatures are extremely low and the absence of an earth-like atmosphere results in a plethora of radiation issues including Analogue Single Event Transients. To this end, a radiation-hardened, temperature compensated CMOS Single-On-Insulator operational amplifier was designed and fabricated using Honeywell's SOI V process. Broad beam heavy-ion tests at the University of Texas A&M were performed to ascertain the duration and severity of any SET's for low and high gain application. Ambiguity regarding the location of transient formation required the use of an ion microbeam to confirm a region of major concern in the internal bias circuitry.

  • S. A. Eliza; S. K. Islam; T. Rahman; R. Vijayaraghavan; T. Grundman; B. Blalock; S. J. Randolph; L. R. Baylor; T. S. Bigelow; W. L. Gardner; M. N. Ericson; J. A. Moore
    2007 International Semiconductor Device Research Symposium
    2007

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    Field emission (FE) of electrons from nanostructured graphitic carbon-based materials has been an area of intense investigation in recent years. Each field emitting device has control gates and an electron emitting cathode, which emits electron when a sufficient voltage is applied at the gate electrode. Recently, a technique for fabricating gated cathode structures that uses a single in situ grown vertically aligned carbon nanofiber (VACNF) as a FE element has been reported. This paper presents digitally addressable VACNFs for implementation of massively parallel maskless lithography.

  • K. Akarvardar; S. Chen; J. Vandersand; B. Blalock; R. Schrimpf; B. Prothro; C. Britton; S. Cristoloveanu; P. Gentil; M.M. Mojarradi
    2006 IEEE international SOI Conferencee Proceedings
    2006

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    A novel voltage-controlled negative differential resistance device, using complementary SOI four-gate transistors (G4-FETs) is presented. Innovative LC oscillator and Schmitt trigger circuits based on the G4-FET NDR device are experimentally demonstrated

  • K. Akarvardar; B. Blalock; S. Chen; S. Cristoloveanu; P. Gentil; M. M. Mojarradi
    2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings
    2006

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    Novel G4-FET based logic-circuits (adjustable-threshold inverter, real-time reconfigurable logic gates and DRAM cell) are experimentally demonstrated. The independent action of the four gates helps minimize the required transistor count per logic function while enhancing design flexibility

  • T. Rahman; S.K. Islam; R. Vijayaraghavan; T. Gundman; S.A. Eliza; A.B.M.I. Hossain; B. Blalock; L.R. Baylor; T.S. Bigelow; M.N. Ericson; W.L. Gardner; J.A. Moore; S. J. Randolph
    2006 19th International Vacuum Nanoelectronics Conference
    2006

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    This paper discusses the complete integration of the prototype digital electrostatic focused e-beam array direct-write lithography (DEAL) device with the dose control circuitry (DCC). The DCC regulates charge emission from the vertically aligned carbon nanofibers (VACNFs) and prevents resists from being over exposed during the e-beam lithography process. The emission of electrons from the VACNF tip requires relatively high voltage. The I-V characteristic of a typical VACNF based device is presented with threshold voltage of ~75 V. The DCC built using a standard 5 V digital CMOS process cannot handle such voltage levels

  • C.D. Tudryn; B. Blalock; G. Burke; Yuan Chen; S. Cozy; R. Ghaffarian; D. Hunter; M. Johnson; E. Kolawa; Mohammad Mojarradi; D. Schatzel; A. Shapiro
    2006 IEEE Aerospace Conference
    2006

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    This paper presents a survivability and reliability investigation for integrated actuator and brushless motor drive electronics packaging and components under an extreme low temperature and high thermal cycle environment. A universal brushless motor drive electronics assembly has been designed, built, and thermal cycle tested for use in Mars, Moon, and asteroid type cold environments without the need for any active thermal control. The assembly uses electronic part types and chip-on-board electronic packaging technology that allow operation at temperatures down to -180degC. The thermal cycle capability of the assembly has been demonstrated to be in excess of 2010 cycles from -120degC to 85degC, over a 210degC total temperature swing. Future space missions will require electronic and actuator systems on a planet, asteroid or Moon surface to function beyond the established reliability limits of currently used components and materials systems. In support of this target application, the Jet Propulsion Laboratory (JPL) has performed a series of experiments to test the reliability of actuators, sensors, electronic components, and electronic packaging designs to provide input to the detailed flight design of a universal brushless motor drive electronics and integrated actuator assembly. These experiments started with the use of a chip-on-board electronic packaging strategy due to its inherent advantage of improved high functionality with minimal circuit board area compared with standard packaged electronic components. Initial electronic packaging experiments were comprised of various sized chip devices with gold wire bonds. The second phase of electronic packaging experiments conducted at JPL consisted of power devices with large diameter wire bonds as well as various surface mount resistor devices. Full factorial experiments were designed to find the most reliable combinations of substrate type, component attach method and encapsulation. The surviving material combinations after a minimum of 1500 thermal cycles were utilized to form the basis of the packaging and electronic component detailed design approach used in the universal brushless motor drive electronics design. Electrical failures were defined as open circuits. A failure analysis procedure was applied by defining the failure mechanism and applying a risk mitigation. After 1500 cycles, the packaged assembles were cycled to exceed 2010 cycles and additional material considerations were made. In addition, selected components were functionally tested over the temperature range of +100degC to -180degC and cold soaked at -150degC for 1000 hours for reliability. A design for reliability method was also developed at the component and circuit level for electronics operating at extreme low temperatures

  • Steven Ripp; Scott Moser; Brandon Weathers; Sam Caylor; Benjamin Blalock; Syed Islam; Gary Sayler
    2006 Bio Micro and Nanosystems Conference
    2006

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    Bioluminescent bioreporter integrated circuits (BBICs) are hybrid microluminometer/whole-cell reporter sensor devices for monitoring target chemical and biological agents. The integrated circuit portion of the biosensor consists of a 0.35mum complementary metal oxide semiconductor (CMOS) photodiode capable of low level light detection within an approximate 2.25 mm2 footprint. Interfaced to it is a population of bioreporter microorganisms genetically engineered to specifically and reproducibly respond to desired analytes through autonomous, quantitative emission of luxCDABE-based bioluminescent light signals. The microluminometer chip detects these signals, processes them, and communicates the results either through cable or wireless interconnects for distributed biosensing. In addition, BBIC chips can be outfitted with auxiliary functions such as time stamping, positional sensing, or temperature measurement to provide a more thorough profile of the environment in which it is operating. Our existing laboratory set-up places the BBIC in-line with a liquid or air flow-through system for continuous online monitoring. A remote BBIC has also been developed for static monitoring in either liquid or vapor phase. Detection limits for tested bioreporters approach part-per-billion levels with response times of less than one hour. In progress evolution of BBIC design using nanostructured arrays of vertically aligned carbon nanofibers may permit multiplexed detection of chemical and biological agents in a single chip format

  • S. K. Islam; W. Qu; R. Vijayaraghvan; S.C. Terry; M. Zhang; B. Blalock; S. Caylor; S. Ripp; G. S. Sayler
    2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings
    2006

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    An integrated CMOS microluminometer for detection of very low-level bioluminescence is presented. Signal processing is accomplished with a current-to-frequency converter circuit. Photodiode, integrator, voltage reference circuit and noise are analyzed in detail in this paper. The biosensor chip was fabricated using a standard 0.35mum CMOS process and dissipate 3 mW for 3.3 V power supply. Test results are given to prove the concept

  • S.K. Islam; B. Weathers; S.C. Terry; M. Zhang; B. Blalock; S. Caylor; S. Ripp; G.S. Sayler
    Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.
    2005

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    We report a biosensor using genetically-engineered whole-cell bioreporters on integrated circuit for low-level chemical sensing. The bioluminescent bioreporters are bacteria that can be genetically altered to achieve bioluminescence when in contact with a targeted substance. The bioreporters are placed on a microluminometer. The microluminometer includes integrated photodetector and signal processor and is realized on a standard CMOS process. The bioluminescent bioreporter integrated circuit (BBIC) can detect luminescence from as few as 5000 fully induced pseudomonas fluorescene 5RL bacteria cell.

  • S.K. Islam; C. Durisety; R. Vijayaraghavan; H. Nguyen; B. Blalock; L.R. Baylor; W.L. Gardner
    2005 International Vacuum Nanoelectronics Conference
    2005

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    This paper presents a prototype implementation of a circuit that can control charge emission from the vertically aligned carbon nanofibers (VACNF), for use in the implementation of digital electrostatic e-beam array lithography (DEAL). This lithography technique can be used to fabricate ultra-small feature size devices, while cutting down the manufacturing costs of photomasks. These VACNF's are found to be quite robust for use as micro-fabricated field emission devices. The all inverter based dose control circuit (DCC) presented in this paper was fabricated using a standard 0.5 /spl mu/m CMOS process to improve the dose-rate accuracy, when using these VACNF's for etching in maskless lithography. Simulation and measurement results are compared and analyzed, and future work for improving the design is discussed.

  • L.R. Baylor; W.L. Gardner; X. Yang; R.J. Kasica; B. Blalock; C. Durisety; J. Fowlkes; D.K. Hensley; S. Islam; D.C. Joy; A.V. Melechko; P.D. Rack; S.J. Randolph; R. Rucker; D.K. Thomas; M.L. Simpson
    2005 International Vacuum Nanoelectronics Conference
    2005

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    Prototype field emission devices have been fabricated in the 300-1000 eV range using vertically aligned carbon nanofibers as the field emitter. The devices are fabricated using a self-aligned process for the extraction gate opening and the focus grid opening is defined lithographically. Field emission tests of the completed devices are carried out in a vacuum chamber with a phosphor anode and show that the emission follows Fowler-Nordheim characteristics. A technique to selectively grow fibers with W in digitally addressable field-emission array (DAFEA) prototype devices is demonstrated by nanoscale electron beam induced deposition (EBID). A non-organometallic precursor, WF/sub 6/, is used to deposited metallic W fibers. Vacuum electrical testing revels that electrons are successfully extracted from the W nanofiber tip and have been used to draw lines in PMMA coated glass substrates in the DEAL lithography testbed. This growth technique can be used to repair DAFEA emitters thus providing a means to produce a reliable massive parallel e-beam write head.

  • James Vandersand; Vadim Kushner; Jinman Yang; Benjamin Blalock; Trevor Thornton
    2005 IEEE Aerospace Conference
    2005

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    Silicon-on-insulator MESFETs have been manufactured using a commercial SOI CMOS process and their electrical characteristics measured from room temperature up to 200deg C. No modifications were made to the CMOS process flow. The prototype devices use a CoSi2 gate material and the gate current follows the expected Shottky diode behavior. At room temperature a 0.6 mum gate length device has a threshold voltage of -0.8 V with an off-state drain current of approximately 5 nA. The device shows an attractive family of I-V curves up to 200deg C. For higher temperatures the reverse diode current makes it hard to switch the device off. Numerical simulations of a similar device with a higher barrier height PtSi gate show reasonable behavior up to 300degC

  • M.M. Mojarradi; R.S. Cozy; Yuan Chen; E.A. Kolawa; M. Johnson; T. McCarthy; G.C. Levanas; B. Blalock; G. Burke; L. Del Castillo; A.A. Shapiro
    2004 IEEE Aerospace Conference Proceedings (IEEE Cat. No.04TH8720)
    2004

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    Commercial-off-the-shelf electronic components (COTS) offer a very low cost and attractive solution for construction of electronic systems for Mars missions, including the actuator electronic systems for the Mars Rovers. One issue with using COTS lies in the difference between their specified operating temperature range (-55/spl deg/C to125/spl deg/C for military components) and the temperatures observed at the surface of Mars (-120/spl deg/C to 20/spl deg/C). To compensate for the difference between these temperatures, most of the electronics are placed in a central warm-electronics-box or WEB. In some cases, such as the distributed control system for the actuators, the electronic assemblies that are to be placed on or near the motors are outside of the central WEB. The experimental search consists of two steps. First, a short functional/non-functional test at -120/spl deg/C is used to identify and narrow down the number of candidate COTS that can work at very cold temperatures. More extensive characterization of the parts that passes the short test is performed to determine the operating margins and estimate the thermal cycle life capability for the COTS parts. Finally, the operating margins of the COTS parts are published as a set of specifications.