The accurate control of negative sequence (NS) current distribution among multiple grid-forming (GFM) sources can lower the requirement on NS current capability of the sources. Existing control approaches mainly focus on microgrids (MGs) with fixed points of common couplings and on only the NS current distribution among inverter-based resources (IBRs). As MG configuration has been rapidly evolving to be more complicated, it is critical to take into consideration the impact of MG topologies on the NS current sharing. Moreover, synchronous generators (SGs) are still commonly applied as sources in MGs. The NS current distribution among IBRs and SGs also needs to be considered. In this paper, a novel NS impedance design and regulation approach is proposed to achieve accurate and flexible NS current sharing among different GFM sources (IBRs and SGs). The approach accounts for MG topology impacts by including MG's NS admittance matrix in the impedance design. The effectiveness of the proposed approach is evaluated through simulations and compared to existing solutions in a MG with four different source locations. Results show improved flexibility and accuracy in NS current sharing when MG topology impacts are considered. The proposed approach is also validated through experimental testing on a converter-based hardware testbed.

Substantial differences in fault levels between grid-tied and islanded modes is one of the primary challenges of microgrid protection. During grid-tied mode, the bulk grid provides significant short-circuit, while during islanded operation the short-circuit magnitude is small due to inverter-based resources limiting their current output close to nominal ratings. Consequently, conventional distribution protection strategies based on overcurrent cannot reliably protect microgrids when operating in islanded mode. Fuses and circuit breakers are particularly affected because of their inverse characteristics. Presently, the absence of affordable solutions for protecting microgrids in islanded mode leads to microgrids shutting down during electrical faults. The contribution of this article is two-fold. The first innovation proposes specific hardware modifications to grid-forming inverters to increase their short-circuit current during electrical faults. The second innovation introduces a novel control strategy designed to preserve control stability margins even when the grid-filter saturates, ensuring sinusoidal output currents under normal and fault conditions. Through experimental results, the inverter with the proposed modifications can provide more than three-times its nominal current during electrical faults. For the prototype testbed, this was sufficient to enable the use of traditional legacy overcurrent protection, achieving the fuse-to-relay and relay-to-relay minimum coordination time for the line-to-ground, line-to-line to ground, and three-phase electrical faults.

Inverter-based resources (IBRs) introduce fast dynamics and high non-linearities to microgrids, degrading their stability and complicating the design of effective controllers. To address the arising vulnerability and non-linearities, this paper presents a systematic controller design approach that ensures large-signal stability and domain of attraction (DOA) for islanded microgrids. First, the nonlinear electromagnetic transient model of inverter-based microgrids is developed in the rotating dq reference frame, which is then transformed to a homogeneous-like system with nonlinear terms acting as superimposed parameter uncertainties. Next, the stability conditions, including certified stability, certified DOA, and their combination, are derived to rigorously guarantee a designated range to be a subset of DOA. The designated region is customized and flexible enough to cover microgrids’ normal or emergency operational ranges, such as low- and high-voltage ride-through (L/HVRT) conditions. Then, a systematic method for identifying the candidate control parameter set is developed by integrating the analytical stability conditions. This approach is further exemplified in the droop controller design to improve microgrid stability and resilience. Finally, the proposed systematic controller design is verified through numerical simulation and power hardware-in-the-loop experiments to ensure large-signal stability and DOA of microgrids in emergency L/HVRT conditions.

The output power of an ocean wave energy (WE) system has an intermittent and stochastic characteristic. WE output power can be transferred to the grid without sudden fluctuations when combined with a hybrid energy storage system (HESS) consisting of a battery pack and an ultracapacitor (UC) module. The study presented in this paper identifies the lowest-cost HESS sizing for WE systems by using a genetic algorithm (GA) optimization method. In this study, the system cost was reduced with the HESS cost and sizing study for ocean WE converter systems, and the battery was used effectively for a longer cycle. GA optimization has been applied in the field of HESS in ocean WE systems and has brought innovation to the literature with its optimum cost and sizing study. An optimum design model is presented considering the maximum/minimum voltage and current limits and the energy storage units’ temperature and depth of discharge parameters. The series and parallel connection calculations and the required number of battery and UC cells are given in the sizing section. The GA optimization was performed in MATLAB, and the energy storage rate for the 625-kW system and the power and energy results of the energy storage units were given as a result of the optimum cost analysis.

Electric vehicles (EVs) can provide power to the grid or buildings similar to distributed energy resources (DER) for energy balancing applications or optimizing the operation of the microgrids in harmony with the other DER assets. This paper presents the operating modes of a bidirectional wireless power transfer (WPT) system designed for a medium-duty package delivery vehicle. The WPT system designed for this study can transfer 20 kW of power across 11 inches of airgap using custom-designed double-D (DD) couplers with LCC-LCC tuning networks. The proposed system utilizes a 480 V 3-phase grid connection, a plug-in hybrid delivery truck with bidirectional WPT, and a stationary energy storage system (SESS) that can be connected to the primary-side dc link. Due to the differences in primary and secondary dc bus voltages; and considering the voltage of the SESS, asymmetric voltage gains were used in the system. Sensitivity analyses of this system with respect to these voltage levels are presented. Five different operating modes of the grid, SESS, and the EV battery are investigated with experimental results. Control algorithms are described for grid-to-vehicle (G2V) and vehicle-to-grid (V2G) operating modes. A bidirectional WPT system is operated with a power factor of 0.99 on the grid side in every operating mode. The EV battery was charged with 20.3 kW with an overall efficiency of 93.02% in the G2V operating mode. In V2G operating mode, the WPT system provided 12.82 kW of power back to the grid with an overall efficiency of 89.08%.

This article presents a desat protection scheme with the ultrafast response for high-voltage (>3.3 kV) SiC MOSFETs. Its working principle is the same as the conventional desat protection designed for high-voltage SiC MOSFETs, yet its blanking time is implemented by fully considering the influence of high negative dvds/dt during the fast turn-on transient. With the same circuitry as the conventional desat protection, the proposed protection scheme can significantly shorten the response time of the desat protection when it is used to protect high-voltage SiC MOSFETs. In addition, the proposed protection scheme with ultrafast response features strong noise immunity, low-cost, and simple implementation. By taking advantage of the high dv/dt during the normal turn-on transients, the proposed protection scheme can be even faster when the MOSFET has a faster switching speed. Design details and the response speed analysis under various short circuit faults are presented in detail. A half bridge phase leg based on discrete 10 kV/20 A SiC MOSFETs is built to demonstrate the proposed protection scheme. Experimental results at 6.5 kV validate the ultrafast response (115 ns response time under a hard switching fault, 155 ns response time under a fault under load), and strong noise immunity of the proposed desat protection scheme.

Due to multiple operation modes and corresponding mode transitions of microgrids (MGs), the MG grounding design is challenging. An MG may lose its grounding provided by the main distribution grid when it transitions to the islanded operation, resulting in potential hazards to both equipment and personnel. Existing transformer-based grounding schemes are bulky and have low control capability, which leads to poor transition performances and may affect the operation and protection of the whole distribution grid in the grid-connected mode. Power inverters have been applied as interfaces of distributed energy resources (DERs), which can potentially serve as groundings for future MGs. In this article, a novel DER inverter-based MG grounding scheme is proposed to realize flexible grounding in MGs. The detailed grounding structure and control methods are discussed. The proposed grounding scheme is verified on a realistic MG model through simulation. The proposed control strategies are demonstrated on a converter-based hardware testbed.

A microgrid (MG) may lose its grounding provided by the main distribution grid in islanded mode, which could cause equipment insulation damage, hazards to personnel, and protection malfunction. Existing MG grounding schemes include the grounding transformer-based scheme and distributed energy resource (DER) transformer-based scheme. However, the grounding transformer-based scheme will increase MG’s cost, and the DER transformer approach will affect the main grid in the grid-connected mode. Moreover, future MGs may have multiple source locations. In each source location, the source and critical load can potentially operate as a sub-MG, requiring a grounding when it stands alone. In this scenario, the drawbacks of existing grounding schemes will be further magnified. In this paper, a novel controllable DER transformer-based grounding scheme is proposed, where a controllable switch is added to the neutral wire of the transformer. The proposed scheme can disable grounding capability in the grid-connected mode and enable it in the islanded mode by changing the transformer connection. The proposed approach can avoid impacts on the main distribution grid and eliminate the need for additional transformers. The design methodology of the proposed grounding scheme is provided. Simulation verification is conducted on a realistic MG model and experimental verification is conducted.

This article proposes a high-efficiency single-phase GaN-based rectifier with reactive power transfer for use in front-end power supplies as an efficient alternative to centralized reactive power compensation. A full-range zero-voltage switching (ZVS) modulation for both unity power factor (PF) operation and nonunity PF operation is proposed for the GaN-based rectifier in critical conduction mode (CRM) operation. A frequency limitation method is also developed to limit the peak frequency during the ac current zero-crossing. Also, a GaN-based T-type totem-pole rectifier is proposed to overcome the control challenge in CRM during the ac voltage zero-crossing. Meanwhile, a digital-based control scheme is developed to implement ZVS operation and reactive power regulation. The proposed rectifier and ZVS control have the advantages of simple topology, high efficiency, straightforward control implementation, and capability of flexible reactive power regulation. A 1.6-kVA prototype of the GaN-based CRM T-type totem-pole rectifier is built and demonstrated with full-range ZVS operation, 98.9% full-load efficiency, and flexible reactive power regulation with smooth dynamic response.

While the employment of wide bandgap (WBG) devices in high-frequency and high-voltage applications brings benefits such as reduced system size and improved efficiency, it aggravates the electromagnetic interference (EMI) issue due to fast switching. High-frequency EMI noise suppression relies mainly on the filter design, where the filter's performance is strongly affected by parasitics. Through analyzing the common-mode (CM) equivalent circuit of a half-bridge power module, this letter identifies the key parasitics that dominate the performance of a common-mode filter (CMF) at high frequencies. To minimize the parasitics, the concept of integrating the CMF inside the WBG power module package is developed to improve the noise attenuation. A π-type CMF is integrated with a half-bridge GaN-based power module as a prototype to validate the concept. Experiments are conducted by measuring the CM noise spectrum received by the line impedance stabilization networks (LISNs) from the hard switching of the designed power module under 70 V and 80 kHz. Comparing the measured results of the integrated CMF to the externally-added CMF, up to 50 dBμV more attenuation is achieved by the integrated CMF in the frequency range of 10 MHz to 100 MHz, verifying the theoretical analysis and the established CM equivalent circuit.

Lateral gallium nitride (GaN) high-electron-mobility transistors (HEMTs) present better electrical characteristics compared to silicon or silicon carbide devices such as high switching speed and low gate charge, but also present additional challenges on the module design. This paper discusses a high-density GaN power module with double-sided cooling, low inductance, on-package decoupling capacitors, and integrated gate drivers. The GaN dies as well as the gate drive are sandwiched between the printed circuit board (PCB) and direct bonded copper (DBC) substrate to achieve compact loop and double-sided cooling effect. Design considerations and thermal performance are analyzed. A module assembly procedure is presented utilizing the layer-by-layer attachment process. Finally, a 2.7 cm × 1.8 cm half-bridge GaN power module is fabricated and tested, achieving a low power-loop inductance of 1.03 nH, and the overshoot voltage of the switching waveform is less than 5% under a 400-V/25-A double-pulse test. The thermal resistance is 0.32 K/W, verified by simulation and experimental results. The design and assembly process can be generalized and applied to high power applications to achieve high power density and high performance.

The increasing penetration of inverter-based resources (IBRs) calls for an advanced active and reactive power (PQ) control strategy in microgrids. To enhance the controllability and flexibility of the IBRs, this paper proposed an adaptive PQ control method with trajectory tracking capability, combining model-based analysis, physics-informed reinforcement learning (RL), and power hardware-in-the-loop (HIL) experiments. First, model-based analysis proves that there exists an adaptive proportional-integral controller with time-varying gains that can ensure any exponential PQ output trajectory of IBRs. These gains consist of a constant factor and an exponentially decaying factor, which are then obtained using a model-free deep reinforcement learning approach known as the twin delayed deeper deterministic policy gradient. With the model-based derivation, the learning space of the RL agent is narrowed down from a function space to a real space, which reduces the training complexity significantly. Finally, the proposed method is verified through numerical simulation in MATLAB-Simulink and power HIL experiments in the CURENT center.With the physics-informed learning method, exponential response time constants can be freely assigned to IBRs, and they can follow any predefined trajectory without complicated gain tuning.

Misaligned and/or variable coil airgaps cause coupling coefficient variation in wireless power transfer (WPT) systems, resulting in a decrease in the system’s transmitted power and efficiency. This paper presents sensitivity analyses of a three-phase, Y-Y connected, series-tuned WPT system in the frequency domain in terms of several different electric vehicle wireless charging off-nominal conditions (misalignments in Δx and Δy directions, change of airgap Δz, and the roll Δψ, pitch Δθ, and yaw ΔΦ angles) as specified in Society of Automotive Engineers (SAE) J2954 Standard. Coil inductance matrices were obtained by measuring the self- and mutual inductances of the primary and secondary coil phase windings at variable airgap classes (from 5 cm to 30 cm) for five different charging positions as identified in SAE J2954. These 6 × 6 inductance matrices were used in sensitivity and Plexim/PLECS simulation analyses. The sensitivity of the WPT system was analyzed analytically using the input impedance and phase angle, voltage gain, current gain, quality factor, and coupling coefficient parameters of the series-tuned WPT system. The results were confirmed experimentally on a 50 kW WPT system.

The amount of electricity generation from renewable energy resources (RES) has been increasing significantly all over the globe. However, traditional power grid management is challenged when a large amount of intermittent and unpredictable RES-based generation units are integrated into the power network. This can lead to more severe grid frequency fluctuation events. In this paper, a variable speed drive (VSD) based motor load is utilized as a frequency responsive load to support grid frequency stability. A primary frequency control scheme is proposed and applied to the VSD-based motor load, which incorporates the sophisticated rotating speed feedback controller. Additionally, the proposed frequency responsive VSD-based load is modeled and simplified. As a result, a droop-like response can be achieved with multiple VSD load units. The effectiveness of the proposed model and control scheme is evaluated by experimental studies performed in a multi-converter-based hardware testbed (HTB).

Three-phase four-leg four-wire (3P4L4W) three -level (3L) inverters have the ability to supply both balanced and unbalanced loads. This letter establishes common-mode (CM) and differential-mode (DM) circuit models for the 3P4L4W 3L inverter. It is revealed that the 3L phase-leg CM voltage is determined by the voltage balancing control (VBC) for the split dc bus voltages, that the DM load voltages are subject to the DM voltage control for the 3L phase leg, and that the CM load voltage is subject to the control for the fourth phase leg. On this basis, a decoupled modulation is proposed where the 3L phase legs are modulated to attain VBC and closed-loop DM load-voltage control, whereas the fourth phase leg is independently modulated to realize the closed-loop CM load-voltage control. The proposed work has been experimentally verified, showing that the 3P4L4W 3L inverter with this decoupled modulation scheme can provide well-balanced ac load voltages and low total harmonic distortion for any type of ac loads: balanced, unbalanced, linear, and nonlinear.

Data centers have become a widespread power electronics (PE) load, which has significant impact on the power grid. In order to investigate the data center load characteristics, this article proposes a complete dynamic model for a typical data center ac power distribution system. A generalized model with mode transition is proposed to coordinate different power stages in the data center power system. Meanwhile, to help evaluate the grid dynamic performance and transient stability, an all-in-one load data center power emulator is developed on a reconfigurable PE converter-based hardware testbed (HTB). The dynamic power model is digitized and simplified to be implemented in two local voltage source inverters on the HTB. This proposed data center power emulator has been verified experimentally in a regional network. Dynamic performances during voltage sag events and server load variations are emulated and discussed. The article details the design, development, and verification of the data center model and power emulator. The proposed model and emulator provide an effective, easy-to-use tool to better design data centers and study the interaction with the power system.

This paper comprehensively analyzes desaturation (desat) protection for high voltage (>3.3 kV) silicon carbide (SiC) MOSFETs and especially how to build in noise immunity under high dv/dt. This study establishes a solid foundation for understanding the trade-offs between noise immunity and response speed of desat protection. Two implementations of the desat protection for high voltage SiC MOSFETs are examined, including desat protection based on discrete components and desat protection realized with a gate driver integrated circuit (IC). Both positive dv/dt and negative dv/dt are investigated. Analysis results show that the high dv/dt with long duration caused by high voltage SiC MOSFETs’ switching results in strong noise interference in the desat protection circuitry. The impact of numerous influencing factors is investigated analytically, such as parasitic capacitances, parasitic inductance, damping resistance, and clamping impedance. Under high positive dv/dt, extremely small parasitic capacitances (<0.01 pF) between the drain terminal and protection circuitry could still compromise noise immunity of the desat protection circuitry that has a high-impedance voltage divider. Comprehensive design guidelines are summarized to boost the noise immunity, including circuit design, component selection, and PCB layout. The noise immunity margin under the positive dv/dt is also derived quantitatively to guide the noise immunity improvement. The noise immunity analysis results and noise immunity improvement methods are validated with simulation and experimental results obtained from a phase leg based on 10 kV/20 A SiC MOSFETs.

To accelerate the dynamic response in a dual active bridge converter, feed-forward control can be applied in parallel to the conventional PI controller for closed-loop control. The transformer current thus changes significantly due to the phase shift change. A current spike can appear during load transients, particularly when using multiple phase shift modulation. Effort has been made in the previous literature to implement active compensation between two different steady-state operations to eliminate the transformer current spike; however, this results in a complicated control structure. This letter thus proposes a novel modulation method unifying the transformer current for dual phase shift and triple phase shift modulation to mitigate the transformer current spike when switching among various phase shift controls during load transients. By applying the proposed pulsewidth modulation strategy, the instantaneous value of the transformer current stays the same at the beginning of the switching period even with different steady-state modulation techniques. Also, full-operation-range zero-voltage switching can be realized for the primary side or the secondary side switches by combining with the proposed modulation strategy. An experimental prototype demonstration validates the proposed modulation strategy.

Non-utility owned distributed energy resources (DERs) are mostly untapped currently, but they can provide many grid services such as voltage regulation and service restoration, if properly controlled, and can improve the distribution system's reliability when coordinated with utility-owned assets such as self-healing control and microgrids. This paper integrates transactive energy control into the distribution system reliability evaluation to quantitatively assess the impact of non-utility owned DERs on reliability improvement. A transactive reactive power control strategy is designed to incentivize the DERs to provide reactive power support for improving voltage profiles thus enabling additional customer load restoration during an outage. Also, an operational sequence to coordinate the non-utility owned DERs with the utility owned self-healing control and utility owned microgrids is designed and integrated into the service restoration process with the operational constraints guaranteed by checking the three-phase unbalanced power flow for post-fault network reconfiguration. The reliability indices are then calculated through a Monte Carlo simulation. The transactive reactive power control strategy is tested on a four-feeder distribution system operated by Duke Energy in the U.S. Results demonstrate that the non-utility owned DERs with the transactive control improve the reliability of both the system and critical loads by more than 30%.

Distributed energy resources (DERs) and microgrids have seen tremendous growth and research activities in recent years. Flexible DERs and asynchronous microgrids (ASMG) can have many system-level benefits over fixed DERs and conventional microgrids. The key enabler for flexible DERs and ASMG is a power converter based power conditioning system (PCS) as the interface between DERs/microgrids and the medium voltage (MV) distribution grid. High voltage (HV, >3.3 kV) silicon carbide (SiC) based MV converter is now a promising solution for the PCS. This article presents development and testing of a 10 kV SiC MOSFET based MV PCS for 13.8 kV ASMG. MV PCS converter design addressing high dv/dt issue generated by fast switching of the 10 kV SiC MOSFET is presented. The developed PCS is successfully tested at 25 kV dc 13.8 kV ac voltages and 100 kVA power. Grid support functions are also demonstrated with the developed PCS prototype and hardware tests beds, validating HV SiC converter benefits for ASMG.

The dynamic boundary concept enables more flexible and efficient operation of microgrids with distributed energy resources (DER) that are intermittent in nature. As the integration of renewables continues to accelerate, an adaptive power management module that enables dynamic boundary operations in microgrids with an increasing number of source locations is essential for the fast and low-cost deployment of microgrid controllers. The power management module introduced in this paper is capable of handling the increased complexity in topological variations and transitions stemming from dynamic boundaries and multiple source locations. This includes real-time operation of multiple islands with dynamic boundaries, initiation of topological transitions (merging and separation of islands), and automatic source coordination for power sharing and frequency regulation. All functions in the power management module are designed to be automatically adaptable to arbitrary microgrids with non-meshed topologies so that the deployment of the controller at new microgrid sites can be expedited with a reduced cost. The module has been implemented on NI’s CompactRIO system as an essential part of an MG controller and tested on a converter-based hardware testbed (HTB). Testing results validated the effectiveness of the algorithms under various operating conditions.

Paralleled dies in a power module could have instability issues during high current switching transients. The instability is caused by the differential-mode oscillation among paralleled MOSFETs. Conventional analyses of paralleled MOSFETs’ stability are normally limited to a single operating point, which ignores the influences of the switching trajectory and nonlinear device parameters on stability. This article reveals that the switching trajectory can significantly influence parallel stability. The analysis is improved by solving eigenvalues of state-space modeling system matrices of all operating points that the switching trajectory goes through considering nonlinear device parameters. Higher voltage and current stresses result in greater real parts of complex eigenvalues, which explains why the paralleled MOSFETs are more unstable with higher voltage and current stresses. To improve stability in solid-state circuit breaker applications, we propose a method to manipulate the switching trajectory to avoid the unstable region where the conventional hard switching trajectory normally goes through. Experimental results show that the turn-off current capability can be increased from ∼five times of rated current with the gate oscillation using the conventional turn-off trajectory to ∼ten times of rated current without the gate oscillation using the optimal turn-off trajectory.

Industrial motor systems make up a quarter of all electric sales in the United States. Variable speed drives (VSDs) can provide energy efficiency savings to the customer by regulating motor speed based on specific and varying needs. In addition to the benefits provided to the customer, VSDs can provide support to the grid through ancillary services. The Center for Ultra-Wide-Area Resilient Electric Energy Transmission Networks (CURENT) developed a power electronics converter-based grid emulator to allow testing of various power system architectures and demonstration of key technologies in monitoring, control, actuation, and visualization. This paper proposes using an active front-end VSD's connected motor load to provide frequency regulation to a large scale power grid. Each part of the emulator is described including motor and power electronics model and control. The proposed frequency regulation is implemented in VSDs and modeled in both a transmission system in EMTDC/PSCAD and verified on CURENT's hardware testbed.

This paper proposes a novel continuously variable series reactor (CVSR) based on a dc current controller (DCC) to manage power flow in transmission systems. There are threefold major contributions. First, the three-dimensional electromagnetic interaction has been comprehensively analyzed to extend the understanding beyond the conventional 2D relationship. Second, a high-fidelity reluctance model of the CVSR with an improved DCC model is proposed and implemented. To overcome the fundamental concern for the system modeling, the DCC has been modeled as an ideal current source in parallel with an output impedance. The induced back-EMF can be precisely projected which provides critical design guidelines for the DCC. Third, inspired by the theoretical analysis and modeling, a reliable high power DCC converter is designed accordingly to interface with kV-level back-EMF and supply kA-level dc current for a 115 kV / 1500 A CVSR. Experiments are conducted in a practical transmission demonstration system. When the ac current in the transmission system varies from zero to 1500 A, experimental results show that the proposed CVSR can continuously regulate the reactance from 1.6 Ω to 5 Ω, validating the effectiveness of the proposed system design and modeling methodology.

The modular multilevel converter (MMC) is a popular topology in medium- and high-voltage applications, and many efforts have been spent on MMC modeling. However, the impact of submodule voltage sensor noise (SVSN), which becomes more severe due to increasing switching speed of power semiconductors and compact submodule design, has not been considered in conventional models. In this letter, the SVSN is introduced by coupling capacitances between the sensor and power stage in an MMC switching model. Furthermore, the SVSN impact is considered in an MMC average model based on derivation of the relationship between the SVSN and the duty cycle. The proposed MMC switching model and average model considering the SVSN are validated by comparing simulations with experimental results in an MMC prototype using 10-kV SiC MOSFETS.

The GaN-based critical conduction mode (CRM) totem-pole power factor correction (PFC) converter with full-line-cycle zero voltage switching (ZVS) is a promising candidate for high-efficiency front-end rectifiers. However, the input current can be degraded by line-cycle current distortion and ac line zero-crossing current spikes, and maintaining reliable ZVS control is difficult in noise-susceptible high-frequency environments. In this paper, a detailed analysis of the current distortion issues in a GaN-based CRM totem-pole PFC with digital ZVS control is provided, and effective approaches are proposed to mitigate different kinds of current distortion and ensure stable ZVS control under high-frequency operation. The proposed solutions have the advantages of straightforward implementation and do not increase the control complexity. The current distortion issues are demonstrated in two GaN-based CRM totem-pole PFC prototypes, a 1.5 kW PFC for data centers and a 100 W PFC in a 6.78 MHz wireless charging power supply for consumer electronics. The proposed methods are experimentally verified with effective mitigation of the current distortion and improvement of the converter power efficiency.

A variable speed drive (VSD) based induction motor power emulator is presented in this paper, which is intended to be used in a real-time multi-converter-based hardware testbed (HTB) system. The presented HTB load emulator can accurately reflect the dynamic performance of a VSD-based load with multiple control algorithms without requiring significant computational resources and simulation time. Therefore, the developed VSD load emulator can not only mimic VSD-driven motor load performance, but also can be flexibly integrated into electric power grid emulators or simulators, which enable more detailed power grid analyses by providing a more accurate model for this particular type of load. This paper discusses the specification of the developed VSD-based load emulator, including multiple control schemes, and the physical realization in a power grid emulator. Finally, the accuracy of the VSD load emulator is demonstrated with experimental results.

In contrast with conventional microgrids (MGs) with fixed boundaries, a smart and flexible MG with dynamic boundary is introduced in this paper. Such a MG can dynamically change its boundary by picking up or shedding load sections of a distribution feeder depending on its available power, leading to more flexible operation, better utilization of renewables, smaller size of energy storage system, higher reliability, and lower cost. To achieve a flexible MG, the main challenges in MG design are addressed, including recloser placement, MG asset sizing considering resilience, system grounding design, and protection system design. Meanwhile, a hierarchical structure is employed to design and implement the MG controller. On top of the functions defined in IEEE 2030.7-2018, a few new functions, e.g., online topology identification and PQ balance, are added, while the planned/unplanned islanding and reconnection functions are enhanced. The controller is implemented on a CompactRIO, a general-purpose hardware platform provided by National Instruments (NI), and tested on a controller hardware-in-the-loop setup based on an OPAL-RT real-time simulator and a reconfigurable power electronic converter-based hardware testbed. The test results have validated the performance of the developed controllers. Such a flexible MG and its controller have been deployed at a municipal utility, and part of the controller’s functions have been tested on-site.

Planned islanding is one of the fundamental functions of microgrid (MG) controllers. However, existing planned islanding functions cannot be directly utilized in MGs that have the capability to have both dynamic boundary and multiple sub-MGs. To optimize the smart switch operation and distributed energy resource (DER) output power, a planned islanding algorithm is designed to minimize the battery energy storage systems’ power difference before and after a planned islanding. To verify the performance of the proposed algorithm, a hardware-in-the-loop (HIL) test has been conducted by implementing the algorithm in a general purpose MG controller system. The results demonstrate that the difference in active power before and after the planned islanding decreases significantly with the proposed algorithm.

This article establishes an analytical model for the device drain-source overvoltage related to the two loops in three-level active neutral point clamped (3L-ANPC) converters. Taking into account the nonlinear device output capacitance, two common modulation methods are investigated in detail. The results show that the line switching frequency device usually has higher overvoltage, and the switching speed of the high switching frequency device is not strongly influenced by the multiple loops. By keeping the nonactive clamping switch off, the effect of the nonlinear device output capacitance can be significantly mitigated, which helps reduce the overvoltage. Moreover, the loop inductance can be reduced with vertical loop layout and magnetic cancellation in the printed circuit board and busbar design. A 500-kVA 3L-ANPC converter using silicon carbide mosfets was built and tested. The experimental results validate the overvoltage model of the two modulation methods as well as the busbar design. With the nonactive clamping switch off, the overvoltage of both the high and line switching frequency devices is significantly reduced, which helps achieve higher switching speed.

In order to evaluate the feasibility of newly developed gallium nitride (GaN) devices in a cryogenically cooled converter, this article characterizes a 650-V enhancement-mode GaN high-electron mobility transistor (GaN HEMT) at cryogenic temperatures. The characterization includes both static and dynamic behaviors. The results show that this GaN HEMT is an excellent device candidate to be applied in cryogenic-cooled applications. For example, transconductance at cryogenic temperature (93 K) is 2.5 times higher than one at room temperature (298 K), and accordingly, peak di/dt during turn-on transients at cryogenic temperature is around 2 times of that at room temperature. Moreover, the ON-resistance of the channel at the cryogenic temperature is only one-fifth of that at room temperature. The corresponding explanations of performance trends at cryogenic temperatures are also given from the view of semiconductor physics. In addition, several device failures were observed during the dynamic characterization of GaN HEMTs at cryogenic temperatures. The ultrafast switching speed-induced high di/dt and dv/dt at cryogenic temperatures amplify the negative effects of parasitics inside the switching loop. Based on failure waveforms, two failure modes were classified, and detailed failure mechanisms caused by ultrafast switching speed are given in this article.

To better support the superconducting propulsion system in the future aircraft applications, the technologies of high-power high switching frequency power electronics systems at cryogenic temperatures should be investigated. This article presents the development of a 40-kW cryogenically cooled three-level active neutral point clamped inverter with 3 kHz output line frequency and 140 kHz switching frequency. Si mosfets are characterized at cryogenic temperatures, and the results show that they have promising performance such as lower on-resistance and switching loss. The design of the inverter is presented in detail with the special consideration of the cryogenic temperature operation. Moreover, a packaging and integration architecture is designed and fabricated to demonstrate the feasibility and performance of the inverter in the lab. It is able to achieve no leakage with good thermal and air insulation. With the inverter and packaging, the experimental results show that the inverter operates properly at cryogenic temperatures. The loss is measured at different load conditions, and the loss analysis is given, which shows that the cryogenically cooled inverter has 30% less loss than operating at room temperature.

Paralleling three phase three-level inverters is gaining popularity in industrial applications. However, analytical models for the harmonics calculation of a three-level neutral point clamped (NPC) inverter with popular space vector modulation (SVM) are not found in the literature. Moreover, how interleaving angle impacts the dc- and ac-side harmonics and electromagnetic interference (EMI) harmonics in parallel interleaved three-level inverters and how to optimize interleaving angle to reduce these harmonics have not been discussed in the literature. Furthering previous study, this article presents the modeling, analysis, and reduction of harmonics in paralleled and interleaved three-level NPC inverters with SVM. Analytical models for harmonic calculation are developed, and the dc-side harmonics characteristics of an NPC inverter are identified. The impact of interleaving angle on the ac-side voltage and dc-link current harmonics of parallel interleaved three-level NPC inverters is comprehensively studied. The impact of switching frequency and interleaving angle on EMI harmonics is also illustrated. Optimal interleaving angle ranges to reduce these harmonics are derived analytically. The developed models and harmonic reduction analysis are verified experimentally with two paralleled and interleaved three-level NPC inverters.

In order to apply power electronics systems to applications such as superconducting systems under cryogenic temperatures, it is necessary to investigate the characteristics of different parts in the power electronics system. This article reviews the influence of cryogenic temperature on power semiconductor devices including Si and wide bandgap switches, integrated circuits, passive components, interconnection and dielectric materials, and some typical cryogenic converter systems. Also, the basic theories and principles are given to explain the trends for different aspects of cryogenically cooled converters. Based on the review, Si active power devices, bulk Complementary metal-oxide-semiconductor (CMOS) based integrated circuits, nanocrystalline and amorphous magnetic cores, NP0 ceramic and film capacitors, thin/metal film and wirewound resistors are the components suitable for cryogenic operation. Pb-rich PbSn solder or In solder, classic printed circuit boards material, most insulation papers and epoxy encapsulant are good interconnection and dielectric parts for cryogenic temperatures.

Three-level converters are more susceptible to parasitics compared with two-level converters because of their complicated structure with multiple switching loops. This paper presents the methodology of busbar layout design for three-level converters based on magnetic cancellation effect. The methodology can fit for 3L converters with symmetric and asymmetric configurations. A detailed design example is provided for a high power three-level active neutral point clamped (ANPC) converter, which includes the module selection, busbar layout, and DC-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. The results match with each other, and the inductances of short and long loops are 6.5 nH and 17.5 nH respectively, which are significantly lower than the busbars of NPC type converters in other references.

For system planning of three-phase inverter-based islanded ac microgrids, the low frequency instability issue caused by interactions of inverter droop controllers is a major concern. When internal control information of procured commercial inverters is unknown, impedance-based small-signal stability criteria facilitate prediction of resonances in medium and high frequency ranges, but they usually assume the grid fundamental frequency as constant and thus they are incapable of analyzing the low-frequency oscillation of the fundamental frequency in islanded microgrids. Aiming at solving this issue, this paper proposes two stability analysis methods based on terminal characteristics of inverters and passive connection network including the dynamics of the fundamental frequency for analysis of low-frequency stability in islanded multiple-bus microgrids. Based on the Component Connection Method (CCM) to systematically separate inverters from the passive connection network, a general approach is developed to model the microgrid as a multiple-input-multiple-output (MIMO) negative feedback system in the common system d-q reference frame. By applying the generalized Nyquist stability criterion (GNC) to the return-ratio and return-difference matrices of the MIMO system model, the low-frequency stability related to the fundamental frequency can be analyzed using the measured terminal characteristics of inverters. Analysis and simulation of a 37-bus microgrid verify the effectiveness of the proposed stability analysis methods.

Turn-on loss is the dominant part of the switching loss for SiC MOSFETs in hard switching. It is difficult to reduce turn-on loss with conventional voltage source gate drives (VSGs) because of the limited gate voltage rating and large internal gate resistance of SiC MOSFETs. A charge pump gate drive (CPG) that can reduce the turn-on loss is presented in this paper. By pre-charging the charge-storage capacitor in the gate drive with a charge pump circuit, the gate drive output voltage is pumped up to provide higher gate current during the turn-on transient. As a result, the turn-on time and loss is decreased. Moreover, due to the charge transfer from the charge-storage capacitor to the MOSFET gate capacitance, the pumped output voltage can naturally drop back to a normal value that avoids gate overcharging. The structure of the gate drive is simple, and no additional control is needed. The operation of the proposed CPG is verified with double pulse tests based on SiC MOSFETs. The switching loss of the proposed CPG is reduced by up to 71.7% compared to the conventional VSG at full load condition.

Using high voltage (HV) Silicon Carbide (SiC) power semiconductors in the modular multilevel converter (MMC) is promising because of a fewer submodules and lower switching loss compared to conventional Si based solutions. The nearest level pulse width modulation (NL-PWM) is commonly used in the MMC for medium voltage applications. However, with the NL-PWM and existing voltage balancing control, there are many submodules that switch their modes in a control cycle, resulting in a high dv/dt during the deadtime of the power semiconductor, which could be multiple times of the dv/dt of single device. This poses great challenges on the noise immunity and insulation design in the MMC using HV SiC devices, which have very fast switching speed. A novel voltage balancing control, which ensures only two submodules switch their modes in a control cycle, is proposed in this paper, limiting the maximum dv/dt to the dv/dt of single power semiconductor and meanwhile maintaining the voltage balance performance. The proposed voltage balancing control is experimentally validated in a 10 kV SiC MOSFET based MMC with four submodules per arm.

High performance gate drive power supply (GDPS) plays a crucial role in ensuring the reliability and safety of the gate driver for power semiconductor devices. This paper focuses on the design of a high-voltage- insulated GDPS for the 10-kV SiC MOSFET in medium-voltage (MV) application. Design considerations, including insulation scheme, high-voltage-insulated transformer design, and load voltage regulation scheme, are proposed. In addition, the performance of the secondary-side-regulated (SSR) GDPS and that of the primary-side-regulated (PSR) GDPS are compared for several aspects, including inter-winding capacitance, load-voltage-regulation-rate, conversion efficiency, and hardware complexity. Finally, an SSR GDPS and a PSR GDPS, with an insulation voltage of 20 kV, are built in the lab. The test results demonstrate that the PSR GDPS is more preferable because of lower interwinding capacitance, lower load-voltage-regulation-rate, higher conversion efficiency, and simpler control circuit.

This paper presents a new control method to enable large-scale solar photovoltaic (PV) plants to damp electromechanical oscillations. The proposed step-down modulation (SDM) control method is based on active power modulation, and it does not require curtailment as in other approaches. After an oscillation event is detected, the PV panel voltage is controlled to transiently deviate the power from its maximum power point (MPP), this power margin is used to modulate active power until the oscillation event is mitigated. Then, the SDM control restores the PV power to its MPP, and it is reset to operate for the next event. The control design, panel voltage strategy, and implementation is tested in a two-area system. A comparison of the SDM control with a curtailment-based PV damping control is also explored in a test case of the 179-bus WECC system with six large-scale PV plants, showing the improved damping capability of the proposed method.

PV inverters can provide reactive power while generating active power. An ongoing microgrid implementation at Duke Energy actively engages non-utility PVs to generate/absorb reactive power in support of ancillary services to increase microgrid resiliency during extreme events. PV systems are requested to provide reactive power support: 1) in response to grid voltage variation to better regulate the local voltage; or 2) in response to utility incentives, such as following Transactive Energy System (TES) incentives. However, providing ancillary services might shorten the lifetime expectation of PV inverter semiconductors. This paper summarizes the potential impacts on a PV inverter semiconductor's lifetime when providing ancillary services. The analysis presented in this research work shows that providing reactive power support will increase the mean junction temperature and the junction temperature variation of the inverter diodes. This increased junction temperature will eventually lead to shorter diode lifetime. The lifetime estimation of semiconductors is briefly reviewed. The power losses of PV inverter semiconductors are derived as a support analysis to the junction temperature calculation. In addition, the impact of the filtering inductor on the semiconductor current distribution is discussed. The theoretical analysis presented in this research work is supported by simulation results.

Novel power system control and new utility devices need to be tested before their actual deployment to the power grid. To assist with such a testing need, real-time digital emulators such as RTDS and Opal-RT can be used to connect to the physical world and form a hardware in the loop (HIL) emulation. However, due to the limitations of today's computational resources, the accuracy and fidelity suffer from different levels of model reductions in purely digital simulations. CURENT has developed a reconfigurable electric grid hardware testbed (HTB) to overcome the limitations of digital emulators. The HTB has been used to develop measurement, control, modeling, and actuation techniques for a national grid with a high penetration of renewables. The power electronic-based system includes emulators for synchronous generators; photovoltaics with grid-interfacing inverter; wind turbines; induction motor loads, ZIP loads, power electronic loads; batteries; ac and dc transmission lines; short circuit faults and grid relay protection; and a multiterminal HVDC overlay including power electronics interfaces. The system contains real elements of power flow, measurement, communication, protection, and control that mimic what would be seen in an actual electric grid. This paper presents an overview of the HTB and several scenarios that have been run to determine control and actions needed for the future power grid.

The integrated starter-generator system (ISGS) is a combination of starter and generator for independent power systems in transportation. It replaces both a conventional starter and generator with a single set of highly integrated devices. A power hardware in the loop simulation that is flexible and can include the hardware under test is used to test the ISGS under representative field conditions. This paper utilizes the special structure of the ISGS and proposes an ISGS emulator (ISGSE) to develop and test the converter. The proposed ISGSE can be used to test a variety of motor drives or rectifiers including dynamic capabilities without necessitating a connection to a large motor load. To emulate the ISGS, the structure and operation principle in different modes are introduced in detail. Also, the issue of stability and accuracy is discussed in this paper. Detailed simulation and experimental comparisons are carried out between the ISGS and the ISGSE, which validates the proposed ISGSE as an effective tool for designing and testing new motor drives.

To understand the limitation of maximizing the switching speed of SiC low current discrete devices and high current power modules in hard switching applications, double pulse tests are conducted and the testing results are analyzed. For power modules, the switching speed is generally limited by the parasitics rather than the gate drive capability. For discrete SiC devices, the conventional voltage source gate drive (VSG) is not sufficient to maximize the switching speed even if the external gate resistance is minimized. The limitation of existing current source gate drives (CSG) are analyzed, and a CSG dedicated for SiC discrete devices is proposed, which can provide constant current during the switching transient regardless of the high Miller voltage and large internal gate resistance. Compared with the conventional VSG, the proposed CSG achieves 67% faster turnon time and 50% turn-off time, and 68% reduction in switching loss at full load condition.

Junction temperature is an important design/operation parameter, as well as, a significant indicator of device's health condition for power electronics converters. Compared to its silicon (Si) counterparts, it is more critical for silicon carbide (SiC) devices due to the reliability concern introduced by the immaturity of new material and packaging. This paper proposes a practical implementation using an intelligent gate drive for online junction temperature monitoring of SiC devices based on turn-off delay time as the thermo-sensitive electrical parameter. First, the sensitivity of turn-off delay time on the junction temperature for fast switching SiC devices is analyzed. A gate impedance regulation assist circuit is proposed to enhance the sensitivity by a factor of 60 and approach 736 ps/°C tested in the case study with little penalty on the power conversion performance. Next, an online monitoring unit based on gate assist circuits is developed to monitor the turn-off delay time in real time with the resolution less than 104 ps. As a result, the micro-controller is capable of “reading” junction temperature during the converter operation. Finally, a SiC-based half-bridge inverter is constructed with an intelligent gate drive consisting of the gate impedance regulation circuit and online turn-off delay time monitoring unit. Experimental results demonstrate the feasibility and accuracy of the proposed approach.

As wide-bandgap (WBG) devices and applications move from niche to mainstream, a new generation of engineers trained in this area is critical to continue the development of the field. This paper introduces a new hands-on course in characterization of WBG devices, which is an emerging and fundamental topic in WBG-based techniques. First, the lecture-simulation-experiment format based course structure and design considerations, such as safety, are presented. Then, the necessary facilities to support this hands-on course are summarized, including classroom preparation, software tools, and laboratory equipment. Afterward, the detailed course implementation flow is presented to illustrate the approach of close interaction among lecture, simulation, and experiment to maximize students' learning outcomes. Finally, grading for students and course evaluation by students are discussed, highlighting the findings and potential improvements. Detailed course materials are provided via potenntial.eecs.utk.edu/WBGLab for educational use.

For some distribution networks equipped with smart switches such as Chattanooga Electric Power Board (EPB) system, they can island some areas of the network to mitigate the impact through defensive islanding. However, due to intermittency and uncertainty of renewable-based distributed energy resources (DERs), it is highly likely that the islanded areas would experience insufficient or surplus power. This problem can be relieved by changing the boundaries of islanded areas to incorporate neighbouring load sections (LSs) or disconnect some connected LSs. Considering penetration level and sharply changing rate of renewable energy, it is challenging to define suitable boundaries for islanded areas in real time. Therefore, a two-stage energy management system (EMS) is proposed in this study, which includes day-ahead scheduling stage as well as short-term and real-time control stages. In the first stage, the initial switch combinations of LSs and DERs’ scheduling are obtained through a mixed integer quadratic programming, whereas the second stage is based on rule-based power management algorithm. Finally, a model reduced from real EPB system is used for validating the proposed two-stage EMS. The results successfully verify the effectiveness and performance of the proposed EMS for addressing the energy management of islanded areas under defensive islanding.

This paper presents the characterization of the temperature-dependent short-circuit performance of a Gen3 10 kV/20 A silicon carbide (SiC) mosfet. The test platform consisting of a phase-leg configuration and a fast speed 10-kV solid state circuit breaker, with temperature control, is introduced in detail. A novel FPGA-based short-circuit protection circuit having a response time of 1.5 μs is proposed and integrated into the gate driver. The short-circuit protection is validated through the platform. The short-circuit characteristics for both the hard switching fault and fault under load (FUL) types at various dc-link voltages (from 500 V to 6 kV) are tested and discussed. The saturation current increases with dc-link voltage and achieves 360 A at 6 kV. Different from low voltage SiC devices, there is no current spike in FUL type of fault. The temperature-dependent short-circuit performance is also presented from 25 to 125 °C. The difference of short-circuit waveforms at various initial junction temperatures can be neglected. A thermal model of the 10-kV SiC mosfet is built for the junction temperature estimation during the short circuit and for analysis of the initial junction temperature impact on the short-circuit performance.

Battery energy storage systems (BESSs) tend to be too costly, restrictive, and require high maintenance for experimental use, but power system tests often need their representation. As a solution, we propose an all-in-one, reconfigurable BESS emulation tool for grid applications that only requires one three-phase voltage-source converter. This emulator provides chemistry-specific battery behavior like previous work, but it also includes the BESS's power electronics interface and control as well as automatic frequency and voltage support functions for the attached power system. Thus, it allows simple, plug-and-play BESS emulation for grid applications. This paper details the construction, verification, and use of the BESS emulator in an existing grid testbed and concludes that it provides an inexpensive, easy-to-use alternative to using real BESSs in power system experiments.

The design, implementation, and testing of a control system for a flexible microgrid (MG) is presented in this study. The MG controllers can be implemented in a real-world MG with multiple smart switches, photovoltaic panel system, and battery energy storage systems (BESSs). With the benefits from smart switches, the MG has unique characteristics such as dynamic boundary and flexible point of interconnection (POI) concepts. To control such a unique MG and realise the dynamic boundary, an MG central controller and two types of local controllers are implemented. Compared to the MG with fixed boundary, the MG with dynamic boundary can have smaller BESS capacity, better utilisation of renewable energy, and multiple POI options. Also, compared with IEEE Std 2030.7–2017, the topology identification and active and reactive power balance functions are newly designed to realise the dynamic boundary concept. The planned islanding and reconnection functions are modified to realise the flexible POI concept. These functions are introduced including the software architecture, cooperation, and interaction among them. Finally, a hardware-in-the-loop testing platform based on the Opal-RT real-time simulator is set up to verify the performance, realisation of the dynamic boundary, and flexible POI concepts with four comprehensive test scenarios.

Semiconductor devices based solid-state circuit breakers (SSCBs) are promising in the dc power distribution system as protective equipment for their ultrashort action time. This letter proposes a topology of SSCB using series connected silicon carbide (SiC) metal oxide semiconductor field effect transistors (mosfets), which only requires a single isolated gate driver. The SSCB has very low cost and high reliability because it only has 13 components including passive components and diodes apart from two SiC mosfets to achieve both balanced voltage distribution during short-circuit interruption duration and reliable positive gate voltage during on-state. The SSCB prototype is built and experimentally verified to interrupt 75 A short-circuit current under the dc-bus voltage of 1200 V within 1.5 μs.

Electric distribution systems around the world are seeing an increasing number of utility-owned and non-utility-owned (customer-owned) intelligent devices and systems being deployed. New deployments of utility-owned assets include self-healing systems, microgrids, and distribution automation. Non-utility-owned assets include solar photovoltaic generation, behind-the-meter energy storage systems, and electric vehicles. While these deployments provide potential data and control points, the existing centralized control architectures do not have the flexibility or the scalability to integrate the increasing number or variety of devices. The communication bandwidth, latency, and the scalability of a centralized control architecture limit the ability of these new devices and systems from being engaged as active resources. This paper presents a standards-based architecture for the distributed power system controls, which increases operational flexibility by coordinating centralized and distributed control systems. The system actively engages utility and non-utility assets using a distributed architecture to increase reliability during normal operations and resiliency during extreme events. Results from laboratory testing and preliminary field implementations, as well as the details of an ongoing full-scale implementation at Duke Energy, are presented.

A Hardware Testbed(HTB) is developed for accurate and flexible emulation and testing of electrical power system and their control, measurement, and protection systems. In the HTB, modular and programmable power electronics converters are used to mimic the static and dynamic characteristics of electrical power components. This paper overviews the development, integration, and application of the HTB, covering emulation principle, hardware and software configuration, and example results of power system research using the HTB. The advantages of the HTB, compared with real-time digital simulation and downscaled hardware-based testing platform are discussed.

A transmission line emulator has been developed to flexibly represent interconnected ac lines under normal operating conditions in a voltage-source-converter-based power system emulation platform. As the most serious short-circuit fault condition, the three-phase short-circuit fault emulation is essential for power system studies. This paper proposes a model to realize a three-phase short-circuit fault emulation at different locations along a single transmission line or one of several parallel-connected transmission lines. At the same time, a combination method is proposed to eliminate the undesired transients caused by the current reference step changes while switching between the fault state and the normal state. Experiment results verify the developed transmission line three-phase short-circuit fault emulation capability.

The hybrid electric bus (HEB) presents an emerging solution to exhaust gas emissions in urban transport. This paper proposes a multiport bidirectional switched reluctance motor (SRM) drive for solar-assisted HEB (SHEB) powertrain, which not only improves the motoring performance, but also achieves flexible charging functions. To extend the driving miles and achieve self-charging ability, photovoltaic (PV) panels are installed on the bus to decrease the reliance on fuelsbatteries and charging stations. A bidirectional front-end circuit with a PV-fed circuit is designed to integrate electrical components into one converter. Six driving and five charging modes are achieved. The dc voltage is boosted by the battery in generator control unit (GCU) driving mode and by the charge capacitor in battery driving mode, where the torque capability is improved. Usually, an extra converter is needed to achieve battery charging. In this paper, the battery can be directly charged by the demagnetization current in GCU or PV driving mode, and can be quickly charged by the PV panels and GCUAC grids at SHEB standstill conditions, by utilizing the traction motor windings and integrated converter circuit, without external charging converters. Experiments on a three-phase 128 SRM confirm the effectiveness of the proposed drive and control scheme.

The series connection of insulated gate bipolar transistors (IGBTs) allows operation at voltage levels higher than the rated voltage of one IGBT and has less power semiconductor costs compared to multilevel topologies. However, voltage unbalance during the switching transient is a challenge for series-connected device application. This paper presents an field-programmable gate array (FPGA)-based voltage balancing strategy for multiseries-connected high-voltage (HV)-IGBTs including an FPGA-based active voltage balancing control (AVBC) circuit integrated into the gate driver and the control for multiseries-connected IGBTs. The effectiveness of the control has been experimentally validated in a prototype using four 4.5 kV HV-IGBTs in series connection.

The temperature-dependent characteristics of the third-generation 10-kV/20-A SiC MOSFET including the static characteristics and switching performance are carried out in this paper. The steady-state characteristics, including saturation current, output characteristics, antiparallel diode, and parasitic capacitance, are tested. A double pulse test platform is constructed including a circuit breaker and gate drive with >10-kV insulation and also a hotplate under the device under test for temperature-dependent characterization during switching transients. The switching performance is tested under various load currents and gate resistances at a 7-kV dc-link voltage from 25 to 125 C and compared with previous 10-kV MOSFETs. A simple behavioral model with its parameter extraction method is proposed to predict the temperature-dependent characteristics of the 10-kV SiC MOSFET. The switching speed limitations, including the reverse recovery of SiC MOSFET's body diode, overvoltage caused by stray inductance, crosstalk, heat sink, and electromagnetic interference to the control are discussed based on simulations and experimental results.

Owing to the recent power outages caused by extreme events, installing battery energy storage and backup generators is important to improve resiliency for a grid-tied microgrid. In the design stage, the event occurrence time and duration, which are highly uncertain and cannot be effectively predicted, may affect the needed battery and backup generator capacity but are usually assumed to be pre-determined in utility planning tools. This study investigates the optimal battery and backup generator sizing problem considering the stochastic event occurrence time and duration for the grid-tied microgrid under islanded operation. The reliability requirement is quantified by the mean value of the critical customer interruption time in each stochastic islanding time window (ITW), whose length is the duration and the centre is the occurrence time. The stochastic ITW constraint is then transformed to a probability-weighted expression to derive an equivalent Mixed Integer Linear Programming model. Numerical simulations on a realistic grid-tied PV-based microgrid demonstrate that the total cost is reduced by 11.5% considering the stochastic ITW, compared with the deterministic ITW under the same reliability requirement.

This paper proposes a simple and cost-effective current measurement technique for four-phase switched reluctance motor (SRM) control, by splitting the dual bus line of the converter, without pulse injection and voltage penalty. Only two Hall-effect sensors are utilized, where one is installed in the upper bus to measure two phase currents, and the other is placed in the lower bus to measure other two phase currents. In order to realize independent current measurement in the whole turn-on region, switching functions are redesigned so that upper switches of two phases act as the choppers, while lower switches of the other two phases are employed as the choppers. Compared to traditional drives, the developed system requires only two Hall-effect sensors in the dual bus line, without a need for individual phase sensors or additional devices, which reduces the cost and volume for SRM drives. Furthermore, compared to the single-sensor based current measurement scheme, the proposed method has no need to implement pulse injection and will not cause any voltage penalty and current distortion, which also improve the current measurement accuracy and system performance. Simulation and experiments carried out on a 150-W four-phase 8/6 SRM confirm the effectiveness of the proposed technique.

Newly emerged gallium nitride (GaN) devices feature ultrafast switching speed and low on-state resistance that potentially provide significant improvements for power converters. This paper investigates the benefits of GaN devices in an LLC resonant converter and quantitatively evaluates GaN devices' capabilities to improve converter efficiency. First, the relationship of device and converter design parameters to the device loss is established based on an analytical model of LLC resonant converter operating at the resonance. Due to the low effective output capacitance of GaN devices, the GaN-based design demonstrates about 50% device loss reduction compared with the Si-based design. Second, a new perspective on the extra transformer winding loss due to the asymmetrical primary-side and secondary-side current is proposed. The device and design parameters are tied to the winding loss based on the winding loss model in the finite element analysis (FEA) simulation. Compared with the Si-based design, the winding loss is reduced by 18% in the GaN-based design. Finally, in order to verify the GaN device benefits experimentally, 400- to 12-V, 300-W, 1-MHz GaN-based and Si-based LLC resonant converter prototypes are built and tested. One percent efficiency improvement, which is 24.8% loss reduction, is achieved in the GaN-based converter.

This paper presents an intelligent gate drive for silicon carbide (SiC) devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control gate voltages and gate loop impedances of both devices in a phase-leg configuration during different switching transients. Compared to conventional gate drives, the proposed circuit has the capability of accelerating the switching speed of the phase-leg power devices and suppressing the crosstalk to below device limits. Based on Wolfspeed 1200-V SiC MOSFETs, the test results demonstrate the effectiveness of this intelligent gate drive under varying operating conditions. More importantly, the proposed intelligent gate assist circuitry is embedded into a gate drive integrated circuit, offering a simple, compact, and reliable solution for end-users to maximize benefits of SiC devices in actual power electronics applications.

With the increased cloud computing and digital information storage, the energy requirement of data centers keeps increasing. A high-voltage point of load (HV POL) with an input series output parallel structure is proposed to convert 400 to 1 VDC within a single stage to increase the power conversion efficiency. The symmetrical controlled half-bridge current doubler is selected as the converter topology in the HV POL. A load-dependent soft-switching method has been proposed with an auxiliary circuit that includes inductor, diode, and MOSFETs so that the hard-switching issue of typical symmetrical controlled half-bridge converters is resolved. The operation principles of the proposed soft-switching half-bridge current doubler have been analyzed in detail. Then, the necessity of adjusting the timing with the loading in the proposed method is analyzed based on losses, and a controller is designed to realize the load-dependent operation. A lossless RCD current sensing method is used to sense the output inductor current value in the proposed load-dependent operation. Experimental efficiency of a hardware prototype is provided to show that the proposed method can increase the converter's efficiency in both heavy- and light-load conditions.

Dead time significantly affects the reliability, power quality, and efficiency of voltage-source converters. For silicon carbide (SiC) devices, considering the high sensitivity of turn-off time to the operating conditions (> 5× difference between light load and full load) and characteristics of inductive loads (> 2× difference between motor load and inductor), as well as large additional energy loss induced by the freewheeling diode conduction during the superfluous dead time (~15% of the switching loss), then the traditional fixed dead time setting becomes inappropriate. This paper introduces an approach to adaptively regulate the dead time considering the current operating condition and load characteristics via synthesizing online monitored turn-off switching parameters in the microcontroller with an embedded preset optimization model. Based on a buck converter built with 1200-V SiC MOSFETs, the experimental results show that the proposed method is able to ensure reliability and reduce power loss by 12% at full load and 18.2% at light load (8% of the full load in this case study).

This paper develops a synchronous generator emulator by using a three-phase voltage source converter for transmission level power system testing. Different interface algorithms are compared, and the voltage type ideal transformer model is selected considering accuracy and stability. At the same time, closed-loop voltage control with current feed-forward is proposed to decrease the emulation error. The emulation is then verified through two different ways. First, the output waveforms of the emulator in experiments are compared with the simulation under the same condition. Second, a transfer function perturbation-based error model is obtained and redefined as the relative error for the amplitude and phase between the emulated and the target system over the frequency range of interest. The major cause of the error is investigated through a quantitative analysis of the error with varying parameters.

This paper presents a steady-state model of MMC for the second-order phase voltage ripple prediction under unbalanced conditions, taking the impact of negative-sequence current control into account. From the steady-state model, a circular relationship is found among current and voltage quantities, which can be used to evaluate the magnitudes and initial phase angles of different circulating current components. Moreover, in order to calculate the circulating current in a point-to-point MMC-based HVdc system under unbalanced grid conditions, the derivation of equivalent dc impedance of an MMC is discussed as well. According to the dc impedance model, an MMC inverter can be represented as a series connected R-L-C branch, with its equivalent resistance and capacitance directly related to the circulating current control parameters. Experimental results from a scaled-down three-phase MMC system under an emulated single-line-to-ground fault are provided to support the theoretical analysis and derived model. This new models provides an insight into the impact of different control schemes on the fault characteristics and improves the understanding of the operation of MMC under unbalanced conditions.

The double pulse test (DPT) is a widely accepted method to evaluate the dynamic behavior of power devices. Considering the high switching-speed capability of wide band-gap devices, the test results are very sensitive to the alignment of voltage and current (V-I) measurements. Also, because of the shoot-through current induced by Cdv/dt (i.e., cross-talk), the switching losses of the nonoperating switch device in a phase-leg must be considered in addition to the operating device. This paper summarizes the key issues of the DPT, including components and layout design, measurement considerations, grounding effects, and data processing. Additionally, a practical method is proposed for phase-leg switching loss evaluation by calculating the difference between the input energy supplied by a dc capacitor and the output energy stored in a load inductor. Based on a phase-leg power module built with 1200-V/50-A SiC MOSFETs, the test results show that this method can accurately evaluate the switching loss of both the upper and lower switches by detecting only one switching current and voltage, and it is immune to V-I timing misalignment errors.

Small-signal stability is an important concern in three-phase inverter-based ac power systems. The impedance-based approach based on the generalized Nyquist stability criterion (GNC) can analyze the stability related with the medium and high-frequency modes of the systems. However,. the GNC involves the right-half-plane (RHP) pole calculation of return-ratio transfer function matrices, which cannot be avoided for stability analysis of complicated ac power systems. Therefore, it necessitates the detailed internal control information of the inverters, which is not normally available for commercial inverters. To address this issue, this paper introduces the component connection method (CCM) in the frequency domain for stability analysis in the synchronous d-q frame, by proposing a method of deriving the impedance matrix of the connection networks of inverter-based ac power systems. Demonstration on a two-area system and a microgrid shows that: The CCM-enabled approach can avoid the RHP pole calculation of return-ratio matrices and enables the stability analysis by using only the impedances of system components, which could be measured without the need for the internal information. A stability analysis method based on d-q impedances, the CCM, and the determinant-based GNC is also proposed to further simplify the analysis process. Inverter controller parameters can be designed as stability regions in parameter spaces, by repetitively applying the proposed stability analysis method. Simulation and experimental results verify the validity of the proposed stability analysis method and the parameter design approach.

Hybrid ac/dc transmission extends the power transfer capacity of existing long ac lines closer to their thermal limit, by superposing the dc current onto three-phase ac lines through a zigzag transformer. However, this transformer could suffer saturation under unbalanced line impedance conditions. This paper introduces the concept of hybrid line impedance conditioner (HLIC) as a cost-effective approach to compensate for the line unbalance and therefore avoid saturation. The topology and operation principle are presented. The two-level control strategy is described, which enables autonomous adaptive regulation without the need of system-level control. Design and implementation are also analyzed, including dc-link capacitance as one of the key line conditioner components, HLIC installation, and protection under fault conditions. The cost study on this HLIC-based hybrid system is also performed to reveal the benefits of the solution. Simulation results and experimental results based on a down-scaled prototype are provided to verify the feasibility of the proposed approach.

As one of the most popular cloud services, data storage has attracted great attention in recent research efforts. Key-value (k-v) stores have emerged as a popular option for storing and querying billions of key-value pairs. So far, existing methods have been deterministic. Providing such accuracy, however, comes at the cost of memory and CPU time. In contrast, we present an approximate k-v storage for cloud-based systems that is more compact than existing methods. The tradeoff is that it may, theoretically, return errors. Its design is based on the probabilistic data structure called “bloom filter”, where we extend the classical bloom filter to support key-value operations. We call the resulting design as the kBF (key-value bloom filter). We further develop a distributed version of the kBF (d-kBF) for the unique requirements of cloud computing platforms, where multiple servers cooperate to handle a large volume of queries in a load-balancing manner. Finally, we apply the kBF to a practical problem of implementing a state machine to demonstrate how the kBF can be used as a building block for more complicated software infrastructures.

One way to incorporate the increasing amount of wind penetration is to control wind turbines to emulate the behavior of conventional synchronous generators. However, the energy balance is the main issue for the wind turbines to be truly dispatchable by the power system operator such as the generators. This paper presents a comprehensive virtual generator control method for the full converter wind turbine, with a minute-level energy storage in the dc link as the energy buffer. The voltage closed-loop virtual synchronous generator control of the wind turbine allows it to work under both grid-connected and stand-alone condition. Power balance of the wind turbine system is achieved by controlling the rotor speed of the turbine according to the loading condition. With the proposed control, the wind turbine system can enhance the dynamic response, and can be dispatched and regulated by the system operator. The sizing design of the short term energy storage is also discussed in this paper. Experimental results are presented to demonstrate the feasibility and effectiveness of the proposed control method.

This paper presents the development of a scaled four-terminal high-voltage direct current (HVDC) testbed, including hardware structure, communication architecture, and different control schemes. The developed testbed is capable of emulating typical operation scenarios including system start-up, power variation, line contingency, and converter station failure. Some unique scenarios are also developed and demonstrated, such as online control mode transition and station re-commission. In particular, a dc line current control is proposed, through the regulation of a converter station at one terminal. By controlling a dc line current to zero, the transmission line can be opened by using relatively low-cost HVDC disconnects with low current interrupting capability, instead of the more expensive dc circuit breaker. Utilizing the dc line current control, an automatic line current limiting scheme is developed. When a dc line is overloaded, the line current control will be automatically activated to regulate current within the allowable maximum value.

This paper presents a comprehensive short-circuit ruggedness evaluation and numerical investigation of up-to-date commercial silicon carbide (SiC) MOSFETs. The short-circuit capability of three types of commercial 1200-V SiC MOSFETs is tested under various conditions, with case temperatures from 25 to 200 °C and dc bus voltages from 400 to 750 V. It is found that the commercial SiC MOSFETs can withstand short-circuit current for only several microseconds with a dc bus voltage of 750 V and case temperature of 200 °C. The experimental short-circuit behaviors are compared, and analyzed through numerical thermal dynamic simulation. Specifically, an electrothermal model is built to estimate the device internal temperature distribution, considering the temperature-dependent thermal properties of SiC material. Based on the temperature information, a leakage current model is derived to calculate the main leakage current components (i.e., thermal, diffusion, and avalanche generation currents). Numerical results show that the short-circuit failure mechanisms of SiC MOSFETs can be thermal generation current induced thermal runaway or high-temperature-related gate oxide damage.

High power density is a desirable feature of power electronics design, which prompts economic incentives for industrial applications. In this paper, a gallium nitride (GaN)-based 2-kVA single-phase inverter design was developed for the Google Little Box Challenge, which achieves a 102-W/in3 power density. First, the static and dynamic temperature-dependent characteristics of multiple SiC and enhancement-mode GaN FETs are investigated and compared. Based on the device testing results, several topologies of the inverter stage and different power decoupling solutions are compared with respect to the device volume, efficiency, and thermal requirements. Moreover, some design approaches for magnetic devices and the implementation of gate drives for GaN devices are discussed in this paper, which enable a compact and robust system. Finally, a dc notch filter and a hard switching full-bridge converter are combined as the proposed design for the prototype. A 2-kVA prototype is demonstrated, which meets the volume, efficiency, and thermal requirements. The performance of the prototype is verified by the experimental results.

A hardware testbed platform emulating multiple-area power system scenario dynamics has been established aiming at multiple time-scale real-time emulations. In order to mimic real power flow situations in the utility system, the load emulators have to behave like real ones in both their static and dynamic characteristics. A constant-impedance, constant-current, and constant-power (ZIP) model has been used for static load types, while a three-phase induction motor model has been built to represent dynamic load types. In this paper, ways of modeling ZIP and induction motor loads and the performance of each load emulator are discussed. Comparisons between simulation and experimental results are shown as well for the validation of the emulator behaviors. A real-time composite power load emulator is then demonstrated with desired characteristics and detailed transients for representing a power system PQ bus dynamics.

This paper presents the design and implementation of a single-phase on-board bidirectional plug-in electric vehicle (PEV) charger that can provide reactive power support to the utility grid in addition to charging the vehicle battery. The topology consists of two-stages: a full-bridge ac-dc boost converter; and a half-bridge bidirectional dc-dc converter. The charger operates in two quadrants in the active-reactive power (PQ) power plane with five different operation modes (i.e., charging-only, charging-capacitive, charging-inductive, capacitive-only, and inductive-only). This paper also presents a unified controller to follow utility PQ commands in a smart grid environment. The cascaded two-stage system controller receives active and reactive power commands from the grid, and results in line current and battery charging current references while also providing a stable dynamic response. The vehicle's battery is not affected during reactive power operation in any of the operation modes. Testing the unified system controller with a 1.44 kVA experimental charger design demonstrates the successful implementation of reactive power support functionality of PEVs for future smart grid applications.

Double pulse test (DPT) is a widely accepted method to evaluate the switching characteristics of semiconductor switches, including SiC devices. However, the observed switching performance of SiC devices in a PWM inverter for induction motor drives is almost always worse than the DPT characterization, with slower switching speed, more switching losses, and more serious parasitic ringing. This paper systematically investigates the factors that limit the SiC switching performance from both the motor side and inverter side, including the load characteristics of induction motor and power cable, two more phase legs for the three-phase PWM inverter in comparison with the DPT, and the parasitic capacitive coupling effect between power devices and heat sink. Based on a three-phase PWM inverter with 1200 V SiC MOSFETs, test results show that the induction motor, especially with a relatively long power cable, will significantly impact the switching performance, leading to a switching time increase by a factor of 2, switching loss increase up to 30% in comparison with that yielded from DPT, and serious parasitic ringing with 1.5 μs duration, which is more than 50 times of the corresponding switching time. In addition, the interactions among the three phase legs cannot be ignored unless the decoupling capacitors are mounted close to each phase leg to support the dc bus voltage during switching transients. Also, the coupling capacitance due to the heat sink equivalently increases the junction capacitance of power devices; however, its influence on the switching behavior in the motor drives is small considering the relatively large capacitance of the motor load.

This paper presents a board-level integrated silicon carbide (SiC) mosfet power module for high temperature and high power density application. Specifically, a silicon-on-insulator (SOI)-based gate driver capable of operating at 200 °C ambient temperature is designed and fabricated. The sourcing and sinking current capability of the gate driver are tested under various ambient temperatures. Also, a 1200 V/100 A SiC mosfet phase-leg power module is developed utilizing high temperature packaging technologies. The static characteristics, switching performance, and short-circuit behavior of the fabricated power module are fully evaluated at different temperatures. Moreover, a buck converter prototype composed of the SOI gate driver and SiC power module is built for high temperature continuous operation. The converter is operated at different switching frequencies up to 100 kHz, with its junction temperature monitored by a thermosensitive electrical parameter and compared with thermal simulation results. The experimental results from the continuous operation demonstrate the high temperature capability of the power module at a junction temperature greater than 225 °C.

This paper presents the analysis and control of a multilevel modular converter (MMC)-based HVDC transmission system under three possible single-line-to-ground fault conditions, with special focus on the investigation of their different fault characteristics. Considering positive-, negative-, and zero-sequence components in both arm voltages and currents, the generalized instantaneous power of a phase unit is derived theoretically according to the equivalent circuit model of the MMC under unbalanced conditions. Based on this model, a novel double-line frequency dc-voltage ripple suppression control is proposed. This controller, together with the negative- and zero-sequence current control, could enhance the overall fault-tolerant capability of the HVDC system without additional cost. To further improve the fault-tolerant capability, the operation performance of the HVDC system with and without single-phase switching is discussed and compared in detail. Simulation results from a three-phase MMC-HVDC system generated with MATLAB/Simulink are provided to support the theoretical analysis and proposed control schemes.

This paper presents a modular cascaded H-bridge multilevel photovoltaic (PV) inverter for single- or three-phase grid-connected applications. The modular cascaded multilevel topology helps to improve the efficiency and flexibility of PV systems. To realize better utilization of PV modules and maximize the solar energy extraction, a distributed maximum power point tracking control scheme is applied to both single- and three-phase multilevel inverters, which allows independent control of each dc-link voltage. For three-phase grid-connected applications, PV mismatches may introduce unbalanced supplied power, leading to unbalanced grid current. To solve this issue, a control scheme with modulation compensation is also proposed. An experimental three-phase seven-level cascaded H-bridge inverter has been built utilizing nine H-bridge modules (three modules per phase). Each H-bridge module is connected to a 185-W solar panel. Simulation and experimental results are presented to verify the feasibility of the proposed approach.

Featuring modularity and high efficiency, a modular multilevel converter (MMC) has become a promising topology in high-voltage direct-current transmission systems. However, its distributed capacitors lead to a more complicated startup process than that of a two-level converter. To fully understand this issue, the charging loops of an MMC rectifier and an MMC inverter during an uncontrolled precharge period are analyzed in this paper, with special focus on the necessity of additional capacitor charging schemes. Moreover, a small-signal model of a capacitor charging loop is first derived according to the internal dynamics of the MMC inverter. Based on this model, a novel startup strategy incorporating an averaging capacitor voltage loop and a feedforward control is proposed, which is capable of an enhanced dynamic response and system stability without sacrificing voltage control precision. The design considerations of the control strategy are also given in detail. Simulation results from a back-to-back MMC system supplying passive loads and experimental results from a scaled-down MMC prototype are provided to support the theoretical analysis and the proposed control scheme.

Rainflow algorithms are one of the popular counting methods used in fatigue and failure analysis in conjunction with semiconductor lifetime estimation models. However, the rainflow algorithm used in power semiconductor reliability does not consider the time-dependent mean temperature calculation. The equivalent temperature calculation proposed by Nagode et al. is applied to semiconductor lifetime estimation in this paper. A month-long arc furnace load profile is used as a test profile to estimate temperatures in insulated-gate bipolar transistors (IGBTs) in a STATCOM for reactive compensation of load. The degradation in the life of the IGBT power device is predicted based on time-dependent temperature calculation.

Reliability of power converters and lifetime prediction has been a major topic of research in the last few decades, especially for traction applications. The main failures in high power semiconductors are caused by thermomechanical fatigue. Power cycling and temperature cycling are the two most common thermal acceleration tests used in assessing reliability. The objective of this paper is to study the various power cycling tests found in the literature and to develop generalized steps in planning application specific power cycling tests. A comparison of different tests based on the failures, duration, test circuits, and monitored electrical parameters is presented.

This paper presents the paralleling operation of three-phase current-source rectifiers (CSRs) as the front-end power conversion stage of data center power supply systems based on 400-Vdc power delivery architecture, which has been proven to have higher efficiency than traditional ac architectures. A control algorithm of paralleled three-phase CSRs is introduced to achieve balanced outputs and individual rectifier module hot swap, which are required by power supply systems. By using silicon carbide (SiC) power semiconductors, SiC MOSFETs, and Schottky diodes, the power losses of the front-end stage are reduced, and the power supply system efficiency can be further increased. The prototype of a 19-kW front-end rectifier to convert 480 Vac,rms to 400 Vdc, based on three paralleled three-phase CSRs, is developed. Each CSR is an all-SiC converter and designed for high efficiency, and the front-end stage full-load efficiency is greater than 98% from experimental tests. The balanced outputs and individual converter hot swap are realized in the hardware prototype too.

With the emerging area of smart grids, one critical challenge faced by administrators of wide-area measurement systems is to analyze and model streaming data with limited resources on their embedded controllers. Usually, streaming data can be modeled as a multiset where each data item has its own frequency. In this paper, we study the problem on how to generate histograms of data items based on their frequency, so we can identify various issues such as power line tripping or line faults under constraints. The primary challenge for achieving this goal using conventional methods is that keeping an individual counter for each unique type of data is too memory-consuming, slow, and costly. In this paper, we describe a novel data structure and its associated algorithms, called the loglog bloom filter, for this purpose. This data structure extends the classical bloom filter with a recent technique called probabilistic counting, so it can effectively generate histograms for streaming data in one pass with sub-linear overhead. Therefore, this method is suitable for data processing in smart grids, where limited computational resources are available on the controllers. We analyze the performance, trade-offs, and capacity of this data structure, and evaluate it with real data traces collected through the frequency disturbance recorders deployed for the FNET/GridEye infrastructure. We demonstrate that this method can identify the frequencies of all unique items with high accuracy and low memory overhead, so that data outliers can be conveniently identified.

In this paper, the analysis of space vector modulation of a three-phase/wire/level Vienna rectifier is conducted, according to which the implementation of the equivalent carrier-based pulsewidth modulation is deduced theoretically within each separated sector in the diagram of vectors. The voltage balancing ability of dc-link neutral point, which depends on the uneven distribution of short vectors, is analyzed as well. An adaptive and robust controller to balance the output voltage under the unbalanced load limit for different modulation indices is proposed. The proposed controller can work at wide range of unbalanced load condition as well. Furthermore, the maximum unbalanced load is deduced versus the modulation index m when the converter works in unity power factor. An experimental prototype of 2.5 kW was built to verify the effectiveness of the theoretical analysis. Finally, the tested unbalanced limit of outputs for the experimental platform was given under different modulation indices. The output voltages for dual bus are balanced, and the theoretical analysis is verified.

A three-phase nonlinear load emulator using a power electronic converter is presented in this study. The proposed nonlinear load emulator is intended to be used in an ultrawide-area grid transmission network emulator, also called hardware testbed (HTB). The emulator converter is controlled in rectifier mode to act as the real nonlinear three-phase diode rectifier load. This paper presents an accurate controller for the nonlinear load emulator based on a three-phase diode rectifier system to be used in the HTB. This study also demonstrates simulation and experimental results for verification of the proposed controller.

In a phase-leg configuration, the high-switching-speed performance of silicon carbide (SiC) devices is limited by the interaction between the upper and lower devices during the switching transient (crosstalk), leading to additional switching losses and overstress of the power devices. To utilize the full potential of fast SiC devices, this paper proposes two gate assist circuits to actively suppress crosstalk on the basis of the intrinsic properties of SiC power devices. One gate assist circuit employs an auxiliary transistor in series with a capacitor to mitigate crosstalk by gate loop impedance reduction. The other gate assist circuit consists of two auxiliary transistors with a diode to actively control the gate voltage for crosstalk elimination. Based on CREE CMF20120D SiC MOSFETs, the experimental results show that both active gate drivers are effective to suppress crosstalk, enabling turn-on switching losses reduction by up to 17%, and negative spurious gate voltage minimization without the penalty of decreasing the switching speed. Furthermore, both gate assist circuits, even without a negative isolated power supply, are more effective in improving the switching behavior of SiC devices in comparison to the conventional gate driver with a -2 V turn-off gate voltage. Accordingly, the proposed active gate assist circuits are simple, efficient, and cost-effective solutions for crosstalk suppression.

This paper presents an active gate driver (AGD) for IGBT modules to improve their overall performance under normal condition as well as fault condition. Specifically, during normal switching transients, a di/dt feedback controlled current source and current sink is introduced together with a push-pull buffer for dynamic gate current control. Compared to a conventional gate drive strategy, the proposed one has the capability of reducing the switching loss, delay time, and Miller plateau duration during turn-on and turn-off transient without sacrificing current and voltage stress. Under overcurrent condition, it provides a fast protection function for IGBT modules based on the evaluation of fault current level through the di/dt feedback signal. Moreover, the AGD features flexible protection modes, which overcomes the interruption of converter operation in the event of momentary short circuits. A step-down converter is built to evaluate the performance of the proposed driving schemes under various conditions, considering variation of turn-on/off gate resistance, current levels, and short-circuit fault types. Experimental results and detailed analysis are presented to verify the feasibility of the proposed approach.

This paper proposes a novel packaging method for insulated-gate bipolar transistor (IGBT) modules based on the concepts of P-cell and N-cell. The novel packaging reduces the stray inductance in the current commutation path in a phase-leg module and hence improves the switching behavior. A P-cell- and N-cell-based module and a conventional module are designed. Using finite-element-analysis-based Ansys Q3D Extractor, electromagnetic simulations are conducted to extract the stray inductance from the two modules. Two prototype phase-leg modules based on the two different designs are fabricated. The parasitics are measured using a precision impedance analyzer. Finally, a double pulse tester based-switching characterization is performed to illustrate the effect of stray inductance reduction in the proposed packaging design. The experimental results show the reduction in overshoot voltage with the proposed layout.

Overcurrent protection of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) remains a challenge due to lack of practical knowledge. This paper presents three overcurrent protection methods to improve the reliability and overall cost of SiC MOSFET-based converters. First, a solid-state circuit breaker (SSCB) composed primarily by a Si IGBT and a commercial gate driver IC is connected in series with the dc bus to detect and clear overcurrent faults. Second, the desaturation technique using a sensing diode to detect the drain-source voltage under overcurrent faults is implemented as well. Third, a novel active overcurrent protection scheme through dynamic evaluation of fault current level is proposed. The design considerations and potential issues of the protection methods are described and analyzed in detail. A phase-leg configuration-based step-down converter is built to evaluate the performance of the protection schemes under various conditions, considering variation of fault type, decoupling capacitance, protection circuit parameters, etc. Finally, a comparison is made in terms of fault response time, temperature-dependent characteristics, and applications to help designers select a proper protection method.

This paper presents an improved phase disposition pulsewidth modulation (PWM) (PDPWM) for the modular multilevel converter (MMC) which is based on the selective loop bias mapping (SLBM) method. Its main idea is to change the bias of the PDPWM carrier wave cycling according to the balance situation of the system. This new modulation method can operate at symmetric condition to generate an output voltage with as many as 2N + 1 levels, and by SLBM, the voltages of the upper/lower arm capacitors can be well balanced. Compared to carrier phase-shifted PWM, this method is more easily to be realized and has much stronger dynamic regulation ability. Specially, this method has no issues of sorting, which makes it suitable for MMC with a large number of submodules in one leg. With simulation and experiments, the validity of the proposed method has been shown.

A situational awareness system is essential to provide accurate understanding of power system dynamics, such that proper actions can be taken in real time in response to system disturbances and to avoid cascading blackouts. Event analysis has been an important component in any situational awareness system. However, most state-of-the-art techniques can only handle single event analysis. This paper tackles the challenging problem of multiple event detection and recognition. We propose a new conceptual framework, referred to as event unmixing, where we consider real-world events mixtures of more than one constituent root event. This concept is a key enabler for analysis of events to go beyond what are immediately detectable in a system, providing high-resolution data understanding at a finer scale. We interpret the event formation process from a linear mixing perspective and propose an innovative nonnegative sparse event unmixing (NSEU) algorithm for multiple event separation and temporal localization. The proposed framework has been evaluated using both PSS/E simulated cases and real event cases collected from the frequency disturbance recorders (FDRs) of the Frequency Monitoring Network (FNET). The experimental results demonstrate that the framework is reliable to detect and recognize multiple cascading events as well as their time of occurrence with high accuracy.

A particle swarm optimization (PSO) algorithm-based staircase modulation strategy for modular multilevel converters (MMC) is proposed. To reduce switching losses and device stress, the staircase modulation method has been adopted in high-voltage and high-power energy conversion applications. In particular, the selection of the appropriate iterative initial values of switching angles is a significant step to realize a staircase modulated MMC. The proposed method is able to find the optimum initial values of switching angles, while it has the advantages of global optimization and quadratic convergence, which benefit from the PSO algorithm and Newton method, respectively. The paper presents analytical discussion of the voltage balancing control approach with rotation of switching angles. The main benefit of the efficient switching patterns is that the MMC has lower switching losses and minimum dV/dt stress. Simulation and experimental results are presented to verify the practical feasibility of the proposed scheme for the MMC.

The number of offboard fast charging stations is increasing as plug-in electric vehicles (PEVs) are more widespread in the world. Additional features on the operation of chargers will result in more benefits for investors, utility companies, and PEV owners. This paper investigates reactive power support operation using offboard PEV charging stations while charging a PEV battery. The topology consists of a three-phase ac-dc boost rectifier that is capable of operating in all four quadrants. The operation modes that are of interest are power-factor-corrected charging operation, and charging and capacitive/inductive reactive power operation. This paper also presents a control system for the PQ command following of a bidirectional offboard charger. The controller only receives the charging power command from a user and the reactive power command (when needed) from a utility, and it adjusts the line current and the battery charging current correspondingly. The vehicle's battery is not affected during the reactive power operation. A simulation study is developed utilizing PSIM, and the control system is experimentally tested using a 12.5-kVA charging station design.

This paper presents a front-end three-phase ac/dc power factor correction rectifier, which is based on the three-level bidirectional-switch Vienna topology. On one hand, the rectifier is designed to operate in continuous-conduction mode (CCM) at full power. However, at reduced load, it operates in discontinuous-conduction mode (DCM). On the other hand, with reduced input inductance, the DCM mode occurs even when the rectifier operates at full power. In this paper, the digitized feedfoward compensation method is proposed for the rectifier to reduce the impact of the switch between DCM and CCM. The theoretical analysis of the proposed method is deduced; furthermore, the control design strategy is given. The experimental results are obtained by using a digitally controlled Vienna rectifier, which validated the proposed compensation method.

This paper presents a summary of the available single-phase ac-dc topologies used for EV/PHEV, level-1 and -2 on-board charging and for providing reactive power support to the utility grid. It presents the design motives of single-phase on-board chargers in detail and makes a classification of the chargers based on their future vehicle-to-grid usage. The pros and cons of each different ac-dc topology are discussed to shed light on their suitability for reactive power support. This paper also presents and analyzes the differences between charging-only operation and capacitive reactive power operation that results in increased demand from the dc-link capacitor (more charge/discharge cycles and increased second harmonic ripple current). Moreover, battery state of charge is spared from losses during reactive power operation, but converter output power must be limited below its rated power rating to have the same stress on the dc-link capacitor.

In this paper, a fully integrated silicon carbide (SiC)-based six-pack power module is designed and developed. With 1200-V, 100-A module rating, each switching element is composed of four paralleled SiC junction gate field-effect transistors (JFETs) with two antiparallel SiC Schottky barrier diodes. The stability of the module assembly processes is confirmed with 1000 cycles of -40°C to +200°C thermal shock tests with 1.3°C/s temperature change. The static characteristics of the module are evaluated and the results show 55 mΩ on-state resistance of the phase leg at 200°C junction temperature. For switching performances, the experiments demonstrate that while utilizing a 650-V voltage and 60-A current, the module switching loss decreases as the junction temperature increases up to 150°C. The test setup over a large temperature range is also described. Meanwhile, the shoot-through influenced by the SiC JFET internal capacitance as well as package parasitic inductances are discussed. Additionally, a liquid cooled three-phase inverter with 22.9 cm × 22.4 cm × 7.1 cm volume and 3.53-kg weight, based on this power module, is designed and developed for electric vehicle and hybrid electric vehicle applications. A conversion efficiency of 98.5% is achieved at 10 kHz switching frequency at 5 kW output power. The inverter is evaluated with coolant temperature up to 95°C successfully.

This paper proposed an improved phase disposition pulse width modulation (PDPWM) for a modular multilevel inverter which is used for Photovoltaic grid connection. This new modulation method is based on selective virtual loop mapping, to achieve dynamic capacitor voltage balance without the help of an extra compensation signal. The concept of virtual submodule (VSM) is first established, and by changing the loop mapping relationships between the VSMs and the real submodules, the voltages of the upper/lower arm's capacitors can be well balanced. This method does not requiring sorting voltages from highest to lowest, and just identifies the MIN and MAX capacitor voltage's index which makes it suitable for a modular multilevel converter with a large number of submodules in one arm. Compared to carrier phase-shifted PWM (CPSPWM), this method is more easily to be realized in field-programmable gate array and has much stronger dynamic regulation ability, and is conducive to the control of circulating current. Its feasibility and validity have been verified by simulations and experiments.

The low power losses of silicon carbide (SiC) devices provide new opportunities to implement an ultra high-efficiency front-end rectifier for data center power supplies based on a 400-Vdc power distribution architecture, which requires high conversion efficiency in each power conversion stage. This paper presents a 7.5-kW high-efficiency three-phase buck rectifier with 480-Vac,rms input line-to-line voltage and 400-Vdc output voltage using SiC MOSFETs and Schottky diodes. To estimate power devices' losses, which are the dominant portion of total loss, the method of device evaluation and loss calculation is proposed based on a current source topology. This method simulates the current commutation process and estimates devices' losses during switching transients considering devices with and without switching actions in buck rectifier operation. Moreover, the power losses of buck rectifiers based on different combinations of 1200-V power devices are compared. The investigation and comparison demonstrate the benefits of each combination, and the lowest total loss in the all-SiC rectifier is clearly shown. A 7.5-kW prototype of the all-SiC three-phase buck rectifier using liquid cooling is fabricated and tested, with filter design and switching frequency chosen based on loss minimization. A full-load efficiency value greater than 98.5% is achieved.

A new approach for modulation of an 11-level cascade multilevel inverter using selective harmonic elimination is presented in this paper. The dc sources feeding the multilevel inverter are considered to be varying in time, and the switching angles are adapted to the dc source variation. This method uses genetic algorithms to obtain switching angles offline for different dc source values. Then, artificial neural networks are used to determine the switching angles that correspond to the real-time values of the dc sources for each phase. This implies that each one of the dc sources of this topology can have different values at any time, but the output fundamental voltage will stay constant and the harmonic content will still meet the specifications. The modulating switching angles are updated at each cycle of the output fundamental voltage. This paper gives details on the method in addition to simulation and experimental results.

This paper presents an alternative to the traditional dc-dc converter interfacing the battery with the inverter dc bus in plug-in hybrid electric vehicle (HEV) traction drives. The boost converter used in commercial HEVs meets with obstacles when it comes to upgrading the power rating and achieving high efficiency while downsizing the converter. A four-level flying-capacitor dc-dc converter is explored that can overcome these drawbacks by dramatically reducing the inductance requirement. A special case of the four-level converter, the 3X dc-dc converter, operates at three discrete output/input voltage ratios, thus further reducing the inductance requirement to a minimal value (almost zero). When further compared to its switched-capacitor dc-dc converter counterparts, the 3X dc-dc converter can be operated at variable output/input voltage ratios without sacrificing efficiency, and it lowers the capacitance requirement by utilizing the parasitic inductance. The operating principle, current ripple analysis, the transient control to limit the inrush current, and power loss analysis are introduced. Experimental results of a 55-kW prototype are provided to demonstrate the principle and analysis of this topology.

Based on the introduction of a dual-loop current control strategy for a grid-connected inverter, an averaged switching model of a grid-connected inverter with an LCL-filter in discrete domain is built under a stationary frame and a proportional resonant (PR) regulator is adopted in the current loop to track the given fundamental sinusoidal current. The impacts of PR parameters, LCL parameters and digital delay on the root locus are studied, respectively. The parameters of the LCL-filter and the PR current regulator loop are designed to assure system stability and dynamic response during a wide power range by using the pole placements method. Finally, a 10 kW prototype of a grid-connected inverter with an LCL-filter is set up to verify the effectiveness, the practicality and robustness of the proposed PR current design method.

High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 °C. This new gate driver prototype has been designed and implemented in a 0.8 μm, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 °C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature (≥220 °C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 μW for operating temperature up to 200 °C.

The application of silicon carbide (SiC) devices as battery interface, motor controller, etc., in a hybrid electric vehicle (HEV) will be beneficial due to their high-temperature capability, high-power density, and high efficiency. Moreover, the light weight and small volume will affect the whole powertrain system in a HEV and, thus, the performance and cost. In this paper, the performance of HEVs is analyzed using the vehicle simulation software Powertrain System Analysis Toolkit (PSAT). Power loss models of a SiC inverter based on the test results of latest SiC devices are incorporated into PSAT powertrain models in order to study the impact of SiC devices on HEVs from a system standpoint and give a direct correlation between the inverter efficiency and weight and the vehicle's fuel economy. Two types of HEVs are considered. One is the 2004 Toyota Prius HEV, and the other is a plug-in HEV (PHEV), whose powertrain architecture is the same as that of the 2004 Toyota Prius HEV. The vehicle-level benefits from the introduction of SiC devices are demonstrated by simulations. Not only the power loss in the motor controller but also those in other components in the vehicle powertrain are reduced. As a result, the system efficiency is improved, and vehicles that incorporate SiC power electronics are predicted to consume less energy and have lower emissions and improved system compactness with a simplified thermal management system. For the PHEV, the benefits are even more distinct; in particular, the size of the battery bank can be reduced for optimum design.

Power electronics is an enabling technology found in most renewable energy generation systems. Because of its superior voltage blocking capabilities and fast switching speeds, silicon carbide (SiC) power electronics are considered for use in power conversion units in wind generation systems in this paper. The potential efficiency gains from the use of SiC devices in a wind generation system are explored by simulations, with the system modeling explained in detail. The performance of the SiC converter is analyzed and compared to its silicon counterpart at different wind speeds, temperatures, and switching frequencies. The quantitative results are based on SiC metal-oxide-semiconductor field-effect transistor (MOSFET) prototypes from Cree and modern Si insulated-gate bipolar transistor (IGBT) products. A conclusion is drawn that the SiC converters can improve the wind system power conversion efficiency and can reduce the system's size and cost due to the low-loss, high-frequency, and high-temperature properties of SiC devices, even for one-for-one replacement for Si devices.

This work approximates the selective harmonic elimination problem using artificial neural networks (ANNs) to generate the switching angles in an 11-level full-bridge cascade inverter powered by five varying dc input sources. Each of the five full bridges of the cascade inverter was connected to a separate 195-W solar panel. The angles were chosen such that the fundamental was kept constant and the low-order harmonics were minimized or eliminated. A nondeterministic method is used to solve the system for the angles and to obtain the data set for the ANN training. The method also provides a set of acceptable solutions in the space where solutions do not exist by analytical methods. The trained ANN is a suitable tool that brings a small generalization effect on the angles' precision and is able to perform in real time (50-/60-Hz time window).

Energy infrastructure is a critical underpinning of modern society that any compromise or sabotage of its secure and reliable operation has an enormous impact on people's daily lives and the national economy. The massive northeastern power blackout of August 2003 and the most recent Florida blackout have both revealed serious defects in both system-level management and device-level designs of the power grid in handling attacks. At the system level, the control area operators lack the capability to 1) obtain real-time status information of the vastly distributed equipment; 2) respond rapidly enough once events start to unravel; and 3) perform coordinated actions autonomously across the region. At the device level, the traditional hardware lacks the capability to 1) provide reliable frequency and voltage control according to system demands and 2) rapidly reconfigure the system to a secure state through switches and power-electronics based devices. These blackouts were a wake-up call for both the industry and academia to consider new techniques and system architecture design that can help assure the security and reliability of the power grid. In this paper, we present a hardware-in-the-loop reconfigurable system design with embedded intelligence and resilient coordination schemes at both local and system levels that would tackle the vulnerabilities of the grid. The new system design consists of five key components: 1) a location-centric hybrid system architecture that facilitates not only distributed processing but also coordination among geographically close devices; 2) the insertion of intelligence into power electronic devices at the lower level of the power grid to enable a more direct reconfiguration of the physical makeup of the grid; 3) the development of a robust collaboration algorithm among neighboring devices to handle possible faulty, missing, or incomplete information; 4) the design of distributed algorithms to better understand the local state of the power grid; and 5) the adoption of a control-theoretic real-time adaptation strategy to guarantee the availability of large distributed systems. Preliminary evaluation results showing the advantages of each component are provided. A phased implementation plan is also suggested at the end of the discussion.

Silicon has long been the semiconductor of choice for such power electronics. But soon this ubiquitous substance will have to share the spotlight. Devices made from silicon carbide (SiC)-a faster, tougher, and more efficient alternative to straight silicon-are beginning to take off. Simple SiC diodes have already started to supplant silicon devices in some applica tions. And over the last few years, they've been joined by the first commercially available SiC transistors, enabling anew range of SiC-based power electronics. What's more, SiC wafer manufacturers have steadily reduced the defects in the material while increasing the wafer size, thus driving down the prices of SiC devices. Last year, according to estimates made by wafer maker Cree, the global market for silicon car bide devices topped US $100 million for the first time.

This paper will present the analytical proof of concept of the multilevel modular capacitor-clamped converter (MMCCC). The quantitative analysis of the charge transfer mechanism among the capacitors of the MMCCC explains the start-up and steady-state voltage balancing. Once these capacitor voltages are found for different time intervals, the start-up and steady-state voltages at various nodes of the MMCCC can be obtained. This analysis provides the necessary proof that explains the stable operation of the converter when a load is connected to the low-voltage side of the circuit. In addition, the analysis also shows how the LV side of the converter is (1/N)th of the HV side excitation when the conversion ratio of the circuit is N. In addition to the analytical and simulation results, experimental results are included to support the analytical proof of concept.

A three-phase insulated gate bipolar transistor (IGBT)-based static var compensator (STATCOM) is used for voltage and/or current unbalance compensation. An instantaneous power theory is adopted for real-time calculation and control. Three control schemes - current control, voltage control and integrated control - are proposed to compensate the unbalance of current, voltage or both. The compensation results of the different control schemes in unbalance cases (load current unbalance or voltage unbalance) are compared and analysed. The simulation and experimental results show that the control schemes can compensate the unbalance in load current or in the voltage source. Different compensation objectives can be achieved, that is, balanced and unity power factor source current, balanced and regulated voltage or both, by choosing appropriate control schemes.

Silicon carbide (SiC)-based field effect transistors (FETs) are gaining popularity as switching elements in power electronic circuits designed for high-temperature environments like hybrid electric vehicle, aircraft, well logging, geothermal power generation etc. Like any other power switches, SiC-based power devices also need gate driver circuits to interface them with the logic units. The placement of the gate driver circuit next to the power switch is optimal for minimising system complexity. Successful operation of the gate driver circuit in a harsh environment, especially with minimal or no heat sink and without liquid cooling, can increase the power-to-volume ratio as well as the power-to-weight ratio for power conversion modules such as a DC-DC converter, inverter etc. A silicon-on-insulator (SOI)-based high-voltage, high-temperature integrated circuit (IC) gate driver for SiC power FETs has been designed and fabricated using a commercially available 0.8--m, 2-poly and 3-metal bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) process. The prototype circuit-s maximum gate drive supply can be 40-V with peak 2.3-A sourcing/sinking current driving capability. Owing to the wide driving range, this gate driver IC can be used to drive a wide variety of SiC FET switches (both normally OFF metal oxide semiconductor field effect transistor (MOSFET) and normally ON junction field effect transistor (JFET)). The switching frequency is 20-kHz and the duty cycle can be varied from 0 to 100-. The circuit has been successfully tested with SiC power MOSFETs and JFETs without any heat sink and cooling mechanism. During these tests, SiC switches were kept at room temperature and ambient temperature of the driver circuit was increased to 200-C. The circuit underwent numerous temperature cycles with negligible performance degradation.

A 5-kW multilevel modular capacitor-clamped DC-DC converter (MMCCC) with bi-directional power management and real-time fault bypassing capability will be presented in this study. The modular structure of the MMCCC topology was utilised to build this 5-kW converter with necessary redundancy and hot swap feature for industrial and automotive applications including a future plug-in hybrid or fuel-cell powered all electric vehicles. Moreover, the circuit has flexible conversion ratio that leads to establish bi-directional power management for automotive applications mitigating the boost voltage for the fuel-cell or dual battery architecture. In addition, the MMCCC exhibits better component utilisation compared to many capacitor-clamped or classical DC-DC converters based on inductive energy transfer mechanism. Thus, the MMCCC circuit can be made more compact and reliable compared to many other DC-DC converters for high-power applications.

A multilevel modular capacitor-clamped DC-DC converter (MMCCC) will be presented in this paper with some of its advantageous features. By virtue of the modular nature of the converter, it is possible to integrate multiple loads and sources with the converter at the same time. The modular construction of the MMCCC topology provides autotransformer-like taps in the circuit, and depending on the conversion ratio of the converter, it becomes possible to connect several dc sources and loads at these taps. The modularity of the new converter is not limited to only this dc transformer (auto) like operation, but also provides redundancy and fault bypass capability in the circuit. Using the modularity feature, some redundant modules can be operated in bypass state, and during some faults, these redundant modules can be used to replace a faulty module to maintain an uninterrupted operation. Moreover, by obtaining a flexible conversion ratio, the MMCCC converter can transfer power in both directions. Thus, this MMCCC topology could be a solution to establish a power management system among multiple sources and loads having different operating voltages.

This paper presents a cascaded H-bridge multilevel boost inverter for electric vehicle (EV) and hybrid EV (HEV) applications implemented without the use of inductors. Currently available power inverter systems for HEVs use a dc-dc boost converter to boost the battery voltage for a traditional three-phase inverter. The present HEV traction drive inverters have low power density, are expensive, and have low efficiency because they need a bulky inductor. A cascaded H-bridge multilevel boost inverter design for EV and HEV applications implemented without the use of inductors is proposed in this paper. Traditionally, each H-bridge needs a dc power supply. The proposed design uses a standard three-leg inverter (one leg for each phase) and an H-bridge in series with each inverter leg which uses a capacitor as the dc power source. A fundamental switching scheme is used to do modulation control and to produce a five-level phase voltage. Experiments show that the proposed dc-ac cascaded H-bridge multilevel boost inverter can output a boosted ac voltage without the use of inductors.

This paper presents a fundamental-frequency-modulated diode-clamped multilevel inverter (DCMLI) scheme for a three-phase stand-alone photovoltaic (PV) system. The system consists of five series-connected PV modules, a six-level DCMLI generating fundamental-modulation staircase three-phase output voltages, and a three-phase induction motor as the load. In order to validate the proposed concept, simulation studies and experimental measurements using a small-scale laboratory prototype are also presented. The results show the feasibility of the fundamental frequency switching application in three-phase stand-alone PV power systems.

Silicon carbide (SiC) power devices are expected to have an impact on power converter efficiency, weight, volume, and reliability. Currently, only SiC Schottky diodes are commercially available at relatively low current ratings. Oak Ridge National Laboratory has collaborated with Cree and Semikron to build a Si insulated-gate bipolar transistor-SiC Schottky diode hybrid 55-kW inverter by replacing the Si p-n diodes in Semikron's automotive inverter with Cree's made-to-order higher current SiC Schottky diodes. This paper presents the developed models of these diodes for circuit simulators, shows inverter test results, and compares the results with those of a similar all-Si inverter.

This paper presents the various configurations of a multilevel modular capacitor-clamped converter (MMCCC), and it reveals many useful and new formations of the original MMCCC for transferring power in either an isolated or nonisolated manner. The various features of the original MMCCC circuit are best suited for a multibus system in future plug-in hybrid or fuel-cell-powered vehicles' drive train. The original MMCCC is capable of bidirectional power transfer using multilevel modular structure with capacitor-clamped topology. It has a nonisolated structure, and it offers very high efficiency even at partial loads. This circuit was modified to integrate single or multiple high-frequency transformers by using the intermediate voltage nodes of the converter. On the other hand, a special formation of the MMCCC can exhibit dc outputs offering limited isolation without using any isolation transformer. This modified version can produce a high conversion ratio from a limited number of components and has several useful applications in providing power to multiple low-voltage loads in a hybrid or electric automobile. This paper will investigate the origin of generating ac outputs from the MMCCC and shows how the transformer-free version can be modified to create limited isolation from the circuit. In addition, this paper will compare various modified forms of the MMCCC topology with existing dc-dc converter circuits from compactness and component utilization perspectives.

This paper presents a cascaded H-bridge multilevel inverter that can be implemented using only a single dc power source and capacitors. Standard cascaded multilevel inverters require n dc sources for 2n + 1 levels. Without requiring transformers, the scheme proposed here allows the use of a single dc power source (e.g., a battery or a fuel cell stack) with the remaining n-1 dc sources being capacitors, which is referred to as hybrid cascaded H-bridge multilevel inverter (HCMLI) in this paper. It is shown that the inverter can simultaneously maintain the dc voltage level of the capacitors and choose a fundamental frequency switching pattern to produce a nearly sinusoidal output. HCMLI using only a single dc source for each phase is promising for high-power motor drive applications as it significantly decreases the number of required dc power supplies, provides high-quality output power due to its high number of output levels, and results in high conversion efficiency and low thermal stress as it uses a fundamental frequency switching scheme. This paper mainly discusses control of seven-level HCMLI with fundamental frequency switching control and how its modulation index range can be extended using triplen harmonic compensation.

A multilevel DC-DC power conversion system with multiple DC sources is proposed in this paper. With this conversion system, the output voltage can be changed almost continuously without any magnetic components. With this magnetic-less system, very high temperature operation is possible. Power loss and efficiency analysis is provided in the paper. Comparison results show that the system does not require more semiconductors or capacitance than the traditional boost converter. Experimental results are provided to confirm the analysis and control concept.

This paper presents a reduced switching-frequency active-harmonic-elimination method (RAHEM) to eliminate any number of specific order harmonics of multilevel converters. First, resultant theory is applied to transcendental equations to eliminate low-order harmonics and to determine switching angles for a fundamental frequency-switching scheme. Next, based on the number of harmonics to be eliminated, Newton climbing method is applied to transcendental equations to eliminate high-order harmonics and to determine switching angles for the fundamental frequency-switching scheme. Third, the magnitudes and phases of the residual lower order harmonics are computed, generated, and subtracted from the original voltage waveform to eliminate these low-order harmonics. Compared to the active-harmonic-elimination method (AHEM), which generates square waves to cancel high-order harmonics, RAHEM has lower switching frequency. The simulation results show that the method can effectively eliminate all the specific harmonics, and a low total harmonic distortion (THD) near sine wave is produced. An experimental 11-level H-bridge multilevel converter with a field-programmable gate-array controller is employed to experimentally validate the method. The experimental results show that RAHEM does effectively eliminate any number of specific harmonics, and the output voltage waveform has low switching frequency and low THD.

Indirect field-oriented control of an induction machine requires knowledge of the rotor time constant to estimate the rotor flux linkages. Here, an online method is presented for estimating the rotor time constant and the stator resistance, both of which vary during operation of the machine due to ohmic heating. The method uses measurements of the stator voltages, stator currents, and their derivatives (first derivative of the voltages and both the first and second derivatives of the currents). The problem is formulated as finding those parameter values that best fit (in a least-squares sense) the model of the induction motor to the measured output data of the motor. This method guarantees that the parameter values are found in a finite number of steps. Experimental results of an online implementation are presented

A method is proposed to estimate the rotor time constant TR of an induction motor without measurements of the rotor speed/position. The method consists of solving for the roots of a polynomial equation in TR whose coefficients depend only on the stator currents, stator voltages, and their derivatives. Experimental results are presented

Fuel cells are considered to be one of the most promising sources of distributed energy because of their high efficiency, low environmental impact and scalability. Unfortunately, multiple complications exist in fuel cell operation. Fuel cells cannot accept current in the reverse direction, do not perform well with ripple current, have a low output voltage that varies with age and current, respond sluggishly to step changes in load and are limited in overload capabilities. For these reasons, power converters are often necessary to boost and regulate the voltage as a means to provide a stiff applicable DC power source. Furthermore, the addition of an inverter allows for the conversion of DC power to AC for an utility interface or for the application of an AC motor. To help motivate the use of power conditioning for the fuel cell, a brief introduction of the different types, applications and typical electrical characteristics of fuel cells is presented. This is followed by an examination of the various topologies of DC-DC boost converters and inverters used for power conditioning of fuel cells. Several architectures to aggregate multiple fuel cells for high-voltage/high-power applications are also reviewed.

A generalised instantaneous non-active power theory is presented. Comprehensive definitions of instantaneous active and non-active currents, as well as instantaneous, average and apparent powers, are proposed. These definitions have flexible forms that are applicable to different power systems, such as single-phase or multi-phase, periodic or non-periodic and balanced or unbalanced systems. By changing the averaging interval and the reference voltage, various non-active power theories can be derived from this theory. The definitions of instantaneous active and non- active currents provide an algorithm for a STATCOM to calculate the non-active current in the load current. The theory is implemented by the STATCOM, and four cases (three-phase balanced RL load, three-phase unbalanced RL load, diode rectifier load and single-phase load) are tested. The experimental results show that the STATCOM can perform instantaneous non-active power compensation, and both the fundamental non-active component and the harmonics are eliminated from the utility so that nearly unity power factor can be achieved. The STATCOM also has a fast dynamic response for transients.

The key of reactive power planning (RPP), or Var planning, is the optimal allocation of reactive power sources considering location and size. Traditionally, the locations for placing new Var sources were either simply estimated or directly assumed. Recent research works have presented some rigorous optimization-based methods in RPP. This paper will first review various objectives of RPP. The objectives may consider many cost functions such as variable Var cost, fixed Var cost, real power losses, and fuel cost. Also considered may be the deviation of a given voltage schedule, voltage stability margin, or even a combination of different objectives as a multi-objective model. Secondly, different constraints in RPP are discussed. These different constraints are the key of various optimization models, identified as optimal power flow (OPF) model, security-constrained OPF (SCOPF) model, and SCOPF with voltage-stability consideration. Thirdly, the optimization-based models will be categorized as conventional algorithms, intelligent searches, and fuzzy set applications. The conventional algorithms include linear programming, nonlinear programming, mixed-integer nonlinear programming, etc. The intelligent searches include simulated annealing, evolutionary algorithms, and tabu search. The fuzzy set applications in RPP address the uncertainties in objectives and constraints. Finally, this paper will conclude the discussion with a summary matrix for different objectives, models, and algorithms.

In this paper, a fault diagnostic system in a multilevel-inverter using a neural network is developed. It is difficult to diagnose a multilevel-inverter drive (MLID) system using a mathematical model because MLID systems consist of many switching devices and their system complexity has a nonlinear factor. Therefore, a neural network classification is applied to the fault diagnosis of a MLID system. Five multilayer perceptron (MLP) networks are used to identify the type and location of occurring faults from inverter output voltage measurement. The neural network design process is clearly described. The classification performance of the proposed network between normal and abnormal condition is about 90%, and the classification performance among fault features is about 85%. Thus, by utilizing the proposed neural network fault diagnostic system, a better understanding about fault behaviors, diagnostics, and detections of a multilevel inverter drive system can be accomplished. The results of this analysis are identified in percentage tabular form of faults and switch locations

This paper presents a two-phase cooling method using the R134a refrigerant to dissipate the heat energy (loss) generated by power electronics (PEs), such as those associated with rectifiers, converters, and inverters for a specific application in hybrid-electric vehicles. The cooling method involves submerging PE devices in an R134a bath, which limits the junction temperature of PE devices while conserving weight and volume of the heat sink without sacrificing equipment reliability. First, experimental tests that included an extended soak for more than 850 days were performed on a submerged insulated gate bipolar transistor (IGBT) and gate-controller card to study dielectric characteristics, deterioration effects, and heat-flux capabilities of R134a. Results from these tests illustrate that R134a has high dielectric characteristics and no deterioration of electrical components. Second, experimental tests that included a simultaneous operation with a mock automotive air-conditioner (A/C) system were performed on the same IGBT and gate-controller card. Data extrapolation from these tests determined that a typical automotive A/C system has more than sufficient cooling capacity to cool a typical 30-kW traction inverter. Last, a discussion and simulation of active cooling of the IGBT junction layer with the R134a refrigerant is given. This technique will drastically increase the forward current ratings and reliability of the PE device

A fault diagnostic and reconfiguration method for a cascaded H-bridge multilevel inverter drive (MLID) using artificial-intelligence-based techniques is proposed in this paper. Output phase voltages of the MLID are used as diagnostic signals to detect faults and their locations. It is difficult to diagnose an MLID system using a mathematical model because MLID systems consist of many switching devices and their system complexity has a nonlinear factor. Therefore, a neural network (NN) classification is applied to the fault diagnosis of an MLID system. Multilayer perceptron networks are used to identify the type and location of occurring faults. The principal component analysis is utilized in the feature extraction process to reduce the NN input size. A lower dimensional input space will also usually reduce the time necessary to train an NN, and the reduced noise can improve the mapping performance. The genetic algorithm is also applied to select the valuable principal components. The proposed network is evaluated with simulation test set and experimental test set. The overall classification performance of the proposed network is more than 95%. A reconfiguration technique is also proposed. The proposed fault diagnostic system requires about six cycles to clear an open-circuit or short-circuit fault. The experimental results show that the proposed system performs satisfactorily to detect the fault type, fault location, and reconfiguration.

A novel topology of a multilevel modular capacitor-clamped dc-dc converter will be presented in this paper. In contrast to the conventional flying capacitor multilevel dc-dc converter, this new topology is completely modular and requires a simpler gate drive circuit. Moreover, the new topology has many advantageous features such as high frequency operation capability, low input/output current ripple, low on-state voltage drop, and bidirectional power flow management. This paper discusses the construction and operation of the new converter along with a comparison to a conventional converter. Finally, simulation and experimental results are used to validate the concept of this new topology.

This paper proposes two constant boost-control methods for the Z-source inverter, which can obtain maximum voltage gain at any given modulation index without producing any low-frequency ripple that is related to the output frequency and minimize the voltage stress at the same time. Thus, the Z-network requirement will be independent of the output frequency and determined only by the switching frequency. The relationship of voltage gain to modulation index is analyzed in detail and verified by simulation and experiments.

This note considers a differential-algebraic approach to estimating the speed of an induction motor from the measured terminal voltages and currents. In particular, it is shown that the induction motor speed /spl omega/ satisfies both a second- and a third-order polynomial equation whose coefficients depend on the stator voltages, stator currents, and their derivatives. It is shown that as long as the stator electrical frequency is nonzero, the speed is uniquely determined by these polynomials. The speed so determined is then used to stabilize a dynamic (Luenberger type) observer to obtain a smoother speed estimate. With full knowledge of the machine parameters and filtering of the sensor noise, simulations indicate that this estimator has the potential to provide low speed (including zero speed) control of an induction motor under full rated load.

This paper presents an active harmonic elimination method to eliminate any number of specific higher order harmonics of multilevel converters with equal or unequal dc voltages. First, resultant theory is applied to transcendental equations characterizing the harmonic content to eliminate low order harmonics and to determine switching angles for the fundamental frequency switching scheme and a unipolar switching scheme. Next, the residual higher order harmonics are computed and subtracted from the original voltage waveform to eliminate them. The simulation results show that the method can effectively eliminate the specific harmonics, and a low total harmonic distortion (THD) near sine wave is produced. An experimental 11-level H-bridge multilevel converter with a field programmable gate array controller is employed to implement the method. The experimental results show that the method does effectively eliminate any number of specific harmonics, and the output voltage waveform has low THD.

In this letter, a genetic algorithm (GA) optimization technique is applied to determine the switching angles for a cascaded multilevel inverter which eliminates specified higher order harmonics while maintaining the required fundamental voltage. This technique can be applied to multilevel inverters with any number of levels. As an example, in this paper a seven-level inverter is considered, and the optimum switching angles are calculated offline to eliminate the fifth and seventh harmonics. These angles are then used in an experimental setup to validate the results.

Eliminating harmonics in a multilevel converter in which the separate dc sources vary is considered. That is, given a desired fundamental output voltage, the problem is to find the switching times (angles) that produce the fundamental while not generating specifically chosen harmonics. Assuming that the separate dc sources can be measured, a procedure is given to find all sets of switching angles for which the fundamental is produced while lower order harmonics are eliminated. This is done by first converting the transcendental equations that specify the elimination of the harmonics into an equivalent set of polynomial equations. Then, using the mathematical theory of resultants, all solutions to this equivalent problem can be found. Experimental results are presented to validate the theory.

This paper presents a regenerative passive snubber circuit for pulse-width modulation (PWM) inverters to achieve soft-switching purposes without significant cost and reliability penalties. This passive soft-switching snubber (PSSS) employs a diode/capacitor snubber circuit for each switching device in an inverter to provide low dv/dt and low switching losses to the device. The PSSS further uses a transformer-based energy regenerative circuit to recover the energy captured in the snubber capacitors. All components in the PSSS circuit are passive, thus leading to reliable and low-cost advantages over those soft-switching schemes relying on additional active switches. The snubber has been incorporated into a 150 kVA PWM inverter. Simulation and experimental results are given to demonstrate the validity and features of the snubber circuit.

The problem of eliminating harmonics in a switching converter is considered. That is, given a desired fundamental output voltage, the problem is to find the switching times (angles) that produce the fundamental while not generating specifically chosen harmonics. In contrast to the well known work of Patel and Hoft and others, here all possible solutions to the problem are found. This is done by first converting the transcendental equations that specify the harmonic elimination problem into an equivalent set of polynomial equations. Then, using the mathematical theory of resultants, all solutions to this equivalent problem can be found. In particular, it is shown that there are new solutions that have not been previously reported in the literature. The complete solutions for both unipolar and bipolar switching patterns to eliminate the fifth and seventh harmonics are given. Finally, the unipolar case is again considered where the fifth, seventh, 11th, and 13th harmonics are eliminated along with corroborative experimental results.

A method is presented to compute the switching angles in a multilevel converter so as to produce the required fundamental voltage while at the same time not generate higher order harmonics. Using a staircase fundamental switching scheme, previous work has shown that this is possible only for specific ranges of the modulation index. Here it is shown that, by considering all possible switching schemes, one can extend the lower range of modulation indices for which such switching angles exist. A unified approach is presented to solve the harmonic elimination equations for all of the various switching schemes. In particular, it is shown that all such schemes require solving the same set of equations where each scheme is distinguished by the location of the roots of the harmonic elimination equations. In contrast to iterative numerical techniques, the approach here produces all possible solutions.

This article describes a proof-of-concept development for a 7.5 kW gen-set in a family of military gen-sets in the 5 to 60 kW range. Several power electronic converters have been implemented in the design of this proof-of-concept gen-set that is lighter, smaller, and more fuel efficient than conventional fixed-speed gen-sets. The unit also has the flexibility of several selectable voltage and frequency options that greatly reduces the inventory logistics burden for a family of different unit types and sizes. With integrated controls and power electronics, the gen-set is able to run at its most efficient condition to minimize fuel consumption. It would also be possible to control the gen-set such that it ran at other different optimized conditions such as: maximum headroom for supplying load transients; most audibly quiet; and least polluting for certain emissions.

This paper presents a new definition of nonactive current from which the definitions of instantaneous active and nonactive power are also derived. The definitions are consistent with the traditional power definitions and valid for single-phase and polyphase systems, as well as periodic and nonperiodic waveforms. The definitions are applied to a shunt compensation system. The paper elaborates on the compensation of three different cases of nonperiodic current: single-phase disturbance, three-phase subharmonics, and three-phase stochastic current. Simulation results give credibility to the applicability of the definition for a diversity of load currents. According to different compensation cases and the goals to be achieved, different averaging time intervals for the compensator are chosen which will determine the compensator's energy storage requirement and the extent of residual distortion in the source current.

In this work, a method is given to compute the switching angles in a multilevel converter to produce the required fundamental voltage while at the same time cancel out specified higher order harmonics. Specifically, a complete analysis is given for a seven-level converter (three dc sources), where it is shown that for a range of the modulation index m/sub I/, the switching angles can be chosen to produce the desired fundamental V/sub 1/=m/sub I/(s4V/sub dc///spl pi/) while making the fifth and seventh harmonics identically zero.

The emergence of silicon carbide (SiC) based power semiconductor switches, with their superior features compared with silicon (Si) based switches, has resulted in substantial improvement in the performance of power electronics converter systems. These systems with SiC power devices have the qualities of being more compact, lighter, and more efficient; thus, they are ideal for high-voltage power electronics applications. In this study, commercial Si pn and SiC Schottky diodes are tested and characterized, their behavioral static and loss models are derived at different temperatures, and they are compared with respect to each other.

This paper presents transformerless multilevel converters as an application for high-power hybrid electric vehicle (HEV) motor drives. Multilevel converters: (1) can generate near-sinusoidal voltages with only fundamental frequency switching; (2) have almost no electromagnetic interference or common-mode voltage; and (3) make an HEV more accessible/safer and open wiring possible for most of an HEV's power system. The cascade inverter is a natural fit for large automotive hybrid electric drives because it uses several levels of DC voltage sources, which would be available from batteries, ultracapacitors, or fuel cells. Simulation and experimental results show how to operate this converter in order to maintain equal charge/discharge rates from the DC sources (batteries, capacitors, or fuel cells) in an HEV.

This paper presents the development of a control scheme for a multilevel diode-clamped converter connected in a series-parallel fashion to the electrical system such that it can compensate for deviations in utility voltage (sag, surge, and unbalance) and act as a harmonic and/or reactive current source for a load. New carrier-based multilevel pulsewidth modulation techniques are identified to maximize switch utilization of the two back-to-back diode-clamped inverters that constitute the universal power conditioner. An experimental verification for a six-level power conditioner is given.

When utilized at low amplitude modulation indices, existing multilevel carrier-based PWM strategies have no special provisions for this operating region, and several levels of the inverter go unused. This paper proposes some novel multilevel PWM strategies to take advantage of the multiple levels in both a diode-clamped inverter and a cascaded H-bridges inverter by utilizing all of the levels in the inverter even at low modulation indices. Simulation results show what effects the different strategies have on the active device utilization. A prototype 6-level diode-clamped inverter and an 11-level cascaded H-bridges inverter have been built and controlled with the novel PWM strategies proposed in this paper.

This paper presents transformerless multilevel power converters as an application for high-power and/or high-voltage electric motor drives. Multilevel converters: (1) can generate near-sinusoidal voltages with only fundamental frequency switching; (2) have almost no electromagnetic interference or common-mode voltage; and (3) are suitable for large voltampere-rated motor drives and high voltages. The cascade inverter is a natural fit for large automotive all-electric drives because it uses several levels of DC voltage sources, which would be available from batteries or fuel cells. The back-to-back diode-clamped converter is ideal where a source of AC voltage is available, such as in a hybrid electric vehicle. Simulation and experimental results show the superiority of these two converters over two-level pulsewidth-modulation-based drives.

The advent of the transformerless multilevel inverter topology has brought forth various pulsewidth modulation (PWM) schemes as a means to control the switching of the active devices in each of the multiple voltage levels in the inverter. An analysis of how existing multilevel carrier-based PWM affects switch utilization for the different levels of a diode-clamped inverter is conducted. Two novel carrier-based multilevel PWM schemes are presented which help to optimize or balance the switch utilization in multilevel inverters. A 10 kW prototype six-level diode-clamped inverter has been built and controlled with the novel PWM strategies proposed in this paper to act as a voltage-source inverter for a motor drive.

Lightning continues to be the major cause of outages on overhead power distribution lines. Through laboratory testing and field observations and measurements, the properties of a lightning stroke and its effects on electrical distribution system components are fairly well-understood phenomena. A meticulous compilation of 32 years of historical records has been kept for outage causes, duration, and locations for eight distribution feeders at the Oak Ridge National Laboratory (ORNL). Due to the limited growth of ORNL, the number, length, and location of the 13.8 kV overhead lines have remained the same between 1960 and 1992. Except for noted differences (voltage construction class, length, age, and maximum elevation above a reference level), other factors that could influence the reliability of an overhead line have remained nearly the same. This allowed a meaningful reliability study to be performed on the entire ORNL electrical distribution system. In this article, the main findings of the reliability assessment as it relates to lightning-resistant overhead line construction techniques are out-lined, and a simple and cost-effective method to reduce lightning caused outages is offered. In addition, comparisons are made between the failure rates and causes experienced at ORNL and those in industry surveys. Where large discrepancies exist between survey data and experiences at ORNL, evidence is presented to explain the differences between ORNL's distribution system and those typical of industry.

A direct induction machine torque control method based on predictive, deadbeat control of the torque and flux is presented. By estimating the synchronous speed and the voltage behind the transient reactance, the change in torque and flux over the switching period is calculated. The stator voltage required to cause the torque and flux to be equal to their respective reference values is calculated. Space vector PWM is used to define the inverter switching state. An alternative approach to deadbeat control for use in the transient or pulse-dropping mode is also presented. An alternative modulation scheme is presented in which transient performance is improved by specifying the inverter switching states and then calculating the required switched instants to maintain deadbeat control of the flux while reducing the torque error during the entire switching interval. A similar approach is used for a transient in the flux. The implementation of the control scheme using DSP-based hardware is described, with complete experimental results given.<>

Nonlinear magnetic properties in power electronics applications, such as permeability and core loss cause significant discrepancies between magnetic designs and prototype measurements, leading to iterative prototyping efforts. To address this issue, a bottom-up approach that is based on the physics of magnetic material is proposed to unveil the fundamental origin of nonlinearity. The physical parameters such as magnetization, gyromagnetic ratio, damping factor, etc., are translated to equivalent circuit parameters. The nonlinear magnetization dynamics of a single magnetic domain are described by an equivalent circuit model derived from the Landau-Lifshitz-Gilbert (LLG) equation. A fictitious magnetic domain is used to demonstrate the developed model’s capability on predicting the nonlinearity that includes magnetization dynamics and hysteresis. Then, the model is further validated by a commercial material, TDK N87 toroidal core. The results such as B-H loop and permeability simulated from the circuit model are in close agreement with the datasheet, validating the feasibility of predicting magnetic material’s nonlinear performance from physics perspective rather than empirical approaches.

Negative-sequence (NS) current sharing among different grid-forming (GFM) sources is a critical issue in islanded microgrids (MGs). Existing sharing strategies only focus on the NS current distribution among inverter-based resources (IBRs). However, existing approaches have not fully considered the NS current sharing among IBRs and SGs and are easily affected by line impedances. In this paper, a leader-follower-based approach is proposed for the NS current sharing among IBRs and SGs. The leader IBR, attempting to regulate the bus NS voltage to zero, generates the total NS current references. The NS current references are distributed to follower IBRs. After the IBRs’ NS currents track the references, the SGs’ NS currents is subsequently determined. The proposed control strategy is verified through both simulation and experimental testing on a converter-based hardware testbed.

Microgrids usually consist of inverter-based resources (IBRs), so it is essential to test their control parameters to ensure their dynamic response. At CURENT, a converter-based hardware testbed (HTB) was developed to emulate power systems in real-time to overcome the limitations of computer simulations such as computation convergence, initial conditions, and processor capability. However, to test a microgrid in the existing HTB platform required modification of the topology and line impedances compared to that used to represent transmission lines. Therefore, a converter-based microgrid platform has been developed on the existing HTB to enable changing inverter control parameters in real-time. This microgrid platform development has the capability to test a PI controller of IBRs in real-time. The design of the converter-based microgrid platform is introduced, and the experimental results are provided.

The 10-kV SiC device imposes high insulation requirements on the corresponding power stage design. As the voltage stress and clearance distance increases, achieving a compact design of the converter will be challenging. In this paper, a compact power stage design is realized by adopting a new heatsink configuration. With the new heatsink configuration, a field shaping structure is proposed to suppress concentrated electric field close to the edges, so that the clearance between heatsinks can be reduced. Simulation and experimental tests have validated the design. The proposed design has been tested up to 6250 V/10 A, and the gate drive and bus-bar design are also discussed in this paper.

To dissipate heat effectively, a sufficient cooling system is required for a five-level MMC (Modular Multilevel Converter) based on 10 kV, 100 A power modules. However, achieving efficient heat dissipation necessitates a large cooling system, which in turn reduces the overall power density of the converter. Additionally, ensuring proper insulation between the high voltage switching devices and cooling components poses another challenge. This paper addresses these issues by presenting a detailed numerical design procedure for liquid cooling and selecting appropriate coolant with high dielectric strength. Air cooling with specific clearance and creepage distances is also presented. These two types of cooling methods are compared in terms of thermal performance, size, cost and installation effort. The effectiveness of the design is validated through experimental measurements.

This paper presents the design of a megawatts (MW) level modular multilevel converter (MMC) phase-leg for 13.8 kV medium voltage (MV) grid based on Wolfspeed 10 kV SiC MOSFET XHV-9 half bridge module. Compared with the 10 kV SiC single die discrete device, the 10 kV SiC multi-die module has higher di/dt, higher dv/dt (for loss reduction), and more stringent protection requirement, posing new challenges on the MW-level MV power converter design based on this 10 kV SiC module. Detailed MMC submodule and system design to address these challenges are presented. A protection strategy for this 10 kV SiC MOSFET power module is proposed, which can detect the short circuit within 200 ns and effectively limit short circuit current to within 200 A for short circuit fault at 6 kV dc voltage. Hardware is built and experimental results of the MMC submodule test at 6 kV dc voltage, MMC phase-leg test at 12 kV dc voltage, and 8-level converter test up to 23 kV are demonstrated and verify the effectiveness of the presented design.

This paper presents the switching cell design for medium voltage (MV) flying capacitor converter (FCC) with emerging 10 kV SiC MOSFET using a 5-level FCC for the 13.8 kV MV grid as an example. The design of flying capacitors and decoupling capacitors to achieve compact size, loop inductance minimization, high voltage insulation, and good scalability is discussed. The flying capacitor switching cell double pulse test (FCC-DPT) concept is proposed for switching evaluation. With detailed switching loop characterization and analysis, the switching speed of this 10 kV 20 A SiC MOSFET discrete device is pushed to exceed 100 V/ns. Hardware of the 5L-FCC phaseleg is built and continuous power test experimental results up to 23 kV dc voltage are demonstrated.

Asynchronous microgrid (ASMG) with a power conditioning system (PCS) is a promising solution for future microgrids (MGs). High voltage (HV, >3.3 kV) SiC device-based PCS is becoming more and more popular in the ASMG PCS implementation. PCS with HV SiC MOSFETs can realize higher control frequencies with lower losses to bring numerous system-level benefits, which have not been fully investigated in the existing literature. In this paper, the active power filtering (APF) capability of the HV SiC-based PCS for both grid and MG power quality improvement is discussed and demonstrated. A harmonic impedance-based APF algorithm is proposed for MG-side PCS. The PCS APF functions are demonstrated on a 10 kV SiC MOSFET-based PCS prototype with the modular multi-level converter (MMC) topology to 19th-order harmonic currents.

A new modeling framework and optimization approach is proposed for co-optimization of both switched reluctance machine (SRM) design and control across the entire torque-speed range. Custom modeling codes use static finite element analysis (FEA) results to determine optimal current profiles and conventional control conditions for discrete speeds, torques, and torque ripple levels. A machine design optimization method is proposed that leverages outputs from control optimization and determines quality metrics for each design based on the efficiency and torque ripple across the operation envelope. Simulations are validated through empirical testing across the entire torque-speed operation range as comparisons of transient FEA, custom models, and tests are presented.

The integration of distributed generation (DG) into electric grid systems results in some significant consequences for the protection of distributed systems. Distributed systems that have high penetration of inverter-based distributed generation (IDG) will have changes in fault current levels causing traditional overcurrent protective devices to not operate as intended. As a result, distributed systems require new protection schemes to deal with the wide varieties of IDG, which need significant investment in the protection devices. This paper discusses the impact of IDGs on the protection of the distributed system. To solve the issues faced in grids with IDG, a fault detection method that utilizes instantaneous power theory is proposed. Simulation and experimental results illustrate how this theory can be used to detect faults even with low fault current levels.

This paper, to the best knowledge of the authors, for the first time reports the packaging of a 100kW three-level active neutral point clamped (3L-ANPC) phase leg power module for electric vehicle (EV) traction inverter applications using 650V/150A e-mode gallium nitride high-electron-mobility transistors (GaN HEMTs). Compared with two-level (2L) half bridge power module, the main challenges of packaging a 3L-ANPC phase leg power module are high number of switches (6 switches vs 2 switches) and multiple commutation loops (1 commutation loop vs 4 commutation loops). In addition, there are four switches involved in the two long commutation loops. Those parasitic loop inductances must be minimized simultaneously. Those challenges are addressed by meticulous packaging of the power module, featuring low power loop inductances, double-sided cooled power module, low junction-to-coolant thermal resistance, symmetrical layout for the two parallel dies of each switch and mechanical robustness, etc. The simulated loop inductances are 1.92nH for the short loops and 5.21nH for the long loops, respectively; resulting in a 471V and 540V of turn-off voltage spikes in a double pulse test simulation at 400V/200A. The simulated junction-to-coolant thermal resistances are 0.37°C/W and 0.53°C/W for different switches, respectively.

As the utilization of supercapacitors in power system applications continues to increase, it is important to observe their behavior under transient and long-term operations in order to understand their impact on power grids. A real-time reconfigurable hardware testbed (HTB) is a power network emulator that provides flexibility to study various power system scenarios. This paper presents an emulation of a supercapacitor for a photovoltaic (PV) system on the HTB platform such that its dynamic behavior during power system scenarios can be observed. The developed emulator on the HTB is verified by comparing the emulation results with the model developed in MATLAB/Simulink. The experimental results of the emulator are consistent with the simulation results under the grid support scenarios. This supercapacitor emulator can be potentially used for various power system scenarios in addition to the PV applications presented in this paper.

Severe electromagnetic interference (EMI) issues in wide-bandgap (WBG) power electronics systems result in larger filter sizes to attenuate noise, which compromises the high power density brought by WBG devices. To mitigate the high-frequency EMI noises of WBG systems, integrating a common-mode filter inside the power module is an effective way of managing parasitics in the noise propagation paths and thereby improving the filter performance. However, the magnetic core of a common-mode choke (CMC) takes up considerable height and weight, which lowers the power density of a module. In this paper, an air-cured and module-compatible manufacturing methodology is developed using permalloy-epoxy magnetic composites for the integrated CMC inside a GaN power module.The magnetic composite is mixed into a paste texture and can conveniently mold the power module to form the CMC, improving the space utilization and power density of the whole module. This also offers a potential magnetic integration solution for other WBG power modules or circuits. One of the composites has a real part of the complex permeability of 13.5 under high frequency with low core-loss density. A 3-D finite-element model is built to predict the inductance of the over-molded CMC cured with the designed magnetic composite. The manufacturing process of the over-molded CMC is explained and the impact of the magnetic material on the power module parasitics is analyzed. The benefits of the over-molded CMC in EMI reduction and power density improvement are verified by test results, and some suggestions for future optimization are provided.

The parasitic capacitance of a power module baseplate provides a path for displacement current during the switching transient of the power module, which causes extra switching loss and EMI noise. It becomes an increasing concern especially for emerging 10 kV SiC MOSFET modules due to their high voltage and fast switching speed. This paper presents an in-depth analysis of 10 kV SiC MOSFET module baseplate parasitic capacitance impact on switching loss. The turn-on switching energy is divided into four parts, and the module baseplate parasitic capacitance impact on each part of the energy is analyzed. In addition to a constant capacitive energy (i.e., $\displaystyle \frac{1}{2}$ CV2), the module baseplate parasitic capacitance also introduces extra V-I overlap energy during voltage fall stage of the turn-on switching transient because it increases voltage fall time. This portion of loss is modeled and quantified. The module baseplate parasitic capacitance impact on switching loss is experimentally evaluated at 6 kV dc voltage and 0 to 50 A currents. This 10 kV SiC MOSFET module baseplate capacitance contributed loss is in the 5-10% range.

In this paper, a 50-kW 1-kV/6.25-kV medium voltage dual-active-bridge (DAB) transformer has been designed and tested. The shell-type transformer structure with stacked small cores is selected to integrate the leakage inductance and reduce the eddy current loss. Dry-type insulation with selective shielding is adopted and both winding-to-ground and winding turn-to-turn insulation are considered. The transformer geometry-based design procedure is discussed to achieve high efficiency and power density considering the effect of eddy current loss and insulation constraint. Tests up to the full voltage and power were performed and the DAB transformer achieved 99.66% full-load efficiency and 13.5 kW/L density for the transformer.

This paper presents a state of charge (SOC) management strategy to ensure low-voltage ride-through (LVRT) services of a grid-connected photovoltaic (PV) with a supercapacitor (SC) energy storage system (PVSS). A concept of SOC reservation for LVRT operations is introduced to guarantee that the PV grid-connected system can provide LVRT services complying with grid code requirements. SOC management is derived by considering SC limitations, the current rating of the converters, and grid conditions. Therefore, safe operation of the power system and PVSS can be achieved. The study also adopts an electrothermal model of the SC to adjust the current set points during SOC management by considering the temperature-dependent SC parameters; thus, both safety and full utilization of the SC can be achieved. Consequently, SOC management can rapidly be accomplished, thereby increasing the certainty of providing LVRT services to the system.

Electromagnetic energy harvesters (EMEHs) have the potential to harvest various energy forms from different frequencies. But there is no AC-DC power converter that can achieve impedance matching for multi-input of a single energy harvester to extract maximum power from all frequency points. The article proposes a new AC-DC converter based on feedforward control to realize variable input impedance under different input frequencies. The article proposes an auxiliary coil to obtain the reference signal for feedforward control. The model of the auxiliary coil is built to guide the design. The AC-DC converter realizes variable impedance matching at different frequencies using an auxiliary coil. The article also analyzes the impedance mismatching loss caused by current ripple and builds a numerical calculation model. It can provide guidance for the design of key parameters, such as threshold voltage. The article designs a prototype of the AC-DC converter and EMEH with auxiliary coils. According to the measurement, the MPPT efficiency of the AC-DC converter is 98.7% at input frequency of 50 Hz and 97.7% at 1000 Hz. The converter transmission efficiency is 86.3%. The output voltage of AC-DC converter is 5 V with load resistor of 837 Ω. The overall of the multi-input energy harvesting system is 84.8%.

This work focuses on a comparison between the effects, on an electrical power system, of adopting, for three-phase inverters, a three-phase averaged Volt/Var algorithm, as proposed by IEEE 1547 standard, and employing three, separate, control references for each phase. In order to carry out its proposal, two daily simulations were performed on the IEEE 34-Bus test case feeder. Three-phase phovoltaic systems were placed across the feeder, and, for each batch of power flows, they were configured to apply each one of the evaluated control algorithms. The single-phase Volt/Var performed significantly better, while not producing higher losses. Depending on the conditions of the circuit, it could also be observed that there may be a higher or lower effort from the inverters in order to satisfy the requested reactive power output demanded by the algorithm.

This paper presents temperature sensitive electrical parameters (TSEPs) selection for a 10 kV silicon carbide (SiC) MOSFET power module. Static parameters including ON-state resistance and threshold voltage are introduced. A double pulse test (DPT) platform is built to test the power module on a hotplate, and the switching transient behavior in a temperature range from 25℃ to 125℃ is analyzed in detail. Various parameters during turn on and turn off are measured and compared based on their temperature linearity and sensitivity. Load current and gate resistance impacts on measurement are discussed, as well as comparisons to low voltage SiC MOSFETs.

This paper presents a low cost Si IGBT circuit breaker for protection of the Wolfspeed 10 kV XHV-9 half bridge SiC MOSFET module. Based on the 10 kV SiC module short circuit (SC) protection requirement, both current limiting and desaturation protection are needed for this IGBT breaker. Voltages balancing for series-connected IGBTs and effective current limiting of this IGBT breaker during SC transient are discussed. Detailed modes transition between the 10 kV SiC module and the IGBT breaker during SC transient is analyzed. Demonstration of the 10 kV SiC module with the IGBT breaker SC test and continuous power test at 6 kV voltage are presented.

This paper presents a half-bridge submodule design based on a 10 kV SiC MOSFET XHV-9 power module. The design of the gate driver, isolated power supply, and busbar are presented. High voltage insulation capability, fast short circuit protection, and resilience to EMI of the designed submodule are demonstrated through continuous power tests at 6.5 kV, 57 A and through a short circuit test. This submodule verification facilitates the adoption of high-voltage SiC MOSFETs in medium-voltage (MV) converters, shedding light on highly efficient power conditioning systems (PCS) for grid applications.

A hybrid microgrid is an attractive concept that aims to deliver energy to local ac and dc loads, reducing the strain imposed on the electrical grid. A hybrid microgrid of a flexible manufacturing plant consists of dc and ac loads, and distributed energy resources interfaces with the distributed grid through a power conditioning system to enable grid support capabilities and control power flow. To evaluate the controller functions of the hybrid microgrid, an appropriate testing platform is required. In this paper, the plant is emulated via a converter-based hardware testbed. The developed hardware testbed serves as a realistic model of the flexible manufacturing plant to test the controls and different scenarios to address potential issues or challenges with the control strategies and algorithms before system deployment. In addition, the hardware testbed provides the opportunity to validate the system’s response under different operating conditions in a controlled environment, leading to a more robust and reliable system design.

This paper proposes a novel design for grid-tied 3-ph Photovoltaic (PV) inverter to improve its low-voltage ride through (LVRT) response while significantly increasing its voltampere reactive (VAR) support during voltage sags. The literature available on LVRT for PV inverters can be grouped in solutions that dissipate the excess energy and those that temporary stores this energy. This paper proposes a third solution; oversizing inverter hardware components to safely transferring all the energy excess back to while maintaining the semiconductor under the maximum temperature limits. The advantages of the proposed approach are: 1) Improved LVRT capabilities and stable dc-link voltage control at MPP during sags. 2) Increased VAR support during voltage sags. 3) Increased use of renewable energy as all active power is injected back to the grid during voltage sags. Finally, the proposed solution is more cost effective compared with solutions that incorporate energy storage because only a few inverter components are required to be oversized. This paper also presents a detailed power loss analysis, which determined that that oversizing the power semiconductors has minimal impact in the inverter losses while significatively reducing the diode and IGBT conduction losses during both normal operation and grid fault conditions.

This paper proposes a high-efficiency single-phase GaN-based T-type totem-pole front-end rectifier with reactive power transfer. A full-range zero voltage switching (ZVS) modulation approach for both unity power factor (PF) operation and non-unity PF operation is proposed for the GaN-based rectifier in critical conduction mode (CRM) operation. T-type mode operation and switching frequency limitation are proposed to overcome the ac-line zero-crossing challenges. A digital-based control strategy is also proposed to regulate the active power and reactive power simultaneously. A 1.6 kVA prototype of the T-type totem-pole rectifier is built and demonstrated with full-range ZVS operation, 98.9% full-load efficiency, and flexible reactive power regulation.

This paper discusses the impact of parasitic inductances on the electromagnetic interference (EMI) performance at radiated frequency and provides a new concept for high-frequency wide bandgap (WBG) power module package design with integrated $\pi$-type common mode filter ($\pi$-CMF). The connection parasitic-inductances of a $\pi$-type CMF model are analyzed, and the parasitic inductances from the CMF to the CM noise source and to the heatsink are minimized to improve the CMF's EMI performance in the radiated frequency range. Therefore, placing the $\pi$-CMF closer to the power module (i.e. in-package CMF) provides a larger noise attenuation compared to placing it outside the module (i.e. external CMF). To verify the theoretical analysis, a half-bridge GaN power module with an in-package $\pi$-CMF is designed, and experiments are conducted by comparing the attenuated noise spectrums of a 70-V/1.75-A hard-switching buck converter built by the designed module with an external CMF and the power-module integrated CMF. According to the experiment results, up to $10\ \text{dB}\mu\mathrm{V}$ more attenuation is achieved by the in-package CMF than the external CMF, validating the analytical conclusion.

Microgrids (MGs) with dynamic boundaries and multiple source locations have been proposed as a future MG concept, which requires sophisticated control and coordination. Testing of MG controllers in a realistic environment becomes essential for the efficient and reliable deployment of such MGs. A converter-based testing platform has been proposed for MG controller evaluation, which requires well-modeled emulators. However, as a core component, existing battery energy storage system (BESS) emulators in the literature cannot meet the testing needs of the M G with dynamic boundaries and multiple source locations. In this paper, a BESS emulator for controller testing of M G with dynamic boundaries and multiple source locations is developed, considering controller functions, different operation modes, and transition coordination. Experimental results are conducted to verify the developed emulator on a converter-based testbed.

Previous work on real-time simulation of DFIGs have assumed that the generator model is valid over a wide range of operating speeds and for multiple grid voltage unbalances. However, this assumption has not been tested in the literature, which limits the accuracy of results obtained in both simulations and in hardware-in-the-loop (HIL) applications. To address this gap in the literature, this paper presents a preliminary model validation of the DFIG with iron losses and demonstrates the limitations of the model in accurately representing a physical DFIG machine under grid unbalanced operation. This paper implements all the required discrete models for real-time emulation of the DFIG on a field programmable gate array (FPGA), including: the dynamic model of the DFIG, rotor side converter (RSC), grid side converter (GSC), and aerodynamic and mechanical models. Also included are key implementation aspects of the hardware-testbed utilized for the model validation, which consists of a DFIG machine connected to a partial-scaled four-quadrant back-to-back power converter. The DFIG machine models utilized for this research are available to the public and can be accessed in a GitHub repository listed in the references.

In this paper, an embedded GaN half-bridge power module with double-sided cooling, low inductance, low thermal resistance, on-package decoupling capacitors, localized common mode filter, and integrated gate drivers is proposed. The two GaN dies are embedded in a printed circuit board (PCB) with heat dissipation paths to a ceramic substrate from both sides of the devices to achieve double-sided cooling capability. Thermal and electrical performance are fully analyzed and optimized. A low-cost module assembly procedure is presented utilizing standard layer attaching process. Finally, a compact $\mathbf{2.7}\ \mathbf{cm} \times \mathbf{1.8}\ \mathbf{cm}$ half-bridge GaN power module is fabricated to verify both electrical and thermal performance through experiments. The switching performance of the power module is tested under 400 V/25 A double-pulse test that shows the power loop inductance is as low as 1.03 nH and the overshoot voltage of the switching waveform is less than 5% of the dc bus voltage. The thermal resistance is verified to be 0.32 K/W, and the fabricated power module is employed in a buck converter with 500 W output power at 600 kHz switching frequency.

The resiliency offered by a microgrid may be lost if the microgrid is not properly protected during short-circuit faults inside its boundaries. Many studies conclude that protecting microgrids in islanded mode is very challenging due to the limited short-circuit capability of distributed energy resources (DERs). The limited short-circuit capability of DERs typically inhibits the use of reliable and affordable overcurrent protective devices in microgrids. Although extensive research on microgrid protection is available in the literature, to date this research has not led to a cost-effective, commercially available relay that effectively tackles the challenges of microgrid protection. This work proposes hardware modifications to enhance the current contribution of an energy storage inverter with the objective of enabling the use of legacy overcurrent protection for islanded microgrids. This paper demonstrates through experimental results that few modifications are required in the inverter to significantly enhance its current contribution. In this study, a three-phase energy storage inverter was modified to provide three times its rated current during three-phase faults, which proved sufficient current for enough time to enable fuse-relay, and relay-to-relay coordination. The proposed modifications effectively increase the current contribution of the inverter, which is a promising advancement to allow the adoption of overcurrent protective devices for protecting microgrids.

The emerging 10 kV SiC MOSFET brings great benefits for medium and high voltage applications, and is drawing increased research attention. Accurate switching transient modeling of the 10 kV SiC MOSFET is critical for successful application. Curve tracer is usually used to extract parameters needed for device modeling. However, the transconductance extracted from curve tracer is tested at low voltage, which is different from the transconductance during actual high voltage turn-on switching transient because of short channel effect and drain induced barrier lowering effect. Moreover, the gate-drain capacitance extracted from curve tracer is tested at static off-state, which is also different from the gate-drain capacitance during dynamic turn-on switching transient as the MOSFET channel is turned on in this process. Conventional models based on curve tracer tests show obvious discrepancies compared to experiments. This paper investigates and characterizes the high voltage transconductance and dynamic gate-drain charge of the 10 kV SiC MOSFET during turn-on switching transient. An improved turn-on switching transient model considering these factors is proposed. Experiments with the 10 kV 20 A SiC MOSFET are conducted and verify the accuracy of the proposed improved model.

An investigation of a resonant reactive shielding coil for wireless power transfer (WPT) systems is presented in this work. The shielding coil attenuates the magnetic field above and to the side of air-core WPT coils. A parameterized coil model is used to allow arbitrary circular winding geometry and current direction. Detailed modeling and mathematical calculations are provided, and an optimized design algorithm is proposed. The design method is validated using an experimental prototype shielding coil applied to a 3.03 MHz electric vehicle (EV) WPT system operating at 500 W output power. Experimental results show that the peak flux density on the top-center area of the coil is suppressed from 105 μT to 50 μT, and the magnetic field to the side of the vehicle is maintained well below the safety standard. In addition, effect of the shielding coil in WPT systems with metal and ferrite plates is investigated.

Data centers have become a widespread power electronics (PE) load, with significant impact on the power grid. In order to investigate data centers’ load characteristic and help evaluate the grid dynamic performance, this work develops a data center power emulator based on a reconfigurable PE converter-based hardware testbed (HTB). A complete dynamic power model is proposed which can precisely predict the data center dynamic performance. Based on the model, the data center power emulator is implemented in two voltage source inverters (VSIs) as an all-in-one load in the HTB. The proposed emulator has been verified experimentally in a regional network. Dynamic performances during voltage sag events are emulated and discussed. The emulator provides an effective, easy-to-use tool to better design the data center and study the power system.

Grid-forming converters have recently been gaining more interest as a viable alternative to replace bulk synchronous generation for supporting and sustaining medium to low voltage grids. While the ability of grid-connected converters to support bulk generation has been thoroughly investigated, the capacity and behavior of converters that would replace bulk generation are not well defined. In an inverter-dominated system with one or more grid-forming inverters, maintaining dc-link stability is equally, if not more, important as maintaining frequency stability. To this end, and to better understand the behavior of grid-forming converters with different types of controllers, this paper derives the small-signal models for converters with nested and single-loop control structures, and compares their input and output impedance characteristics with and without synchronization. The analysis of input impedance provides insight into the impact of each grid-forming converter controller on upstream (dc) elements such as the dc-link and non-stiff dc sources, while the analysis of output impedance provides insight into the interaction of the controller with downstream (ac) elements of the grid such as the line impedance and loads. The analytical results are verified using simulation and experimental measurements.

An asynchronous microgrid (ASMG) with silicon carbide (SiC) MOSFET-based power conditioning system (PCS) is an attractive option for future microgrids, which can potentially improve microgrid dynamic performance and grid power quality. To support future microgrids’ needs for higher power, scaling PCS power via paralleling multiple modules or converters is a potential solution. In this paper, a strategy for scalable ASMG PCS operation is proposed. MMC-based PCSs are implemented to demonstrate the proposed strategy, including MMC paralleling operation analysis and corresponding control functions. Experimental results are provided to demonstrate the scalable PCS operation at 25 kV rated voltage.

Asynchronous microgrid (ASMG) is a microgrid concept where the ac microgrid is connected to a utility grid through a power conditioning system (PCS). The development of high voltage (HV, >3.3 kV) silicon carbide (SiC) MOSFET technology promotes the implementation of ASMG PCS converters. However, the system-level benefits from SiC MOSFETs have not been well studied for this application. This paper discusses ASMG system stability enhancement resulting from HV SiC MOSFET-based PCS converters. HV SiC MOSFET-based PCS converters can achieve high control frequency, which can benefit the potential harmonic instability caused by the digital control delay. A detailed theoretical analysis is provided, and experimental results for the stability enhancement capability are demonstrated on a converter-based hardware testbed (HTB).

This paper provides an analysis of the desat protection for high voltage (>3.3 kV) SiC MOSFETs from the perspective of noise immunity. The high positive dv/dt with long voltage rise time generated by high voltage SiC MOSFETs is identified as a major threat to noise immunity of the desat protection circuitry. The impact of numerous influencing factors is analyzed, such as parasitic inductance, damping resistance, and clamping impedance. In some cases, small parasitic capacitances (<0.01 pF) between the drain terminal with high dv/dt and protection circuitry dominate the noise immunity of the desat protection circuitry with high-impedance voltage divider. The noise immunity margin is derived quantitatively to guide the noise immunity improvement. Different noise immunity enhancement methods are developed and validated with experimental results, including adding a shielding layer, reducing clamping impedance, and decreasing voltage divider impedance.

Power electronic systems (PES) incorporate complex Intra-system communication, which are of vital importance for the successful operation of these systems. This paper proposes and outlines a communication testbed that will help in the development and testing of the communications between the components of PES. It allows for the comparison and evaluation of different communication methods, such as MQTT, Modbus, or User Datagram Protocol (UDP), and for the characterization of how these communication protocols perform.

Medium voltage (MV) asynchronous microgrids have numerous unique benefits over regular synchronous MV ac microgrids. This paper focuses on a MV transformer less asynchronous microgrids power conditioning system (PCS) using 10 kV SiC MOSFETs. The benefits of a 10 kV SiC MOSFET based PCS include simplified topology, higher control bandwidth, and hence more advanced control functions, although it is still challenging to apply 10 kV SiC MOSFETs with their associated much faster switching speed in MV systems. A modular design approach is adopted in the design and implementation of the PCS as well as its controller. The sophisticated grid functions of the asynchronous microgrid PCS are supported by a hierarchical modular control system. A 100 kVA back-to-back transformer less PCS for a 13.8 kV MV grid is developed and tested at rated voltage and power.

A new modeling and optimization approach is proposed for co-optimization of both switched reluctance machine (SRM) design and control across the entire speed range. A unique method uses static finite element analysis (FEA) results to determine a set of current profiles for discrete speeds, torques, and torque ripple levels, and the associated voltage profiles are computed using steady state equations without time-domain simulations. Particle swarm optimization is implemented to determine optimal current profiles with the consideration of voltage limits, torque ripple, and other system parameters. Further, a machine design optimization method is proposed that leverages outputs from current profile optimizers and determines quality metrics for each design based on the torque requirements and torque ripple limits across the operation region of the targeted application.

Increasing the resiliency of distribution systems through the use of advanced controls and the engagement of distributed energy resources (DERs) has been gaining attention. However, there is no available tool to evaluate resilience considering advanced technology in the distribution grid. This paper presents a method to quantitatively evaluate the resilience improvement of a distribution system after deploying self-healing control, microgrid and transactive energy systems. The proposed method is based on the time-sequential Monte Carlo simulation and considers the complexity of a real distribution system. Additionally, a heuristic algorithm is developed to find a practical service restoration strategy based on the three-phase power flow constraints and topology constraints. Characterized by its simplified computation process, the proposed algorithm applies to the long-term resilience evaluation. Case study on a real distribution system shows that the resilience of both the critical load and the system is greatly improved.

Reactive power support is a part of ancillary services that is becoming more important due to an increase of distributed energy resources (DERs) in today’s power systems. The intermittent nature of the DERs also increases the challenges of voltage management in power systems, and limitations of power system reinforcement are becoming a bottleneck to improving reliability of power systems. Thus, cooperation of existing equipment, including utility-owned and nonutility-owned assets, can be utilized to achieve higher reliability of the system. A transactive energy approach is proposed to coordinate the nonutility DERs to participate in reactive power support. Voltage sensitivity is used to determine the impact of DERs at different locations that will simultaneously participate in a reactive power market. The modified DERs’ supply curve is constructed to evaluate the impact of DERs’ locations based on the transactive energy approach. The performance of the proposed method is validated by comparing to other location-based and non-location-based reactive power dispatch methods. An implementation of the modified DER’s supply curve can successfully improve the voltage at the target location by an amount that is specified by the system.

Power system simulations with long-term data tend to have large time steps varying from one second to a few minutes. However, for PV inverter semiconductors, the minimum thermal stresses cycle is with line frequency. This requires the time step of the fatigue simulation to be much smaller than the line period. This small time step results in poor simulation speed, especially for long-term simulations. This paper proposes a fast fatigue simulation for inverter semiconductors using the quasi-static time series (QSTS) simulation concept. The fatigue analysis typically focuses on the peak and valley values of a strain and neglect the transients from peaks to valleys. The proposed simulation utilizes this property of fatigue analysis and calculates the steady state of the semiconductor junction temperature only. The resulting time step of the fatigue simulation is 15 minutes, which is consistent with the solar dataset without losing accuracy.

As two effective ways to enhance power system reliability, self-healing control and microgrids have been implemented in advanced distribution systems. This paper presents a quantitative approach to assess the benefits of deploying self-healing control and/or a microgrid in improving distribution system reliability. The proposed method utilizes time-sequential Monte Carlo simulation method and further integrates the service restoration and three-phase power flow constraints to accommodate practical distribution system complexity. To reduce the computation burden in searching for optimal service restoration strategy, this paper proposes a heuristic algorithm to find a practical service restoration strategy according to the topology constraints and the constraints of three-phase power flow. Tests on a four-feeder distribution system show that both the system-level reliability and the critical load level reliability are significantly improved after deploying the self-healing control and microgrid.

In paralleled three-phase three-level voltage source inverters, sometimes the currents of paralleled inverters need to be separately adjusted to control power sharing, and the reference vectors will differ in phase and amplitude. In other cases, although the current references of the paralleled inverters are set to be the same, the d-axis and q-axis current closed-loop control outputs of each converter cannot be exactly the same due to the asymmetry in hardware or software. As a result, the reference vector of each inverter may also be different in terms of phase and amplitude. When conventional three-level space vector pulse width modulation (SVPWM) is applied, periodical jump can be observed in the phase current of each inverter and the zero sequence circulating current (ZSCC). This paper investigates the current jump phenomenon in paralleled three-level inverters with space vector modulation (SVM). The mechanism that causes the current jump is illustrated. A modulation method to eliminate this current jump is proposed. Simulation and experimental results are presented to verify the effectiveness of the proposed method and conducted analysis.

This paper presents the modeling and analysis of zero common-mode voltage (ZCMV) pulse width modulation with dead-time for three-level voltage source inverters. Analytical model to calculate phase output voltage harmonic of three-level inverter with ZCMV modulation is developed. With ZCMV modulation, the common-mode voltage (CMV) of a three-level inverter can be eliminated in theory. However, CMV reduction performance is limited by dead-time in practical applications. Hence, the harmonic characteristics of CMV is modeled and analyzed considering dead-time. Experiments are conducted on a three-level neutral point clamped inverter with ZCMV modulation, and verify the accuracy of developed models.

The residential air-conditioner (A/C) is one of the most widespread load types for a household in the U.S., and it is reported that the malfunction of A/C load influences the performance of the transmission network. However, the lack of accurate modeling of A/C loads limits the effectiveness of evaluating power system dynamic performance and grid stability analysis. A real-time power emulator for an A/C motor using a three-phase voltage source inverter (VSI) is proposed in this paper, which emphasizes the "point-on-wave" characteristics of the A/C load. The proposed VSI based A/C emulator is advantageous since it demonstrates an accurate dynamic performance without sacrificing the computational resources and simulation time. The experimental results verify the accuracy of the A/C load emulator. Furthermore, the fault-induced delayed voltage recovery (FIDVR) events are emulated and analyzed in a multiconverter based hardware test bed (HTB) by using the proposed A/C load emulator. In addition, experiments emulating the dynamic response of the A/C load driven by the power electronics (PE) interface is also performed in the HTB, verifying that the application of PE-interface-driven A/C motor can contribute to alleviating the FIDVR event.

Turn-on loss is the dominant part of the switching loss for SiC MOSFETs in hard switching. The turn-on loss is difficult to reduce with conventional voltage source gate drives (VSG) because of limited gate voltage rating and large internal gate resistance of SiC MOSFETs. A charge pump gate drive (CPG) is presented in this paper that can help improve the switching speed and reduce turn-on loss. By pre-charging the charge-storage capacitor in the gate drive with a charge pump circuit, the gate drive output voltage is pumped up to provide higher gate current during the turn-on transient. Moreover, due to the charge transfer from the charge-storage capacitor to the MOSFET gate capacitance, the pumped output voltage can naturally drop back to a normal value, avoiding gate overcharging. The structure of the gate drive is simple, and no additional control is needed. The proposed CPG is verified with double pulse tests. The turn-on switching time is reduced by 67.4% at full load condition with the proposed CPG.

Medium voltage (MV) power converters using high voltage (HV) Silicon Carbide (SiC) power semiconductors result in great benefits in weight, size, efficiency and control bandwidth. However, HV SiC MOSFET based converters suffer from high dv/dt (>100 V/ns). Under high dv/dt environment, sensors are easily interfered due to the power electronic device’s fast switching. In this paper, the noise coupling mechanism in a submodule (SM) voltage sensor is analyzed, and the impact of SM voltage sensor noise on MMC phase-leg operation is discussed. A simulation model and a 10 kV SiC MOSFET based MMC prototype with 25 kV dc-link are built to validate the analysis of the impact.

This work focuses on improving voltage sensor noise immunity in a high voltage and high dv/dt environment. This is demonstrated in a 10 kV SiC MOSFET based Modular Multilevel Converter phase leg. The design is improved through several iterations while employing methodologies such as shielding, PCB layout techniques, improving the signal-to-noise ratio, and reducing the bandwidth of the sensor to reduce the noise impact of the high dv/dt of the SiC device. The impact of each methodology on the design is stressed, and the final version of the sensor shows significant improvement in noise immunity while offering the best high voltage design available.

In a modular multilevel converter (MMC) working as a rectifier, digital controllers are widely adopted and usually have three control loops: an inner ac current loop, an outer dc voltage loop, and a circulating current suppression loop. The main design constraint on these control loops is the control delay, which may cause system instability. A few previous papers have analyzed this issue, but only MMC inverter with circulating current proportional integral (PI) control was investigated. In this paper, the generation mechanism of control delay in each control loop of an MMC rectifier is analyzed. Small-signal loop gain models for all the three loops are developed. Based on the control loop models, design cases are examined, and a delay compensation scheme is implemented as an example. Both simulations and experiments validate the effectiveness of the analytical models.

This paper focuses on a robust 10 kV SiC MOSFET gate driver with an improved desaturation protection scheme for overcurrent protection. The gate driver is designed for 10 kV/20 A SiC MOSFETs in a modular multilevel converter (MMC) submodule. The gate driver has short circuit protection, status feedback in every switching cycle, dead time insertion, and undervoltage lockout (UVLO) function to support robust continuous operation of the MOSFET and converter. Practical design considerations are elaborated to achieve these functions. With a digital blanking time of 600 ns, the improved desat protection achieves a response time of <350 ns under hard switching fault (HSF), and a response time of <200 ns under fault under load (FUL) and flashover fault. All functions of the gate driver are fully validated in a MMC submodule with a rated dc-link voltage of 6.5 kV.

In this work, we develop a methodology and tool to quantitatively evaluate the reliability of a self-healing system that considers practical distribution system features such as the distributed energy resources, microgrids, and service restoration strategies. Also, this paper addresses various practical issues when being applied to an actual Duke Energy distribution system, including the design of feasible and practical service restoration strategies that are used to identify the customer interruptions after a fault, and the incorporation of the utility's historical reliability indices that are used to calibrate the failure rate and repair time of distribution system components such as overhead lines and underground cables. This case study demonstrates the effectiveness of the proposed method.

Asynchronous microgrid with PCS converter is a new microgrid concept with potentially better performance compared to conventional microgrid. In this paper, a PCS converter controller is designed and tested fully considering different grid requirements including different microgrid operation modes as well as normal and fault grid conditions. The controller architecture and functions are presented. The developed controller is tested on a scaled converter-based hardware test-bed.

Variable speed drives (VSDs) have been gaining more popularity in recent years, since they not only improve the motor load performance, but also can provide grid frequency support after a grid disturbance. However, the existing open loop grid frequency control scheme restricts the power support performance provided by VSDs. In this paper, a closed loop primary frequency support scheme adopted by the VSD is proposed for grid frequency enhancement. Additionally, a real-time power emulator for a passive-front-end VSD using a three-phase voltage source converter (VSC) is developed, which is used for analog testing environment. The developed VSD load emulator demonstrates an accurate dynamic performance without sacrificing the computational resources and simulation time. The accuracy of the VSD load emulator has been verified by experimental results. Furthermore, the grid frequency support provided by VSD loads is performed in the multi-converter based hardware test-bed (HTB) by using the proposed VSD power emulator.

Conventional numerical integration based simulation methods for modular multilevel converters (MMCs) need small integration time-steps to ensure simulation accuracy, which leads to a huge computation burden and limits the simulation speed. An analytical approach is proposed in this paper to reduce the computation burden and improve the time performance. Between any two adjacent switching moments, the MMC can be modeled by linear ordinary differential equations which can be quickly solved via eigenvalue decomposition techniques. A single phase 3-level MMC is used to test the proposed analytical approach and compare it with the Euler forward method in terms of simulation accuracy and computation time. The result shows that the analytical approach can greatly reduce the computation burden and simulation time without much trade-off in simulation accuracy.

The behavior of 10 kV SiC MOSFETs during a flashover fault condition is investigated comprehensively. A larger turn-off gate resistance R_g,off is recommended for 10 kV SiC MOSFETs without Kelvin source to avoid very asymmetrical gate resistance, while a small R_g,off is recommended for 10 kV SiC MOSFETs with Kelvin source. Guidelines regarding gate loop inductance and selecting an external capacitor across gate and source terminal are also provided. 10 kV SiC MOSFETs have much higher energy loss under flashover fault compared to typical short circuit faults. The required response time for short circuit protection to safely clear flashover fault should be at least 350 ns shorter than the response time designed to clear conventional short circuit faults.

CURENT's grid emulator contains multiple inverters to mimic the behaviors of several grid elements. The filtering inductor at the ac terminal of an inverter filters out the switching ripple current. However, the voltage on the point of common coupling (PCC) still contains switching harmonics. A decoupling capacitor at the PCC can effectively suppress the switching ripple voltage and improve voltage quality of the grid emulator. This paper provides a reduced order model of the multi-inverter system. With this reduced model, the PCC voltage harmonics can be derived. The decoupling capacitor of the PCC is designed to suppress the switching ripple based on the reduced model. Simulation and experimental results are provided to validate the proposed model and the decoupling capacitor design.

A test scheme is designed to qualify MMC submodules based on 10 kV SiC MOSFETs comprehensively, including thermal design, insulation design, and operation under high dv/dt. In the test scheme, the essential step is the continuous test realized with the proposed ac-dc continuous test circuit with two MMC submodules in series. With the designed modulation scheme, two cascaded submodules are leveraged to generate high dv/dt. The submodule under test has to continuously withstand 2X normal dv/dt of 10 kV SiC MOSFETs, which could occur during the MMC converter operation. Higher dv/dt can also be generated to fully test the submodule. An open loop voltage balancing method is adopted to simplify the continuous test setup. Simulation and experimental results are provided to validate the proposed test scheme.

PV inverters can provide ancillary services while simultaneously providing active power. A transactive energy system (TES) incentivizes a PV inverter to provide ancillary services and compensates for the cost of additional power losses due to additional reactive power production. However, providing ancillary services can shorten the lifetime of the PV inverter since additional reactive power increases the thermal stress of it. This paper models the lifetime shortening effect of a PV inverter when providing ancillary services. Based on the lifetime estimation, an improved marginal cost curve of reactive power generation for the PV inverter is proposed. The improved marginal cost considers the normalized lifetime (NLT) of the PV inverter given the active power, reactive power, and ambient temperature. The proposed NLT algorithm is validated by a simulation case study.

The fast development of the 10-kV SiC MOSFET demands for high-insulated gate drive power supply (GDPS) with low inter-winding-capacitance, low load-regulation-rate, and high conversion-efficiency. This paper presents a comparative study of primary-side-regulated (PSR) and secondary-side-regulated (SSR) GDPS for 10-kV SiC MOSFETs. Design considerations, including high-insulated transformer design, output voltage regulation scheme, and control IC selection, are evaluated. To verify the theoretical analysis, two types of GDPSs are fabricated and tested in the lab, and the experimental results show that the PSR GDPS has better performance because of lower inter-winding-capacitance, lower load-regulation-rate, and higher conversion efficiency.

Y-Matrix Modulated (YMM) Modular Multilevel Converter (MMC) was proposed recently. This modulation utilizes the self-voltage balancing capability of an MMC so that the conventional voltage balancing algorithm of MMC can be eliminated. YMM demonstrates that MMC has inherent self-voltage balancing capability. However, YMM assumes the voltage drop on the arm inductor to be zero to achieve MMC self-voltage balancing. This paper quantitatively justifies the zero voltage drop assumption for YMM based MMC and derives the general state-space model for MMC. Based on the general state-space model, the time-domain state variable dynamics are derived. The arm inductor assumption is justified by using the state variable dynamics. A criterion to determine the arm inductance value is given in this paper to quantify the zero voltage drop assumption. Simulation studies are provided to verify the state-space model derivation and the quantification of arm inductors.

Grid-connected full bridge inverters typically have a bulky electrolytic dc capacitor to absorb the unbalanced power from the ac side. The electrolytic capacitors are vulnerable and normally have shorter lifetime than other components in the converter. In most full-bridge inverter applications, the dc voltage is required to be relatively constant. However, in reactive power compensation applications, such as solid-state variable capacitor (SSVC), the constant dc-bus voltage is unnecessary since the dc bus is floating. This paper proposes a three-phase dc capacitor-less SSVC, which removes the electrolytic dc capacitor from the circuit by releasing the constraints on dc bus voltage fluctuation. The dc voltage is supported by ac side voltage directly. The remaining dc capacitance has a value of only 3% compared to that of the conventional three-phase SSVC. The proposed three-phase dc capacitor-less SSVC is validated by simulation.

To enable better voltage regulation in power systems with high penetration of photovoltaics (PV) and other distributed energy resources (DERs), inverters are now being required to provide reactive power support to the grid in addition to providing real power generated by PV panels. This paper develops a framework that coordinates the support from DER-based inverters, which are grid-connected non-utility assets, by using a transactive energy approach. Results of the implementation demonstrate participation of DER-based inverters can be achieved by using the coordination between distributed controllers and a centralized controller. With the transactive energy approach, both the customer and utility can achieve benefits that meet their individual needs.

Asynchronous microgrid with power condition system (PCS) converter is a potential future application area of medium voltage converters. However, there has been only limited research focusing on actual implementation of PCS converters. This paper describes the controller development of a 13.8 kV, silicon carbide (SiC) MOSFET-based dc/ac four-wire modular multi-level converter (MMC) for an asynchronous microgrid considering grid requirements. Control architecture and detailed central and phase controller functions are discussed. Experimental results under balanced and unbalanced load conditions are demonstrated.

Virtual synchronous generator (VSG) control allows renewable energy sources to behave like traditional synchronous generators under grid disturbances. Under large disturbances, due to the limitation of output current from grid interfacing power electronic converters, VSG controlled sources may output less active power than the emulated SG. Analysis of a single machine infinite bus system shows that the limited current would impair the system transient stability by increasing the acceleration area during a short circuit fault, and decreasing the deceleration area after it. A mitigation method is then proposed to compensate the negative impacts. Experiments with an emulated downscaled multiple machine system are shown to demonstrate the feasibility of the proposed method.

Fast electric vehicle(EV) charging stations have become one of the fastest-growing penetrated power electronics (PE) interfaced loads to the electric power system. The lack of accurate model of the fast EV charger in transient stability (TS) simulation tools limits the effectiveness of power system dynamic performance evaluation and stability analysis. In this paper, The electromechanical model of a fast EV charging unit is proposed, which is suitable for large-scale power system dynamic analysis in TS simulators. The EV charger model is simplified to guarantee a balance between model accuracy and simplicity. The validity of the proposed model has been demonstrated by a comparative study with the benchmark model created in PSCAD/EMTDC.

A method to determine the individual cell voltage in a multilevel converter through the output voltage is introduced. This technique can estimate the cell voltages without any knowledge of the controller switching sequence and can provide updated voltages within a quarter cycle. Estimates are obtained by using k-means algorithm to cluster the measured output data and determine cell voltage levels. Experimental results show that this technique can be applied in real time applications to add resiliency or reduce number of voltage sensors.

Power electronic converter will be a key enabler for future electrified aircraft propulsion system. In aircraft applications, superconducting technologies such as superconducting motors and generators along with supporting power systems will grow in importance. Utilizing cryogenic cooling for power converter potentially can significantly improve the inverter system efficiency and specific power. This paper presents the cooling, hardware, and testing of a cryogenically-cooled MW inverter developed for electrified aircraft propulsion system. The 1 MVA full load testing with cryogenic cooling is demonstrated. The developed inverter system achieves 18 kVA/kg specific power and 99% efficiency, which provides a promising solution to achieve high power density and efficiency for future electrified aircraft propulsion system.

In wireless power transfer systems, active rectifiers demonstrate improved efficiency and regulation capability. To enable impedance or output regulation, ensure stable operation, and maximize the efficiency, switching actions of the rectifier have to be synchronized with the magnetic field generated from the transmitter coil. This work presents an implementation of a phase- locked-loop synchronization controller using commercial components, including a low-cost microcontroller. A discrete-time small-signal model is used to derive the transfer function of the inherent feedback and design a compensator stabilizing the synchronization loop. Large-signal state-space modeling is used to design a high-efficiency, soft-switching, 6.78MHz power stage. A low-profile, 40W, GaN-based rectifier prototype is designed and built to experimentally verify the ability to synchronize and achieve high efficiency due to soft-switching.

The soft-switching gallium-nitride (GaN) based critical conduction mode (CRM) totem-pole power factor correction (PFC) converter is a good candidate for the front-end rectifier in wireless power transfer (WPT) applications. In multi-receiver MHz WPT systems, the PFC converter is required to have fast dynamic response and noise immunity. In this work, a GaN-based CRM totem-pole PFC converter is designed for a multi-receiver wireless charging power supply. Digital-based variable on-time control is used to achieve the zero voltage switching (ZVS) within the whole line cycle, and a voltage-loop controller with notch filters is designed to improve the transient response. The impact of high-frequency noise on the sensing signals and ZVS control are analyzed, and implementation methods are proposed to mitigate the disturbances. A GaN-based CRM totem-pole PFC that is demonstrated with 98.5% full-load efficiency is built as the first stage in the transmitter of a 100 W 6.78 MHz multi-receiver WPT system. The noise immunity of the CRM PFC is verified by testing the whole WPT system. Experimental results show that the system end-to-end efficiency at full load is 90.16%, and fast dynamic response is achieved during load variation.

Data center energy usage is expected to grow in the coming years with the proliferation of cloud services on daily life. The increasing energy demands that data centers will place upon the power grid necessitate the development high efficiency, high power density power supplies. The LLC resonant converter has long been utilized for data center power supplies as the dc-dc transformer to step down the voltage rectified from the ac transmission system to the rack level. As more is demanded of the data center and more information must be processed, space becomes more valuable. The use of wide bandgap materials such as Gallium Nitride (GaN) allows for much faster switching which can lead to higher power density by reducing the size of passive components. However, a higher frequency can lead to much greater switching loss. Zero-voltage switching (ZVS) can be utilized in primary side devices to greatly reduce losses. The achievement of ZVS is dependent on the magnetic design of the LLC transformer. By considering the effects of device capacitance and transformer parasitic capacitance and inductance, ZVS can be achieved to negate the turn-on losses and ensure high efficiency. This paper details the analysis of ZVS for a GaN-based LLC resonant converter with two series-parallel connected transformers.

An analytical model for the device drain-source turn-on overvoltage in three-level active neutral point clamped (3L-ANPC) converters is established in this paper. Considering the two commutation loops in the converter, the relationship between the turn-on overvoltage and the loop inductances is evaluated. The line switching frequency device usually exhibits higher overvoltage, while the high switching frequency device is not strongly influenced by the multiple loops. A 500 kVA 3L-ANPC converter using SiC MOSFETs is tested, and the model is verified with the experimental results.

In paralleled voltage source inverters (VSI), circulating current has both high frequency and low frequency components, and its spectrum highly depends on the modulation scheme. Previous research has mostly focused on the circulating current suppression for paralleled two-level VSIs. Little literature exists on similar analysis for paralleled three-level VSIs using space vector modulation. A detailed circulating current spectrum on full frequency range has not been well developed. This paper presents an improved analytical model for three-level space vector modulation (SVM), considering the impacts of regularly sampled reference and dead time. Then, circulating harmonic currents are determined across the full frequency range for various interleaving angles of two three-level ANPC inverters. The calculated harmonics are also verified by experimental results.

With conventional voltage source gate drives (VSG), the switching speed of SiC MOSFETs is difficult to increase due to large internal gate resistance, high Miller voltage, and limited gate voltage rating. This paper analyzes the requirement of current source gate drive (CSG) for SiC MOSFETs and proposes a CSG that can improve the switching speed and reduce switching loss. With the introduction of bi-directional switches, the influence of the large internal gate resistance of the SiC MOSFET can be mitigated, and sufficient gate current can be guaranteed throughout the switching transient. Therefore, the switching time and loss is reduced. The CSG can be controlled to be a VSG during steady state so the current of the gate drive is discontinuous and the stored energy of the inductor can be returned to the power supply to reduce gate drive loss. Double pulse tests are conducted for a SiC MOSFET with both conventional VSG and the proposed CSG. Testing results show that the switching loss of the proposed CSG is less than one third of the conventional VSG at full load condition.

High power inverters will be a key enabler for future aircraft based on hybrid electric or turbo-electric propulsion as envisioned by NASA and Boeing. Cooling a power electronics converter to low temperature, e.g. using cryogenic cooling, can significantly improve the efficiency and power density of a power conversion system. This paper presents the design of a MW cryogenically-cooled power inverter for electric aircraft applications. The power semiconductor and magnetic component characterization, inverter topology and power stage design, modulation and control, EMI noise reduction and filters design, and cooling system design are illustrated. A MW-level inverter prototype has been assembled and tested. The experimental results verify the functionality of the inverter.

Paralleling power electronics inverters is an effective way to increase dc-ac system power level. Accurately synchronized switching action and independent closed-loop regulator are necessary to prevent circulating current in paralleled inverters. There are many challenges for the controller design, when the number of paralleled inverters is large, and control period gets short for high switching frequency applications. This paper presents a single controller design based on DSP + FPGA that is suitable for paralleling multiple inverters. A simple synchronization scheme between DSP and FPGA based on universal parallel port (UPP) is proposed to eliminate the synchronization delay among inverters, and independent control of each converter can also be implemented. The controller is built for a system consisting of 4 paralleled three-level, three-phase high frequency ANPC inverters using space vector modulation, and it can be easily adopted to other topologies and modulations. Experimental results have demonstrated the effectiveness of this controller.

The adoption of SiC devices in high power applications enables higher switching speed, which requires lower circuit parasitic inductance to reduce the voltage overshoot. This paper presents the design of a busbar for a 500 kVA three-level active neutral point clamped (ANPC) converter. The layout of the busbar is discussed in detail based on the analysis of the multiple commutation loops, magnetic canceling effect, and DC-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. The results match with each other, and the inductances of small and large loop are 6.5 nH and 17.5 nH respectively, which is significantly lower than the busbars of NPC type converters in other references.

High-frequency soft-switched gallium-nitride (GaN) based critical conduction mode (CRM) totem-pole power factor correction (PFC) converter is one of the most potential candidates in data center power supplies. However, the high-speed cycle-by-cycle zero current detection (ZCD) brings challenges to zero-voltage-switching (ZVS) control. Current sensing delay (CSD) exists, and the ZCD circuit is sensitive to high di/dt switching noise. In this paper, mechanisms of the ZCD time error are elaborated, and impacts of the current sensing delay on converter switching frequency, inductor current, input current third harmonic distortion (THD), and power loss are analyzed. Qualification time is added within the controller for immunity to the swiching noise, and a CSD embedded converter model is proposed to compensate the ZCD time delay. Also, loss modeling of the CRM totem-pole PFC is conducted to aid in analysis of the proposed theory. A 1.5 kW single-phase CRM totem-pole PFC prototype is tested. Experimental results validiate the analysis, modeling, and the proposed compensation method for current sensing delay.

The four-leg topology has been applied to two-level inverters for common-mode (CM) noise elimination. To achieve zero common-mode voltage (CMV), the zero vector typically used in the two-level inverter is not allowed. As a result, the reference cannot be synthesized by nearest three vectors, which introduces a penalty in dc voltage utilization and current THD. This paper applies the fourth-leg to three-level neutral point clamped (NPC) inverter fed motor drives. Unlike the case in the two-level inverter, the reference can be synthesized by the nearest three vectors while zero CMV can be achieved at the same time in a three-level inverter with the fourth-leg. The topology and modulation are presented. The fourth-leg filter structures are investigated, and a fourth-leg filter structure which decouples the fourth-leg from the main circuit power level is proposed for high power applications. The experiment results on a three-level NPC inverter show that with the fourth-leg and presented modulation applied, the CM noise has been significantly reduced, and around 25 dB attenuation can be observed at the first noise peak in the electromagnetic interference (EMI) frequency range.

This paper details the inductor design and zero-voltage-switching (ZVS) control of a single-phase GaN-based critical-conduction-mode (CRM) totem-pole rectifier with power factor correction (PFC). A full-line-cycle ZVS strategy is derived, and an analytical converter model with ZVS margin is proposed. The boost inductor design is critical for the operation performance of the CRM totem-pole PFC. Based on analytical loss models, the inductor is designed and implemented using a toroidal powder core and litz wire to minimize converter loss and inductor size. Digital on-time control with real-time calculation and zero current detection (ZCD) is used to implement CRM. A 1.5 kW single-phase GaN-based CRM totem-pole PFC prototype is built and tested. With the on-time control, both the inductor current and the output voltage are well regulated. ZVS is realized for the whole line cycle, and the tested efficiency is 98.8% at full load.

This paper presents a comprehensive analytical analysis of the ac and dc side harmonics of the three-level active neutral point clamped (ANPC) inverter with space vector modulation (SVM) scheme. An analytical model to calculate the harmonics of a three-level converter with SVM is developed. The ac side output voltage harmonics and dc side current harmonics characteristics are calculated and analyzed. With the developed models, the impact of interleaving on both sides harmonics are studied which considers the modulation index, interleaving angle, and power factor. The analysis provides guideline for interleaving angle optimization to reduce the ac side power filter and dc side dc-link capacitor. The relationship between electromagnetic interference (EMI) filter corner frequency and switching frequency is also analytically derived which provides guideline for switching frequency and EMI filter design optimization. Two paralleled three-level ANPC inverters are constructed and experimental results are presented to verify the analytical analysis.

With the development of wide band-gap (WBG) technology, the switching speed of power semiconductor devices increases, which makes circuits more sensitive to parasitics. For three-level active neutral point clamped (3L-ANPC) converters, the over-voltage caused by additional non-active switch loop can be an issue. This paper analyzes the multiple commutation loops in 3L-ANPC converter and summarizes the impact factors of the device over-voltage. The nonlinearity of the output capacitance of the device can significantly influence the over-voltage. A simple control without introducing additional hardware circuit or complex software algorithm is proposed to attenuate the effect of the nonlinear output capacitance. Multi-pulse test is conducted for a 3L-ANPC converter built with silicon carbide (SiC) MOSFETs. With the proposed control, the testing results show that the peak drain-source voltage of both active and non-active switches is reduced by more than 20% compared to the conventional control.

This paper presents the coupled inductor design for interleaved three-level active neutral point clamped (ANPC) inverter considering electromagnetic interference (EMI) noise reduction. Compared to two-level case, the scenarios involved in the three-level space vector modulation (SVM) are more complicated when analyzing the volt-seconds of the coupled inductor for paralleled three-level inverter. At system level, the purpose of converter interleaving is to reduce EMI noise and ripple current in most applications, and coupled inductor design should consider the needs of EMI noise reduction and EMI filter design. These issues are discussed in this paper. The relationship between circulating current and EMI noise is illustrated. EMI filter corner frequency as a function of interleaving angle is analytically derived, and optimal interleaving angle for maximum common-mode (CM) filter and differential-mode (DM) filter corner frequencies is discussed. Coupled inductor design methodology for interleaved three-level inverters with SVM is then presented. Experiments on two interleaved ANPC inverters are conducted. The results verify the coupled inductor design. With the derived optimal interleaving angle, the CM and DM EMI noise are significantly reduced.

This paper presents harmonic analysis of common-mode reduction (CMR) modulation for three-level voltage source inverters. The analytical model to calculate the harmonics of CMR modulation with arbitrary PWM sequence is developed. The impact of alternative PWM sequences of CMR modulation on harmonics is investigated. New three-state and four-state PWM sequences of CMR are proposed which spread the energy centered in the carrier frequency in the conventional CMR, and thus reduce the voltage peaks in frequency domain. Experiments are conducted on a three-level neutral point clamped inverter. Experiment results verify the developed analytical model and harmonic analysis.

The modular multilevel converter (MMC) is regarded as a competitive choice for future dc grids at high and medium voltage levels. To study the dc grid stability, a few MMC dc impedance models have been proposed, but their accuracy is limited by the assumption of ideal submodule voltage or neglecting the circulating current control. In this paper, a more accurate MMC dc impedance model is developed considering both the submodule capacitor voltage and circulating current dynamics. Simulation and experiment results indicate that the developed model matches with the actual MMC better than state-of-art models and can predict the dc system stability correctly.

The performance of the gate drive power supply (GDPS) greatly impacts the safety and reliability of the gate drive for power semiconductor power devices. This paper focuses on the design of isolated gate driver power supply for 10 kV silicon-carbide (SiC) MOSFET for medium-voltage (MV) applications. Different insulation schemes are compared for the high-voltage insulated transformer in GDPS. Impact factors for transformer interwinding capacitance are analyzed, with which, a low inter-winding capacitance design approach is proposed for the high-voltage insulated transformer. Furthermore, an upward-voltage-reference based voltage regulation scheme is proposed for achieving good load regulation without output voltage feedback. Finally, a 20-kV-insulated GDPS is built and tested, and experimental results are presented to verify the effectiveness of the design approach.

The newly emerged 10 kV MOSFETs will be a game changer for the next generation medium-voltage (MV) power converters. While the unique feature of the fast switching speed benefits the development of high efficiency and high power-density MV converters, high dv/dt will be imposed on the power devices and passive components, which will result in accelerated insulation degradation and extreme EMI. This paper investigates the high dv/dt resulting from dead-time insertion in the modular multilevel converter (MMC). For reducing dv/dt, a multiple-step commutation scheme is proposed, in which, the submodules that transfer from bypass-state to insert-state are one-by-one commutated with those transferring from insert-state to bypass-state before the remaining unpaired submodules. Finally, the proposed multiple-step commutation scheme is verified on a single-phase MMC with 10-kV SiC MOSFET.

To overcome the limitations of digital simulation (numerical oscillation, limited computing capability of processors, etc.), a converter-based hardware test-bed was developed at CURENT for real-time power grid emulation. However, distribution systems especially microgrids cannot be emulated and tested on the existing hardware test-bed. This paper develops a microgrid test-bed based on the existing hardware test-bed to enable controller testing for microgrids with dynamic boundary. The design and realization of the microgrid hardware test-bed are introduced. The experimental results of the microgrid controller tests are also provided.

Medium voltage (MV) power converters using high voltage (HV) Silicon Carbide (SiC) power semiconductors result in great benefits in weight, size, efficiency and control bandwidth. However, challenges still exist on the components design considering HV insulation and noise immunity requirements in the MV SiC based power converter. A 5-level MMC based transformer-less grid-connected dc/ac converter is developed for 13.8 kV medium voltage grid using 10 kV SiC MOSFETs. The key components, including gate driver with high dv/dt immunity and fast reliable protection, isolated power supply with low parasitic capacitance, voltage/current sensors with high noise immunity, and passives following related insulation standard are provided. A 25 kV dc-link phase-leg is demonstrated, and the experimental results are presented.

This paper focuses on the design and testing of a half bridge submodule based on discrete 10 kV/20 A SiC MOSFETs for a modular multilevel converter (MMC). The rated dc bus voltage of the submodule is 6.5 kV, and the MOSFETs switch with dv/dt up to 100 V/ns. Design considerations and challenges for components in the submodule are presented, especially the gate driver to support the robust continuous operation and the submodule voltage sensor. Systematic testing procedures are developed to fully test the submodule up to 6.5 kV. High voltage insulation and high dv/dt are tackled throughout the design and testing. The designed submodule is validated in the continuous switching test at 6.5 kV with dv/dt up to 100 V/ns.

Virtual synchronous generator control provides a potential solution to connect power electronics interfaced sources to the power system. With its flexible control, the emulated inertia may be adaptively changed to enhance system small-signal stability. However, previously proposed methods may have adverse impact to system transient stability. This paper proposes to improve the methods by using wide-area measurements, namely center of inertia frequency. Experimental results are presented to both demonstrate the limitations of previous control schemes, and the effectiveness of the proposed one. The practical implementation of this method is discussed.

This paper focuses on the testing approach and validation of a 10 kV SiC MOSFET based Modular Multilevel Converter (MMC) phase-leg meant to interface to a 13.8 kV microgrid. Many of the difficulties associated with testing high-voltage SiC converters are shared regardless of topology, thus the testing setup and challenges associated with it are emphasized while the converter is only briefly summarized. Each component is individually verified, and the entire system is tested up to its rated dc link voltage and power, 25 kV and 35 kVA, respectively.

A microgrid with dynamic boundary can expand or shrink its boundary depending on available local distributed energy resources (DER). Compared to conventional microgrid with fixed boundary, it can lead to better DER utilization and improved reliability. Previous literature has only considered the operation of a microgrid with a single island that is energized by stable voltage sources. This paper introduces control function designs that can effectively synchronize islands inside a dynamic boundary microgrid, depending on the operation status of each voltage source inside the islands. An overview of the components and rationale within the control function designs is provided, and hardware-in-the-loop simulation results are analyzed to demonstrate the effectiveness of the control functions.

With increasing deployment of inverter-based sources in microgrids, inverter control methods are constantly being modified and improved. What remains constant, however, is the phase-locked loop (PLL). Regardless of the control technique adopted and the type of microgrid, a PLL is used to synchronize the output PWM signal of the inverter with the main grid or other inverters. But as penetration of inverter-based sources increases and grids become weaker, the impact of PLLs on controller behavior becomes more pronounced. The issues caused by these influences are described in this paper to make a case for finding a solution for inverter synchronization that better fits the needs of inverter-dominated microgrids than PLLs. Simulation results from a study of a low-voltage microgrid supported by parallel inverters are also presented to demonstrate some of these characteristics.

Many energy storage systems that use technologies such as batteries are composed of power electronics conditioning systems and battery management systems. These are often produced by multiple manufacturers and require hardware and software integration for full grid functionality. This paper proposes an agent-based framework to support the development of an energy storage system with standardized communications. This framework can be utilized with different power conversion systems with an appropriate hardware interface.

The next generation of utility-scale energy storage will be composed of modular systems and autoconfiguring software. This is key to incorporating battery management systems (BMS) and power electronic converters (PEC) from multiple manufacturers into a cohesive single system. In this paper, an agent-based architecture which supports the integration of numerous BMSs and PECs is proposed. This architecture supports optimization and control of the entire system and can be used in many different energy storage technologies.

Wide bandgap (WBG) semiconductor devices and cryogenic cooling are key enablers for highly-efficient ultra-dense power electronics converters, which are critical for future more electric aircraft applications. For the development and optimization of a cryogenically-cooled converter, an understanding of power semiconductor characteristics, especially for emerging WBG devices, is critical. This paper focuses on WBG device characterization at cryogenic temperatures. First, the testing setup for cryogenic temperature characterization is introduced. Then several WBG device candidates (e.g., 1200-V SiC MOSFETs and 650-V GaN HEMTs) are characterized from room to cryogenic temperatures. The test results are presented with trends summarized and analyzed, including on-state resistance, breakdown voltage, and switching performance.

Automated vehicles require sensors and computer processing that can perceive the surrounding environment and make real time decisions. These additional electrical loads expand the auxiliary load profile, therefore reducing the range of an automated electric vehicle compared to a standard electric vehicle. Furthermore, a fully automated vehicle must be fail-safe from sensor to vehicle control, thus demanding additional electrical loads due to redundancies in hardware throughout the vehicle. This paper presents a review of the sensors needed to make a vehicle automated, the power required for these additional auxiliary loads, and the necessary electrical architectures for increasing levels of robustness.

Switching transient overvoltage is inevitable in hard switching applications, and the faster switching speed of SiC MOSFETs suggests even worse overvoltage. This paper focuses on the turn-on overvoltage. To understand its nature, the switching transient is analyzed, and it shows the turn-on overvoltage is largely independent of load current condition. This phenomenon is verified by characterizing the turn-on overvoltage of a SiC MOFET and a SiC Schottky diode. Finally, a SPICE-based model is also built to understand the switching transient more accurately, and the modeling method can accurately predict the turn-on overvoltage and help select device voltage rating.

Dead-time, device output capacitance, and other non-ideal characteristics cause voltage error for the midpoint PWM voltage of the semiconductor phase-leg employed in a voltage-source inverter (VSI). Voltage-second balancing is a well-known concept to mitigate this distortion and improve converter power quality. This paper proposes a unique voltage-second balancing scheme for a SiC based voltage source inverter using online condition monitoring of turn-off delay time and drain-source voltage rise/fall time. This data is sent to the micro-controller to be used in an algorithm to actively adjust the duty cycle of the input PWM gate signals to match the voltage-second of the non-ideal output voltage with an ideal output voltage-second. The monitoring system also allows for this implementation to eliminate the need for precise current sensing and allows for the implementation to be load independent. Dynamic current sensing is still a developing technology, and each load has a unique effect on the output voltage distortion. Test results for a 1 kW half-bridge inverter implementing this monitoring system and voltage-second balancing scheme show a 70% enhancement on the error against the ideal fundamental current value of the output current and a 2% THD improvement on the output current low frequency harmonics.

This work examines the application of GaN within Class D audio by providing a side-by-side comparison of enhancement-mode GaN devices with currently available silicon MOSFETs with 60 V drain-to-source voltage ratings. GaN in Class D audio will allow for lower heat radiation, smaller circuit footprints, and longer battery life as compared to Si MOSFETs with a negligible trade-off for quality of sound.

Data centers consume an ever-increasing amount of electricity because of the rapid growth of cloud computing and digital information storage. A high voltage point of load (HV POL) converter is proposed to convert the 400-VDC distribution voltage to 1-VDC within a single stage to increase the power conversion efficiency. A six-phase input series output parallel (ISOP) connected structure is implemented for the HV POL. The symmetrical controlled half bridge current doubler is selected as the converter topology in the ISOP structure. The full load efficiency is improved by 4% points compared with state of the art products. A voltage compensator has been designed in order to meet the strict dynamic voltage regulation requirement. A laboratory prototype has been built, and experimental results have been provided to verify the proposed HV POL with a single power conversion stage can meet the dynamic voltage regulation requirement for an on-board power supply with higher efficiency compared to the conventional architecture.

Although SiC MOSFETs show superior switching performance compared to Si IGBTs, it is unknown whether SiC MOSFETs have the same advantage over Si super junction (SJ) MOSFETs such as CoolMOS. This paper analyzes the switching performance in different switching cell configurations and summarizes the impact factors that influence switching loss. A double pulse test is conducted for a SiC MOSFET and a CoolMOS with the same voltage and current rating. In the FET/diode cell structure, a SiC Schottky diode is used as the upper device to eliminate the reverse recovery, and the testing results show that the SiC MOSFET has 2.4 times higher switching loss than the Si CoolMOS. This can be explained by the smaller transconductance and the higher Miller voltage of the SiC MOSFET. On the other hand, the Si CooMOS has 10 times higher switching loss than the SiC MOSFET in the FET/FET cell structure because of the significant turn-on loss caused by the poor reverse recovery of its body diode.

Due to the low availability, high cost, and limited performance of high voltage power devices in high voltage high power applications, series-connection of low voltage switches is commonly considered. Practically, because of the dynamic voltage unbalance and the resultant reliability issue, switches in series-connection are not popular, especially for fast switching field-effect transistors such as silicon (Si) super junction MOSFETs, silicon carbide (SiC) JFETs, SiC MOSFETs, and gallium nitride (GaN) HEMTs, since their switching performance is highly sensitive to gate control, circuit parasitics, and device parameters. In the end, slight mismatch can introduce severe unbalanced voltage. This paper proposes an active voltage balancing scheme, including 1) tunable gate signal timing unit between series-connected switches with <; 1 ns precision resolution by utilizing a high resolution pulse-width modulator (HRPWM) which has existed in micro-controllers; and 2) online voltage unbalance monitor unit integrated with the gate drive as the feedback. Based on the latest generation 600-V Si CoolMOS, experimental results show that the dynamic voltage can be automatically well balanced in a wide range of operating conditions, and more importantly, the proposed scheme has no penalty for high-speed switching.

Understanding the CM inductor core saturation mechanism and reducing core flux density is critical for CM inductor design optimization. Instead of a time domain method, this paper introduces frequency domain spectrum concept for CM inductor core saturation analysis and design optimization, which will provide designers a better understanding of CM inductor design. First, both core permeability and converter modulation index's opposite influence on DM flux density and CM flux density are identified. Then, CM flux density is further investigated based on the spectrum concept. Three components in the CM inductor which may cause large CM flux density and core saturation are summarized: (1) switching frequency related components, (2) impedance resonance frequency related components, and (3) modulation frequency related components. Each component is investigated for CM flux density reduction and filter design optimization. A connecting AC and DC side midpoint with notch filter structure is proposed to reduce modulation frequency related components. Experiment results are presented to verify the proposed concept and method.

Superconducting technologies such as motors together with the supporting cryogenic power electronic system are growing in importance in aircraft applications. It is critical to understand the influence of low temperature on filters of the power converter system in these applications. Also, it is worthwhile to investigate whether the converter system can achieve higher efficiency and high power density by utilizing the provided low temperature cooling environment. This paper conducted a comprehensive magnetic core characterization at low temperature to understand the core properties and support filter design at low temperature. The ferrite and nanocrystalline material are characterized from room temperature to cryogenic temperature in a wide range of operating frequencies. The results show that the permeability of ferrite material decreases by a factor of 7~8 and the core loss increases more than 10 times when operating at very low temperature. The permeability of nanocrystalline material decreases to 60% and the core loss increases 1.5~2.5 times when operating at very low temperature. The saturation flux density of both materials has slight increase at low temperature. Based on tested data, a case study of inductor design considering the low temperature cooling environment is presented to illustrate the influence of low temperature on inductor design.

To operate a converter at cryogenic temperatures, understanding the characteristics of power semiconductor devices is critical. This paper presents the characterization of state-of-the-art 1.2 kV SiC MOSFETs from leading manufacturers at cryogenic temperatures. The testing setup consisting of a cryogenic chamber, and a liquid nitrogen Dewar is introduced. With a curve tracer and double pulse test, comprehensive characterization of the SiC MOSFETs including both static and switching performance is conducted and evaluated. Test results indicate the on-resistance increases while the breakdown voltage remains relatively constant at cryogenic temperatures. Other characteristics like threshold voltage and switching loss vary significantly at cryogenic temperatures among devices from different manufacturers.

Zero sequence circulating current (ZSCC) exists when paralleled inverters have common dc and ac sides without isolation. Most of the prior work on the ZSCC analysis and suppression depended on paralleled two-level inverters. The scenarios involved in the three-level converters are more complicated. This paper investigates the ZSCC in paralleled three-level active neutral point clamped (ANPC) inverters. The mechanisms causing potential ZSCC jump in three-level paralleled ANPC inverters are analyzed. The ZSCC patterns of different interleaved modulation schemes for three-level converters are illustrated. Then, the active vector dividing concept is extended to three-level converters, and a modulation scheme is proposed to reduce the high frequency ZSCC in three-level converters. Experiments have been conducted on two paralleled three-level inverters. The current jump in ZSCC is observed and mitigated. The ZSCC with proposed modulation scheme is reduced to less than half of the ZSCC with conventional continuous space vector modulation (CSVM) scheme.

Unlike conventional passive or active filters, an impedance balancing circuit reduces the common-mode (CM) electromagnetic interference (EMI) noise by establishing an impedance balancing bridge. The EMI noise can be significantly reduced when the impedance bridge is designed to be well balanced. This paper investigates impedance balancing circuits in Dc-fed motor drive systems where both DC input and AC output need to meet EMI standards and thus EMI filters are needed for both sides. An impedance balancing circuit is proposed to reduce both DC and AC side CM noise. Two auxiliary branches are added to the conventional passive filters to establish an impedance bridge and reduce CM noise. The design criteria are presented, and the impact of the proposed impedance balancing circuit on both sides CM noise are investigated. It shows that the proposed impedance balancing circuit can reduce DC side and AC side CM noise based on different mechanisms. The CM noise reduction performance of the proposed method does not depend on the motor and cable models. Experiment results are presented to demonstrate the feasibility and effectiveness of the proposed method.

One of the popular converter topologies applied in high power dc-ac applications is the three-level active neutral point clamped (ANPC). Owing to relatively low switching frequency and slow switching speed of these topologies in high power applications, the commutation loop analysis in these topologies has not been fully conducted, and the over-voltage issue of non-active switches has not been thoroughly analyzed. This paper reveals an over-voltage issue on non-active switches in three level inverters due to multi-commutation loop. The detailed mode analysis during the commutation and related over-voltage issue are given. Finally, Si-based ANPC with 140 kHz switching frequency and SiC-based ANPC converters with 280 kHz switching frequency and high switching speed are tested respectively to compare and verify the over-voltage issue for non-active switches.

In order to evaluate the feasibility of newly developed GaN devices in a cryogenic-cooled converter, this paper characterizes a 650 V enhancement-mode Gallium-Nitride heterojunction field-effect transistor (GaN HFET) at cryogenic temperatures. The characterization includes two parts: static and dynamic characterization. The results show that this GaN HEMT is an excellent device candidate to be applied in cryogenic-cooled applications. For example, transconductance at cryogenic temperature is 2.5 times of one at room temperature, and accordingly, peak di/dt during turn-on transients at cryogenic temperature is around 2 times of that at room temperature. Moreover, the on-resistance of the channel at cryogenic temperature is only one-fifth of that at room temperature.

A power converter based transmission line emulator has been developed for the hardware test-bed (HTB) platform, which emulates power systems by mimicking the system components with universal three-phase voltage source converters. In power grids, transmission line series compensation devices are utilized to enhance the power delivery capability and controllability by regulating the equivalent impedance of a transmission line. This paper proposes a method of mimicking variable capacitors and inductors to combine the series compensation device emulation into the transmission line emulator so that various power system scenarios can be studied. Simulation and experiment results verify the effectiveness of the transmission line emulation with integrated series compensation devices.

To better utilize the existing electric power grid distribution network automation of smart switches, a microgrid can expand or shrink its electrical boundary according to available renewable generation. Previous literature only focused on the design of a microgrid with a dynamic boundary, but without considering real-time operation. This paper proposes a microgrid controller that enables operation of microgrid with dynamic boundary and can be integrated into the existing distribution automation system. The architecture of the control system is introduced, and the essential functions such as online topology assessment and synchronization are presented. Simulation results are given to demonstrate the feasibility of the proposed controller.

The short circuit performance of a 3rd generation 10 kV/20 A SiC MOSFET with short channel is characterized in this paper. The platform consisting of a phase-leg configuration, which can test both hard switching fault (HSF) and fault under load (FUL) types of fault, is introduced in detail. A Si IGBT based solid state circuit breaker is developed for short circuit test. The short circuit protection having a response time of 1.5 μs is validated by the test platform. The short circuit characteristics for both the HSF and FUL types at 6 kV DC-link are presented and analyzed.

Modular multilevel converters (MMCs) have been widely adopted for high voltage direct current (HVDC) applications and have been targeted for use in future dc grids as well. However, most of the MMC research is still limited to digital simulations or relied on hardware demonstrations with a specific setup and limited number of submodules (SMs). In this paper, a MMC test-bed with 10 SMs in each arm is developed that has flexible reconfiguration of the MMC topologies, switching frequencies, and passive element parameters. The MMC test-bed hardware construction, control scheme, and communication architecture are described, and typical MMC scenarios are conducted to verify its multiple functions.

In a converter based on 10 kV SiC MOSFETs, major sources of parasitic capacitance are the anti-parallel junction barrier schottky (JBS) diode, heat sink, and load inductor. A half bridge phase leg test setup is built to investigate these parasitic capacitors' impact on the switching performance at 6.25 kV. Generally these parasitic capacitors slows down both turn-on and turn-off transient and can cause significant increase in switching energy loss. The impact of the parasitic capacitor in the load inductor is analyzed, which has either very short wire or long wire in series. Switching performance of the phase leg with two different thermal designs are compared to investigate the impact of the parasitic capacitor due to the heat sink. The large parasitic capacitor due to the large drain plate of discrete 10 kV SiC MOSFET for heat dissipation can result in 44.5% increase in switching energy loss at low load current.

Practical distribution system contains many nodes and short branches. As a result, a more efficient and stable distribution state estimation (DSE) algorithm is needed to properly handle the inverse operation of its large-scale ill-conditioned information matrix. This paper proposed a two-stage DSE algorithm to transform the inverse operation into addition and multiplication operations in a recursive manner. It includes pseudo measurement preprocessing in the offline stage where an approximate linear estimator is adopted to relieve most of computation burdens, and real-time correction in the online stage where a nonlinear estimator is used to update the estimation. Numerical results of the method applied to both IEEE standard test systems and an actual distribution system show the accuracy and effectiveness of the proposed algorithm.

The frequency decoupling effect of the voltage source converter (VSC)-based high voltage dc (HVDC) transmission makes frequency support unavailable between two ac subsystems interconnected by the HVDC link. Recently, several algorithms have been proposed and demonstrated to improve the ac system stability by implementing inertia emulation (IE) functions in the HVDC VSC stations. However, the capability of the VSC-HVDC to achieve the IE control is not clear. According to the previous research, the IE control strategy has been studied without concerning the impact of the practical control process, which will introduce some time delay into the IE realization. In this paper, a detailed multi-terminal HVDC VSC control module, including the phase-locked loop (PLL) and low pass filter (LPF), is considered in order to analyze the multi-terminal HVDC network impact on the IE performance. The analysis indicates that the frequency performance of the ac network with IE integrated HVDC transmission can be nearly as good as that directly connected with the ac subsystem which involves a high penetration of conventional generation units, except for the short time delay introduced by the VSC control modules. The effectiveness of IE performance will be compromised if the response delay is significant. The simulation results have verified the analysis.

Battery energy storage systems (BESSs) are commonly used for frequency support services in power systems because they have fast response times and can frequently inject and absorb active power. Lithium-ion (Li-ion) BESSs dominate the grid energy storage market now, but Vanadium redox flow (VRB) BESSs are predicted to contend in future markets for large-scale storage systems. Previously, a Li-ion BESS emulator has been developed for a grid emulation system known as the Hardware Testbed (HTB), which consists of converters controlled to emulate different power system components. In this paper, we develop a VRB BESS emulator with a VRB-specific internal battery model and a power electronics interface similar to that of the Li-ion BESS emulator. Then, we compare the effectiveness of the VRB and Li-ion technologies for primary frequency regulation and inertia emulation applications. It is concluded that these two technologies are virtually indistinguishable from the power system's perspective when conducting these services over a short period of time.

The impact of the body diode and the anti-parallel junction barrier Schottky (JBS) diode on the switching performance of the 3rd generation 10 kV SiC MOSFET from Wolfspeed/Cree is investigated in detail at various junction temperatures. The switching performance with and without the anti-parallel JBS diode is tested by specific layout design of the 10 kV MOSFET module. The body diode of the 10 kV SiC MOSFET has excellent reverse recovery performance from 25°C to 125 °C, indicating it is a suitable candidate for freewheeling diode. The application of anti-parallel JBS diode will slow down the turn-off transient and result in lower turn-off dv/dt and higher turn-off energy loss, while its impact on the turn-on transient is not significant.

This paper introduces a dead-time optimization technique for a 2-level voltage source converter (VSC) using turn-off transition monitoring. Dead-time in a VSC impacts power quality, reliability, and efficiency. Silicon carbide (SiC) based VSCs are more sensitive to dead-time from increased reverse conduction losses and turn-off time variability with operating conditions and load characteristics. An online condition monitoring system for SiC devices has been developed using gate drive assist circuits and a micro-controller. It can be leveraged to monitor turn-off time and indicate the optimal dead-time in each switching cycle of any converter operation. It can also be used to specify load current polarity, which is needed for dead-time optimization in an inverter. This is an important distinction from other inverter dead-time elimination/optimization schemes as current around the zero current crossing is hard to accurately detect. A 1kW half-bridge inverter was assembled to test the turn-off time monitoring and dead-time optimization scheme. Results show 91% reduction in reverse conduction power losses in the SiC devices compared to a set dead-time of 500ns switching at 50 kHz.

While fast switching brings many benefits, it also presents unwanted ringing during switching transient. In this paper, an increasing magnitude ringing phenomenon is observed during the MOSFET turn-off transient. The unusual phenomenon is replicated in simulation and it is found the MOSFET channel is turned on again after it is turned off. The major cause to this unexpected turn on is found to be common source inductance and a moderate 3 nH one in simulation replicates the severe self-turn-on ringing observed in experiment. This paper reveals the detrimental effect of common source inductance in fast switching. Therefore, Kelvin source connection in circuit and package design is strongly recommended.

Cooling a converter to low temperatures, e.g. using cryogenic cooling, can significantly improve the efficiency and density of a power conversion system. For the development and optimization of a cryogenically-cooled converter, an understanding of power semiconductor characteristics is critical. This paper focuses on the characterization of high-voltage, high-speed switching, power semiconductors at cryogenic temperature. First, the testing setup for cryogenic temperature characterization is introduced. Three testing setups are established for cryogenic switch characterization, including: 1) on-state resistance and forward voltage drop of the body diode, 2) leakage current and breakdown voltage, and 3) switching characteristics. For each testing set up, the corresponding testing configurations, hardware setups, and practical considerations are summarized. Additionally, the test results at cryogenic temperature are illustrated and analyzed for 650-V Si CoolMOS. It is then demonstrated that when the cryogenic temperature test results are compared to that of room temperature, the device performance varies significantly; for example: on-state resistance reduces by 63%, breakdown voltage drops by 31%, switching time decreases and switching energy loss decreases by 26%. Furthermore, the peak dv/dt during transient switching at cryogenic temperature exceeds 100 V/ns which is comparable to the emerging wide bandgap Gallium Nitride devices.

Silicon Carbine (SiC) based power semiconductor devices have increased voltage blocking capability, in the meantime, satisfactory switching performance as compared to conventional Silicon (Si) devices. This paper focuses on the latest generation 10 kV / 20 A SiC MOSFETs and investigates their protection schemes and temperature-dependent switching characteristics. A high voltage double pulse test platform is constructed including solid state circuit breaker, gate drive and hot plate under device under test (DPT) for temperature-dependent characterization. A behavioral model is established to analytically investigate switching performance of 10 kV SiC MOSFETs, and the temperature-dependent factors are studied in detail. The experimental results under various load currents and gate resistances from 25 C to 125 C at 7 kV dc-link voltage are presented.

Preparing power systems to better accommodate renewable energy sources has become increasingly more important as penetration levels rise, and energy storage systems are excellent for suppressing the fluctuations of renewable and for providing other ancillary services to the grid. The Hardware Testbed (HTB) is a novel converter-based grid emulator created for studying the needs associated with high renewable penetration, but the system currently lacks battery storage capability. This paper proposes a configurable Lead Acid and Lithium Ion battery storage emulator equipped with a two-stage power electronics interface, which is capable of independent active and reactive power control as well as inertia emulation. Each part of the emulator is described in detail, in terms of both the models used and the control algorithms governing them. The emulator's behavior is simulated, tested, and confirmed to function correctly with the HTB and will be used to study scenarios in which battery storage can be used to support renewables and other dynamic power system needs.

A hardware test-bed (HTB) has been developed to realize power system emulation by mimicking the system components with universal three-phase voltage source converters (VSCs). The VSC-based transmission line emulator has also been successfully developed to flexibly represent interconnected ac lines under normal operating conditions. As the most serious short-circuit fault condition, the three-phase short-circuit fault emulation is essential for power system studies. This paper proposes a model to realize the three-phase short-circuit fault emulation within the emulated transmission line. At the same time, a combination method is proposed to eliminate the undesired transients caused by the current reference step changes while switching between the fault state and normal state.

Hybrid ac/dc transmission can increase the power transfer capability of long ac transmission lines. High voltage dc (HVDC) converters are needed, and the line-commutated converter (LCC) is used considering the dc fault current controllability. However, zero-sequence current can be generated due to the coupled transmission lines, and it will flow into the HVDC converters as a fundamental frequency current component on dc side (i60). The LCC will convert i60 to dc current components on the ac side, which may cause potential converter transformer saturation. This paper analyzes the influence of coupled transmission lines on i60 and the converter transformer saturation and proposes two possible solutions to avoid converter transformer saturation. The simulation results verify the effectiveness of the proposed methods.

Junction temperature is a critical indicator for health condition monitoring of power devices. Concerning the reliability of emerging silicon carbide (SiC) power semiconductors due to immaturity of new material and packaging, junction temperature measurement becomes more significant and challenging, since SiC devices have low on-state resistance, fast switching speed, and high susceptibility to noise and parasitics in circuit implementations. This paper aims at developing a practical and cost-effective approach for online junction temperature monitoring of SiC devices using turn-off delay time as the thermo-sensitive electrical parameter (TSEP). The sensitivity is analyzed for fast switching SiC devices. A gate impedance regulation assist circuit is designed to improve the sensitivity by a factor of 60 and approach hundreds of ps/°C in the case study with little penalty of the power conversion performance. Also, an online monitoring system based on three gate assist circuits is developed to monitor the turn-off delay time in real time with the resolution within hundreds of ps. In the end, the micro-controller is capable of “reading” junction temperature during the converter operation with less than 0.5 °C measurement error. Two testing platforms for calibration and online junction temperature monitoring are constructed, and experimental results demonstrate the feasibility and accuracy of the proposed approach. Furthermore, the proposed gate assist circuits for sensitivity improvement and high resolution turn-off delay time measurement are transistor based and suitable for chip level integration.

High speed switching of WBG devices causes their switching behavior to be highly susceptible to the parasitics in the circuit, including inductive loads. An inductive load consisting of a motor and power cable significantly worsens the switching speed and losses of SiC MOSFETs in a PWM inverter. This paper focuses on the motor plus power cable based inductive load, and aims at mitigating its negative influence during the switching transient. An auxiliary filter is designed and inserted between the converter and inductive load so that the parasitics of the load will not be “seen” from the converter side during the switching transient. Test results with Cree 1200-V/20-A SiC MOSFETs show that the proposed auxiliary inductor enables the switching performance with a practical inductive load (e.g., motor plus cable based inductive load) to exhibit behavior close to that when the optimally-designed double pulse test load inductor is employed.

In this paper, a single stage system which converts 400 V to 1 V within one stage and performs as the high voltage point of load (HV POL) converter for data centers is proposed. A load dependent soft switching method has been proposed for half bridge current doubler with simple auxiliary circuit. The operation principles of the soft switching converter have been analyzed in detail. A lossless RCD current sensing method is used to sense the output current value to reduce the auxiliary circuit loss and turn off loss of secondary side devices as load reduces to achieve higher efficiency. Experimental efficiency has been tested to prove the proposed method can increase the converter's efficiency in both heavy and light load condition. A prototype of the half bridge current doubler circuit has been built to verify the theory.

Many intelligent gate drivers being designed for new state-of-the-art WBG devices typically only focus on protection and driving capabilities of the devices. This paper introduces an intelligent gate driver that incorporates online condition monitoring of the WBG devices. For this specific case study, three timing conditions (turn-off delay time, turn-off time, and voltage commutation time) of a silicon carbide (SiC) device are online monitored. This online monitoring system is achieved through gate driver assist circuits and a micro-controller. These conditions are then utilized to develop converter-level benefits for the converter application the SiC devices are placed in. Junction temperature monitoring is realized through turn-off delay time monitoring. Dead-time optimization is achieved with turn-off time monitoring. Dead-time compensation is obtained with turn-off time and voltage commutation time monitoring. The case study converter assembled for testing purposes is a half-bridge inverter using two SiC devices in a phase-leg configuration. All timing conditions are correctly monitored within reasonable difference of the actual condition time. A calibration curve was created to give a direct relationship between turn-off delay time and junction temperature. The half-bridge inverter can operate at 600 Vdc input and successfully obtain a junction temperature measurement through monitored td_off and the calibration curve. Furthermore, the proposed online condition monitoring system is transistor based and suitable for the chip level integration, enabling this practical approach to be cost-effective for end users.