The accurate control of negative sequence (NS) current distribution among multiple grid-forming (GFM) sources can lower the requirement on NS current capability of the sources. Existing control approaches mainly focus on microgrids (MGs) with fixed points of common couplings and on only the NS current distribution among inverter-based resources (IBRs). As MG configuration has been rapidly evolving to be more complicated, it is critical to take into consideration the impact of MG topologies on the NS current sharing. Moreover, synchronous generators (SGs) are still commonly applied as sources in MGs. The NS current distribution among IBRs and SGs also needs to be considered. In this paper, a novel NS impedance design and regulation approach is proposed to achieve accurate and flexible NS current sharing among different GFM sources (IBRs and SGs). The approach accounts for MG topology impacts by including MG's NS admittance matrix in the impedance design. The effectiveness of the proposed approach is evaluated through simulations and compared to existing solutions in a MG with four different source locations. Results show improved flexibility and accuracy in NS current sharing when MG topology impacts are considered. The proposed approach is also validated through experimental testing on a converter-based hardware testbed.

This article presents a desat protection scheme with the ultrafast response for high-voltage (>3.3 kV) SiC MOSFETs. Its working principle is the same as the conventional desat protection designed for high-voltage SiC MOSFETs, yet its blanking time is implemented by fully considering the influence of high negative dvds/dt during the fast turn-on transient. With the same circuitry as the conventional desat protection, the proposed protection scheme can significantly shorten the response time of the desat protection when it is used to protect high-voltage SiC MOSFETs. In addition, the proposed protection scheme with ultrafast response features strong noise immunity, low-cost, and simple implementation. By taking advantage of the high dv/dt during the normal turn-on transients, the proposed protection scheme can be even faster when the MOSFET has a faster switching speed. Design details and the response speed analysis under various short circuit faults are presented in detail. A half bridge phase leg based on discrete 10 kV/20 A SiC MOSFETs is built to demonstrate the proposed protection scheme. Experimental results at 6.5 kV validate the ultrafast response (115 ns response time under a hard switching fault, 155 ns response time under a fault under load), and strong noise immunity of the proposed desat protection scheme.

Due to multiple operation modes and corresponding mode transitions of microgrids (MGs), the MG grounding design is challenging. An MG may lose its grounding provided by the main distribution grid when it transitions to the islanded operation, resulting in potential hazards to both equipment and personnel. Existing transformer-based grounding schemes are bulky and have low control capability, which leads to poor transition performances and may affect the operation and protection of the whole distribution grid in the grid-connected mode. Power inverters have been applied as interfaces of distributed energy resources (DERs), which can potentially serve as groundings for future MGs. In this article, a novel DER inverter-based MG grounding scheme is proposed to realize flexible grounding in MGs. The detailed grounding structure and control methods are discussed. The proposed grounding scheme is verified on a realistic MG model through simulation. The proposed control strategies are demonstrated on a converter-based hardware testbed.

A microgrid (MG) may lose its grounding provided by the main distribution grid in islanded mode, which could cause equipment insulation damage, hazards to personnel, and protection malfunction. Existing MG grounding schemes include the grounding transformer-based scheme and distributed energy resource (DER) transformer-based scheme. However, the grounding transformer-based scheme will increase MG’s cost, and the DER transformer approach will affect the main grid in the grid-connected mode. Moreover, future MGs may have multiple source locations. In each source location, the source and critical load can potentially operate as a sub-MG, requiring a grounding when it stands alone. In this scenario, the drawbacks of existing grounding schemes will be further magnified. In this paper, a novel controllable DER transformer-based grounding scheme is proposed, where a controllable switch is added to the neutral wire of the transformer. The proposed scheme can disable grounding capability in the grid-connected mode and enable it in the islanded mode by changing the transformer connection. The proposed approach can avoid impacts on the main distribution grid and eliminate the need for additional transformers. The design methodology of the proposed grounding scheme is provided. Simulation verification is conducted on a realistic MG model and experimental verification is conducted.

Power electronics converters can be applied as emulators to mimic different grid components used for system behavior analyses and control validation. Synchronous generators (SGs) are the major sources of electric grids. Converter-based SG emulators have been developed for system stability analysis, fault analysis, and frequency support. However, existing SG emulators have not considered the impacts of load unbalance, which is a common phenomenon in distribution grids and will lead to system-level issues. In this article, a SG emulator considering an actual SG's negative sequence (NS) performance is developed for system analyses under unbalanced load conditions. With different simplifications, a SG can have different orders of electrical models. By deriving the NS performances of different SG electrical models, an appropriate SG electrical model in unbalanced load conditions is selected. Then a novel control diagram is proposed to ensure that the NS performances of the selected model can be fully realized. The derived NS models and the proposed control diagram are verified through simulation first and then validated with a converter-based hardware testbed.

Load unbalance in electric distribution systems is unavoidable. Unbalanced load currents will lead to negative sequence (NS) voltages that may damage electric equipment. Unbalanced power flow analysis is a common tool to detect and mitigate NS voltage issues and requires accurate models of grid components. While traditional source models are available, grid-forming (GFM) inverter models are not well developed. GFM inverters implement various control strategies, which affect their power flow models. In this paper, a novel GFM inverter model considering control effects is proposed. We show that for some control methods, unbalanced system loading will lead to unbalanced terminal voltages of the GFM inverters, which are modeled through an equivalent negative sequence impedance. The proposed models are initially validated using a simple test circuit. Then, they are applied in the power flow analysis on the IEEE 13-bus and 34-bus systems to demonstrate the accuracy improvement over the state-of-the-art. Using time-domain simulations as benchmarks, we show that the proposed models reduce the calculation error of negative sequence voltages by at least 25% in unbalanced distribution systems.

The amount of electricity generation from renewable energy resources (RES) has been increasing significantly all over the globe. However, traditional power grid management is challenged when a large amount of intermittent and unpredictable RES-based generation units are integrated into the power network. This can lead to more severe grid frequency fluctuation events. In this paper, a variable speed drive (VSD) based motor load is utilized as a frequency responsive load to support grid frequency stability. A primary frequency control scheme is proposed and applied to the VSD-based motor load, which incorporates the sophisticated rotating speed feedback controller. Additionally, the proposed frequency responsive VSD-based load is modeled and simplified. As a result, a droop-like response can be achieved with multiple VSD load units. The effectiveness of the proposed model and control scheme is evaluated by experimental studies performed in a multi-converter-based hardware testbed (HTB).

This paper comprehensively analyzes desaturation (desat) protection for high voltage (>3.3 kV) silicon carbide (SiC) MOSFETs and especially how to build in noise immunity under high dv/dt. This study establishes a solid foundation for understanding the trade-offs between noise immunity and response speed of desat protection. Two implementations of the desat protection for high voltage SiC MOSFETs are examined, including desat protection based on discrete components and desat protection realized with a gate driver integrated circuit (IC). Both positive dv/dt and negative dv/dt are investigated. Analysis results show that the high dv/dt with long duration caused by high voltage SiC MOSFETs’ switching results in strong noise interference in the desat protection circuitry. The impact of numerous influencing factors is investigated analytically, such as parasitic capacitances, parasitic inductance, damping resistance, and clamping impedance. Under high positive dv/dt, extremely small parasitic capacitances (<0.01 pF) between the drain terminal and protection circuitry could still compromise noise immunity of the desat protection circuitry that has a high-impedance voltage divider. Comprehensive design guidelines are summarized to boost the noise immunity, including circuit design, component selection, and PCB layout. The noise immunity margin under the positive dv/dt is also derived quantitatively to guide the noise immunity improvement. The noise immunity analysis results and noise immunity improvement methods are validated with simulation and experimental results obtained from a phase leg based on 10 kV/20 A SiC MOSFETs.

To accelerate the dynamic response in a dual active bridge converter, feed-forward control can be applied in parallel to the conventional PI controller for closed-loop control. The transformer current thus changes significantly due to the phase shift change. A current spike can appear during load transients, particularly when using multiple phase shift modulation. Effort has been made in the previous literature to implement active compensation between two different steady-state operations to eliminate the transformer current spike; however, this results in a complicated control structure. This letter thus proposes a novel modulation method unifying the transformer current for dual phase shift and triple phase shift modulation to mitigate the transformer current spike when switching among various phase shift controls during load transients. By applying the proposed pulsewidth modulation strategy, the instantaneous value of the transformer current stays the same at the beginning of the switching period even with different steady-state modulation techniques. Also, full-operation-range zero-voltage switching can be realized for the primary side or the secondary side switches by combining with the proposed modulation strategy. An experimental prototype demonstration validates the proposed modulation strategy.

Distributed energy resources (DERs) and microgrids have seen tremendous growth and research activities in recent years. Flexible DERs and asynchronous microgrids (ASMG) can have many system-level benefits over fixed DERs and conventional microgrids. The key enabler for flexible DERs and ASMG is a power converter based power conditioning system (PCS) as the interface between DERs/microgrids and the medium voltage (MV) distribution grid. High voltage (HV, >3.3 kV) silicon carbide (SiC) based MV converter is now a promising solution for the PCS. This article presents development and testing of a 10 kV SiC MOSFET based MV PCS for 13.8 kV ASMG. MV PCS converter design addressing high dv/dt issue generated by fast switching of the 10 kV SiC MOSFET is presented. The developed PCS is successfully tested at 25 kV dc 13.8 kV ac voltages and 100 kVA power. Grid support functions are also demonstrated with the developed PCS prototype and hardware tests beds, validating HV SiC converter benefits for ASMG.

The dynamic boundary concept enables more flexible and efficient operation of microgrids with distributed energy resources (DER) that are intermittent in nature. As the integration of renewables continues to accelerate, an adaptive power management module that enables dynamic boundary operations in microgrids with an increasing number of source locations is essential for the fast and low-cost deployment of microgrid controllers. The power management module introduced in this paper is capable of handling the increased complexity in topological variations and transitions stemming from dynamic boundaries and multiple source locations. This includes real-time operation of multiple islands with dynamic boundaries, initiation of topological transitions (merging and separation of islands), and automatic source coordination for power sharing and frequency regulation. All functions in the power management module are designed to be automatically adaptable to arbitrary microgrids with non-meshed topologies so that the deployment of the controller at new microgrid sites can be expedited with a reduced cost. The module has been implemented on NI’s CompactRIO system as an essential part of an MG controller and tested on a converter-based hardware testbed (HTB). Testing results validated the effectiveness of the algorithms under various operating conditions.

This paper introduces two electrical architectures for electric/ hybrid-electric aircraft propulsion systems to address the issues of the radial baseline architecture, where a single bus feeds the four propulsion motors. A fault on this bus results in complete isolation of the bus to which propulsion motors are connected. By using the proposed architectures, the fault can be isolated without having to disconnect all the propulsion motors. This would increase the reliability, redundancy, and robustness of the electrical system, and/or avoid oversizing the components present in the architecture. In this paper, the protection strategy and action of circuit breakers are discussed for different fault conditions. The enhanced fault-tolerant operation of the proposed architectures over the existing radial baseline architecture for the electrified aircraft propulsion (EAP) system is validated for both open circuit and short circuit faults at different locations in the system, using controller hardware in the loop results obtained using typhoon HIL testbed. Furthermore, the feasibility analysis of interconnecting the individual propulsion channels to reduce the over-sizing of components is also discussed.

Existing current sensors suffer from insufficient measurement bandwidth or large insertion area to faithfully capture the continuous switching transient current of wide-bandgap devices. The combinational Rogowski coil concept is proposed here, where the self-integrating region of a shielded Rogowski coil is combined with its differentiating region to extend the overall measurement bandwidth. The coil design methodology, including the parasitic element model and practical design boundaries, is discussed. The concept is implemented with printed circuit boards and prototypes demonstrated up to 300 MHz bandwidth. The coil can also be easily integrated in an SiC mosfet module power stage and it is shown that the switching transient current waveform is faithfully captured.

The impedance-based stability criteria are widely adopted for small-signal stability analysis of power systems. Among them, the determinant-based multi-input multi-output (MIMO) Nyquist criterion is particularly attractive since it simplifies the stability determination process without calculating the eigenvalues of MIMO systems. However, it is found in this letter that the determinant-based Nyquist criterion can potentially result in incorrect stability analysis results with pure inductance models in the MIMO models of the power network. This letter illustrates the issue and its root cause through mathematical derivation and numerical analysis. Then, the issue is demonstrated through an example system, and the corresponding solutions are provided as well.

With the increasing penetration of inverter-based resources (IBRs) and the standing down of synchronous generator-based resources (SGBRs), some IBRs, at least, need to provide grid support functions commonly provided by SGBRs. IBRs usually have a much smaller overcurrent capability than SGBRs, which can result in weak grid strength and corresponding issues on grid transient voltage support, system protection, and black start. This paper aims at addressing the low overcurrent capability issue of IBRs from the source side by combining an IBR with a co-located synchronous condenser (SC). Dubbed grid strengthening IBR (GSI), the proposed setup in grid forming mode uses the SC to regulate the terminal voltage and the IBR to regulate the frequency. The proposed GSI is evaluated through its comparison with an SGBR in the single-unit operation considering different grid faults, multi-unit operation, and transient stability performance. It is verified that the GSI can provide an overcurrent and maintain the terminal voltage comparable to or even slightly better than the SGBR during grid faults. The GSI does not have any transient stability issues; even after a long fault period, it can reestablish the system synchronism. The GSI can help the penetration of the IBRs in the system, as the system operation and the system loads will be largely unaffected, even during transients.

The current limiting function enables the solid-state circuit breaker (SSCB) to have proper protection coordination. It allows sustained overcurrent for a certain period while preventing the fast fault current increase in dc systems. For the conventional method of using switches alone to limit the current, the high loss results in a short withstand time and low current limiting capability of the SSCBs. In this letter, a control strategy is proposed to utilize the energy absorption component to handle the major part of the energy during the current limiting stage to increase the current limiting capability for series-connected SSCB switching cells. The proposed method is experimentally verified to have more than 3X current limiting withstand time compared to the conventional control strategy in a case study.

Paralleled dies in a power module could have instability issues during high current switching transients. The instability is caused by the differential-mode oscillation among paralleled MOSFETs. Conventional analyses of paralleled MOSFETs’ stability are normally limited to a single operating point, which ignores the influences of the switching trajectory and nonlinear device parameters on stability. This article reveals that the switching trajectory can significantly influence parallel stability. The analysis is improved by solving eigenvalues of state-space modeling system matrices of all operating points that the switching trajectory goes through considering nonlinear device parameters. Higher voltage and current stresses result in greater real parts of complex eigenvalues, which explains why the paralleled MOSFETs are more unstable with higher voltage and current stresses. To improve stability in solid-state circuit breaker applications, we propose a method to manipulate the switching trajectory to avoid the unstable region where the conventional hard switching trajectory normally goes through. Experimental results show that the turn-off current capability can be increased from ∼five times of rated current with the gate oscillation using the conventional turn-off trajectory to ∼ten times of rated current without the gate oscillation using the optimal turn-off trajectory.

Industrial motor systems make up a quarter of all electric sales in the United States. Variable speed drives (VSDs) can provide energy efficiency savings to the customer by regulating motor speed based on specific and varying needs. In addition to the benefits provided to the customer, VSDs can provide support to the grid through ancillary services. The Center for Ultra-Wide-Area Resilient Electric Energy Transmission Networks (CURENT) developed a power electronics converter-based grid emulator to allow testing of various power system architectures and demonstration of key technologies in monitoring, control, actuation, and visualization. This paper proposes using an active front-end VSD's connected motor load to provide frequency regulation to a large scale power grid. Each part of the emulator is described including motor and power electronics model and control. The proposed frequency regulation is implemented in VSDs and modeled in both a transmission system in EMTDC/PSCAD and verified on CURENT's hardware testbed.

This paper proposes a novel continuously variable series reactor (CVSR) based on a dc current controller (DCC) to manage power flow in transmission systems. There are threefold major contributions. First, the three-dimensional electromagnetic interaction has been comprehensively analyzed to extend the understanding beyond the conventional 2D relationship. Second, a high-fidelity reluctance model of the CVSR with an improved DCC model is proposed and implemented. To overcome the fundamental concern for the system modeling, the DCC has been modeled as an ideal current source in parallel with an output impedance. The induced back-EMF can be precisely projected which provides critical design guidelines for the DCC. Third, inspired by the theoretical analysis and modeling, a reliable high power DCC converter is designed accordingly to interface with kV-level back-EMF and supply kA-level dc current for a 115 kV / 1500 A CVSR. Experiments are conducted in a practical transmission demonstration system. When the ac current in the transmission system varies from zero to 1500 A, experimental results show that the proposed CVSR can continuously regulate the reactance from 1.6 Ω to 5 Ω, validating the effectiveness of the proposed system design and modeling methodology.

The modular multilevel converter (MMC) is a popular topology in medium- and high-voltage applications, and many efforts have been spent on MMC modeling. However, the impact of submodule voltage sensor noise (SVSN), which becomes more severe due to increasing switching speed of power semiconductors and compact submodule design, has not been considered in conventional models. In this letter, the SVSN is introduced by coupling capacitances between the sensor and power stage in an MMC switching model. Furthermore, the SVSN impact is considered in an MMC average model based on derivation of the relationship between the SVSN and the duty cycle. The proposed MMC switching model and average model considering the SVSN are validated by comparing simulations with experimental results in an MMC prototype using 10-kV SiC MOSFETS.

High bandwidth sensors are required to measure the wide-bandgap devices' transient behavior because of their fast switching speed. In addition to high bandwidth, the current sensor must introduce little extra parasitic inductance to the switching power loop. The analysis of conventional shunt resistors shows the key to high bandwidth is the coaxial structure and its parasitic inductance is proportional to its transient heat energy rating. By combining the structure of coaxial shunt resistor and alumina substrate surface mount thin film resistors, a novel surface mount coaxial shunt resistor is introduced. Experimental measurement verifies its capability of achieving very high bandwidth while introducing very low parasitic inductance. The design can achieve up to 2.23-GHz measurement bandwidth while keeping its parasitic inductance as low as 0.12 nH. Application in gallium nitride heterojunction-field-effect-transistors double pulse test shows it can faithfully capture the transient current waveform while introducing little interference to the switching behavior.

This article presents the cryogenically cooled application for wide bandgap (WBG) semiconductor devices. Characteristics of silicon carbide (SiC) and gallium nitride (GaN) at cryogenic temperatures are illustrated. SiC MOSFETs exhibit increased on-state resistance and slower switching speed at cryogenic temperatures. However, cryogenic cooling provides low ambient temperature environment and thus enables the SiC converter to operate at lower junction temperature to achieve higher efficiency compared to room temperature cooling. A cryogenically cooled MW-level SiC inverter prototype is developed and demonstrated the feasibility of operating high-power SiC converter with cryogenic cooling. GaN HEMTs exhibit more than five times on-state resistance reduction and faster switching speed at cryogenic temperatures which makes GaN HEMTs an excellent candidate for cryogenic power electronics applications. The significantly reduced on-state resistance of GaN devices provides the possibility to operate them at a current level much higher than rated current at cryogenic temperatures. A GaN double pulse test (DPT) circuit is constructed and demonstrated that GaN HEMTs can operate at nearly four times of rated current at cryogenic temperatures. Challenges of utilizing WBG device with cryogenic cooling are discussed and summarized.

Medium-frequency transformer (MFT) dc bias is critical for the safe operation of dual-active-bridge (DAB) converters. To analyze the dc bias, expressions of dc bias are derived for SiC MOSFET DAB converters. It shows that the dc bias is a current source in steady state; thus, a dc bias current capacity is defined and used as a design constraint in the optimization of MFT. The dc bias current capacity is related to core materials, geometric parameters, and flux density, which is analyzed with analytical expression. Optimization equations with geometric variables are derived, which can be solved theoretically or numerically for both interleaved winding (IW) and separated winding (SW) MFT without and/or with leakage inductance design. Based on the optimization equations, different MFT designs for a 150-kW SiC MOSFET DAB converter are compared on the aspects of core materials, winding structures, and without/with leakage inductance design. The combination of IW structure MFT with auxiliary phase shift inductors is chosen, and the assembled prototype is tested with the 150-kW DAB converter. The designed dc bias capacity, temperature rise, and efficiency are verified.

Medium-voltage (MV) power electronics equipment has been increasingly applied in distribution grids, and high-voltage (HV) silicon carbide (SiC) power semiconductors have attracted considerable attention in recent years. This paper first overviews the development and status of HV SiC power semiconductors. Then, MV power-converter applications in distribution grids are summarized and the benefits of HV SiC in these applications are presented. Microgrids, including conventional and asynchronous microgrids, that can fully demonstrate the benefits of HV SiC power semiconductors are selected to investigate the benefits of HV SiC in detail, including converter-level benefits and system-level benefits. Finally, an asynchronous microgrid power-conditioning system (PCS) prototype using a 10 kV SiC MOSFET is presented.

A variable speed drive (VSD) based induction motor power emulator is presented in this paper, which is intended to be used in a real-time multi-converter-based hardware testbed (HTB) system. The presented HTB load emulator can accurately reflect the dynamic performance of a VSD-based load with multiple control algorithms without requiring significant computational resources and simulation time. Therefore, the developed VSD load emulator can not only mimic VSD-driven motor load performance, but also can be flexibly integrated into electric power grid emulators or simulators, which enable more detailed power grid analyses by providing a more accurate model for this particular type of load. This paper discusses the specification of the developed VSD-based load emulator, including multiple control schemes, and the physical realization in a power grid emulator. Finally, the accuracy of the VSD load emulator is demonstrated with experimental results.

In contrast with conventional microgrids (MGs) with fixed boundaries, a smart and flexible MG with dynamic boundary is introduced in this paper. Such a MG can dynamically change its boundary by picking up or shedding load sections of a distribution feeder depending on its available power, leading to more flexible operation, better utilization of renewables, smaller size of energy storage system, higher reliability, and lower cost. To achieve a flexible MG, the main challenges in MG design are addressed, including recloser placement, MG asset sizing considering resilience, system grounding design, and protection system design. Meanwhile, a hierarchical structure is employed to design and implement the MG controller. On top of the functions defined in IEEE 2030.7-2018, a few new functions, e.g., online topology identification and PQ balance, are added, while the planned/unplanned islanding and reconnection functions are enhanced. The controller is implemented on a CompactRIO, a general-purpose hardware platform provided by National Instruments (NI), and tested on a controller hardware-in-the-loop setup based on an OPAL-RT real-time simulator and a reconfigurable power electronic converter-based hardware testbed. The test results have validated the performance of the developed controllers. Such a flexible MG and its controller have been deployed at a municipal utility, and part of the controller’s functions have been tested on-site.

Planned islanding is one of the fundamental functions of microgrid (MG) controllers. However, existing planned islanding functions cannot be directly utilized in MGs that have the capability to have both dynamic boundary and multiple sub-MGs. To optimize the smart switch operation and distributed energy resource (DER) output power, a planned islanding algorithm is designed to minimize the battery energy storage systems’ power difference before and after a planned islanding. To verify the performance of the proposed algorithm, a hardware-in-the-loop (HIL) test has been conducted by implementing the algorithm in a general purpose MG controller system. The results demonstrate that the difference in active power before and after the planned islanding decreases significantly with the proposed algorithm.

This article establishes an analytical model for the device drain-source overvoltage related to the two loops in three-level active neutral point clamped (3L-ANPC) converters. Taking into account the nonlinear device output capacitance, two common modulation methods are investigated in detail. The results show that the line switching frequency device usually has higher overvoltage, and the switching speed of the high switching frequency device is not strongly influenced by the multiple loops. By keeping the nonactive clamping switch off, the effect of the nonlinear device output capacitance can be significantly mitigated, which helps reduce the overvoltage. Moreover, the loop inductance can be reduced with vertical loop layout and magnetic cancellation in the printed circuit board and busbar design. A 500-kVA 3L-ANPC converter using silicon carbide mosfets was built and tested. The experimental results validate the overvoltage model of the two modulation methods as well as the busbar design. With the nonactive clamping switch off, the overvoltage of both the high and line switching frequency devices is significantly reduced, which helps achieve higher switching speed.

In order to evaluate the feasibility of newly developed gallium nitride (GaN) devices in a cryogenically cooled converter, this article characterizes a 650-V enhancement-mode GaN high-electron mobility transistor (GaN HEMT) at cryogenic temperatures. The characterization includes both static and dynamic behaviors. The results show that this GaN HEMT is an excellent device candidate to be applied in cryogenic-cooled applications. For example, transconductance at cryogenic temperature (93 K) is 2.5 times higher than one at room temperature (298 K), and accordingly, peak di/dt during turn-on transients at cryogenic temperature is around 2 times of that at room temperature. Moreover, the ON-resistance of the channel at the cryogenic temperature is only one-fifth of that at room temperature. The corresponding explanations of performance trends at cryogenic temperatures are also given from the view of semiconductor physics. In addition, several device failures were observed during the dynamic characterization of GaN HEMTs at cryogenic temperatures. The ultrafast switching speed-induced high di/dt and dv/dt at cryogenic temperatures amplify the negative effects of parasitics inside the switching loop. Based on failure waveforms, two failure modes were classified, and detailed failure mechanisms caused by ultrafast switching speed are given in this article.

To better support the superconducting propulsion system in the future aircraft applications, the technologies of high-power high switching frequency power electronics systems at cryogenic temperatures should be investigated. This article presents the development of a 40-kW cryogenically cooled three-level active neutral point clamped inverter with 3 kHz output line frequency and 140 kHz switching frequency. Si mosfets are characterized at cryogenic temperatures, and the results show that they have promising performance such as lower on-resistance and switching loss. The design of the inverter is presented in detail with the special consideration of the cryogenic temperature operation. Moreover, a packaging and integration architecture is designed and fabricated to demonstrate the feasibility and performance of the inverter in the lab. It is able to achieve no leakage with good thermal and air insulation. With the inverter and packaging, the experimental results show that the inverter operates properly at cryogenic temperatures. The loss is measured at different load conditions, and the loss analysis is given, which shows that the cryogenically cooled inverter has 30% less loss than operating at room temperature.

Paralleling three phase three-level inverters is gaining popularity in industrial applications. However, analytical models for the harmonics calculation of a three-level neutral point clamped (NPC) inverter with popular space vector modulation (SVM) are not found in the literature. Moreover, how interleaving angle impacts the dc- and ac-side harmonics and electromagnetic interference (EMI) harmonics in parallel interleaved three-level inverters and how to optimize interleaving angle to reduce these harmonics have not been discussed in the literature. Furthering previous study, this article presents the modeling, analysis, and reduction of harmonics in paralleled and interleaved three-level NPC inverters with SVM. Analytical models for harmonic calculation are developed, and the dc-side harmonics characteristics of an NPC inverter are identified. The impact of interleaving angle on the ac-side voltage and dc-link current harmonics of parallel interleaved three-level NPC inverters is comprehensively studied. The impact of switching frequency and interleaving angle on EMI harmonics is also illustrated. Optimal interleaving angle ranges to reduce these harmonics are derived analytically. The developed models and harmonic reduction analysis are verified experimentally with two paralleled and interleaved three-level NPC inverters.

The attenuation performance of an electromagnetic interference filter can be significantly degraded by coupling, parasitics, and frequency-dependent nonlinearity, especially in high frequency (HF) range. This article reveals and investigates a mutual capacitive coupling effect in the popular filter structures with T-shaped joint. The mechanism is explained and the impact on filter attenuation is analyzed, which show this coupling is the dominant cause of performance degradation of T-shaped filters and a major cause for other T-shape-related filters. The effect patterns for both common-mode (CM) and differential-mode (DM) filters are analytically derived and further examined in multistage filter structures. Mitigation solutions using PCB slits and grounded shielding are proposed to improve filter transfer gain up to 30 dB in the HF range. A topological strategy is also presented, further enhancing filter attenuation. In addition, the impact of relative positions of the inductors on the coupling capacitance is discussed, and five positions are experimentally studied and compared. Experimental results obtained from three-phase LCL and LCLC filters verify the significance of this coupling and the effectiveness of the mitigation methods.

In order to apply power electronics systems to applications such as superconducting systems under cryogenic temperatures, it is necessary to investigate the characteristics of different parts in the power electronics system. This article reviews the influence of cryogenic temperature on power semiconductor devices including Si and wide bandgap switches, integrated circuits, passive components, interconnection and dielectric materials, and some typical cryogenic converter systems. Also, the basic theories and principles are given to explain the trends for different aspects of cryogenically cooled converters. Based on the review, Si active power devices, bulk Complementary metal-oxide-semiconductor (CMOS) based integrated circuits, nanocrystalline and amorphous magnetic cores, NP0 ceramic and film capacitors, thin/metal film and wirewound resistors are the components suitable for cryogenic operation. Pb-rich PbSn solder or In solder, classic printed circuit boards material, most insulation papers and epoxy encapsulant are good interconnection and dielectric parts for cryogenic temperatures.

This paper studies how an outer fractional winding can impact the equivalent parallel capacitance (EPC) of a differential-mode inductor, which is a critical passive component in a power electronic converter to combat with electromagnetic noises, and proposes a winding scheme that can reduce EPC and increase inductance, achieving both high-frequency filtering performance and high density. To perform these studies, a comprehensive layer capacitance model based on energy equivalence principle is established, which decouples EPC contribution among three elements, i.e., outer fraction layer, layer-to-layer, and layer-to-core, thus enabling the impact evaluation of different winding elements and schemes. Experimental comparison results have validated the accuracy of this EPC model and excellent performance of the proposed winding scheme with EPC reduction by 4×. It reveals that contrary to previous understanding, the inverse winding, in fact, is more effective for EPC reduction than the direct winding in most of the partial layer scenarios, and that by using this scheme with the outer fraction layer, 45% higher inductance and slightly less EPC can be achieved, compared to the single-layer winding design.

Three-level converters are more susceptible to parasitics compared with two-level converters because of their complicated structure with multiple switching loops. This paper presents the methodology of busbar layout design for three-level converters based on magnetic cancellation effect. The methodology can fit for 3L converters with symmetric and asymmetric configurations. A detailed design example is provided for a high power three-level active neutral point clamped (ANPC) converter, which includes the module selection, busbar layout, and DC-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. The results match with each other, and the inductances of short and long loops are 6.5 nH and 17.5 nH respectively, which are significantly lower than the busbars of NPC type converters in other references.

For system planning of three-phase inverter-based islanded ac microgrids, the low frequency instability issue caused by interactions of inverter droop controllers is a major concern. When internal control information of procured commercial inverters is unknown, impedance-based small-signal stability criteria facilitate prediction of resonances in medium and high frequency ranges, but they usually assume the grid fundamental frequency as constant and thus they are incapable of analyzing the low-frequency oscillation of the fundamental frequency in islanded microgrids. Aiming at solving this issue, this paper proposes two stability analysis methods based on terminal characteristics of inverters and passive connection network including the dynamics of the fundamental frequency for analysis of low-frequency stability in islanded multiple-bus microgrids. Based on the Component Connection Method (CCM) to systematically separate inverters from the passive connection network, a general approach is developed to model the microgrid as a multiple-input-multiple-output (MIMO) negative feedback system in the common system d-q reference frame. By applying the generalized Nyquist stability criterion (GNC) to the return-ratio and return-difference matrices of the MIMO system model, the low-frequency stability related to the fundamental frequency can be analyzed using the measured terminal characteristics of inverters. Analysis and simulation of a 37-bus microgrid verify the effectiveness of the proposed stability analysis methods.

Using high voltage (HV) Silicon Carbide (SiC) power semiconductors in the modular multilevel converter (MMC) is promising because of a fewer submodules and lower switching loss compared to conventional Si based solutions. The nearest level pulse width modulation (NL-PWM) is commonly used in the MMC for medium voltage applications. However, with the NL-PWM and existing voltage balancing control, there are many submodules that switch their modes in a control cycle, resulting in a high dv/dt during the deadtime of the power semiconductor, which could be multiple times of the dv/dt of single device. This poses great challenges on the noise immunity and insulation design in the MMC using HV SiC devices, which have very fast switching speed. A novel voltage balancing control, which ensures only two submodules switch their modes in a control cycle, is proposed in this paper, limiting the maximum dv/dt to the dv/dt of single power semiconductor and meanwhile maintaining the voltage balance performance. The proposed voltage balancing control is experimentally validated in a 10 kV SiC MOSFET based MMC with four submodules per arm.

High performance gate drive power supply (GDPS) plays a crucial role in ensuring the reliability and safety of the gate driver for power semiconductor devices. This paper focuses on the design of a high-voltage- insulated GDPS for the 10-kV SiC MOSFET in medium-voltage (MV) application. Design considerations, including insulation scheme, high-voltage-insulated transformer design, and load voltage regulation scheme, are proposed. In addition, the performance of the secondary-side-regulated (SSR) GDPS and that of the primary-side-regulated (PSR) GDPS are compared for several aspects, including inter-winding capacitance, load-voltage-regulation-rate, conversion efficiency, and hardware complexity. Finally, an SSR GDPS and a PSR GDPS, with an insulation voltage of 20 kV, are built in the lab. The test results demonstrate that the PSR GDPS is more preferable because of lower interwinding capacitance, lower load-voltage-regulation-rate, higher conversion efficiency, and simpler control circuit.

Multi-pulse AC/DC Rectifiers (MPRs) are widely used in aviation application due to their rugged structure, cost effective, and high reliability features. In this paper, an overview of the recent advances and trends on the MPR technology, mainly the auto-configured transformer based MPRs, and its application in more electric aircrafts are performed. The work covers system topologies, transformer configurations, passive and active harmonic reduction schemes, case study, practical selection and design guideline, and applications. To fairly evaluate the performances of MPRs with different pulse number, necessary simulation studies are carried out under comparable conditions, including power rating, input and output specifications, and transformer configuration etc. Then, an 18-pulse asymmetric DP configured prototype is established based on the simulation evaluation and experimental verification is performed. It is expected that the paper can provide a broad perspective on MPR technology, and, in particular, highlight the latest emerged technology that significantly promotes the performances of MPRs. More importantly, it is desired that the results obtained in this paper can provide an effective selection guideline and design suggestion for researchers and engineers engaged in designing MPRs, especially for aviation application.

Novel power system control and new utility devices need to be tested before their actual deployment to the power grid. To assist with such a testing need, real-time digital emulators such as RTDS and Opal-RT can be used to connect to the physical world and form a hardware in the loop (HIL) emulation. However, due to the limitations of today's computational resources, the accuracy and fidelity suffer from different levels of model reductions in purely digital simulations. CURENT has developed a reconfigurable electric grid hardware testbed (HTB) to overcome the limitations of digital emulators. The HTB has been used to develop measurement, control, modeling, and actuation techniques for a national grid with a high penetration of renewables. The power electronic-based system includes emulators for synchronous generators; photovoltaics with grid-interfacing inverter; wind turbines; induction motor loads, ZIP loads, power electronic loads; batteries; ac and dc transmission lines; short circuit faults and grid relay protection; and a multiterminal HVDC overlay including power electronics interfaces. The system contains real elements of power flow, measurement, communication, protection, and control that mimic what would be seen in an actual electric grid. This paper presents an overview of the HTB and several scenarios that have been run to determine control and actions needed for the future power grid.

Middle-point inductance Lmiddle can be introduced in multiple-chip power module package designs. In this paper, the effect of middle-point inductance on switching transients is analyzed first using a frequency-domain analysis. Then a dedicated multiple-chip power module is fabricated with the capability of varying Lmiddle, and extensive switching tests are conducted to evaluate the middle-point inductance's impact. Experiment result shows that the active MOSFET's turn-on loss decreases at higher values of Lmiddle, while its turn-off loss increases. Detailed analysis of this loss variation is presented. In addition to the switching loss variation, it is also observed that different peak voltage stresses are imposed on the active switch and antiparallel diode during the switching transients. Specifically, in the case of lower MOSFET's turn-off, the maximum voltage of the lower MOSFET increases as Lmiddle goes up; however, the peak voltage of the antiparallel diode decreases significantly. The induced voltage spikes during upper MOSFET turn-on process is also evaluated, and an opposite trend is observed experimentally. Analysis of the voltage overshoot variation is discussed. Based on the experimental evaluation and analysis, a multiple-chip power module package design guideline is summarized considering the middle-point inductance's effect.

Parasitic ringing is commonly observed during the high-speed switching of wide band-gap (WBG) devices. Additional loss contributed by parasitic ringing becomes a concern especially for high switching frequency applications. This paper investigates the effects of parasitic ringing on the switching loss of WBG devices in a phase-leg configuration. An analytical switching loss model considering parasitics in power devices and application circuit is derived. Two switching commutation modes, gate drive dominated mode and power loop dominated mode, are investigated, respectively, and the switching loss induced by damping ringing is identified. It is found that this portion of the loss is at most the energy stored in parasitics, which always exists regardless of the switching speed and parasitic ringing. Therefore, with the given WBG device in the specific application circuit, damping more severe parasitic ringing during faster switching transient would not introduce higher switching loss. Additionally, the extra switching loss induced by resonance among parasitics and crosstalk is investigated. It is observed that severe resonance and its resultant over-voltage during the turn-on transient worsen the crosstalk, causing large shoot-through current and excessive switching loss. The theoretical analysis has been verified by the double pulse test with a 1200-V/50-A SiC-based phase-leg power module.

To understand the limitation of maximizing the switching speed of SiC low current discrete devices and high current power modules in hard switching applications, double pulse tests are conducted and the testing results are analyzed. For power modules, the switching speed is generally limited by the parasitics rather than the gate drive capability. For discrete SiC devices, the conventional voltage source gate drive (VSG) is not sufficient to maximize the switching speed even if the external gate resistance is minimized. The limitation of existing current source gate drives (CSG) are analyzed, and a CSG dedicated for SiC discrete devices is proposed, which can provide constant current during the switching transient regardless of the high Miller voltage and large internal gate resistance. Compared with the conventional VSG, the proposed CSG achieves 67% faster turnon time and 50% turn-off time, and 68% reduction in switching loss at full load condition.

This paper identifies extra junction capacitances and switching commutation loops introduced by line-frequency devices (i.e., non-active every other half line cycle) in three-level ac/dc converters and investigates the corresponding effects. Junction capacitances and power loops are well known as the key factors that impact converter switching loss and device stress, thus influence device selection, power stage layout, and thermal design. By examining switching transients of the commonly used T-shaped and I-shaped three-level converters, the cause and mechanism of the extra junction capacitances and power loops are presented. The impacts on switching loss, device voltage stress, and ac-side voltage/current distortion are respectively reported and analyzed. A loss calculation scheme for the three-level converter to include that extra loss is proposed. A power layout scheme to mitigate the device voltage stress is provided. Compensation and modeling of the voltage and current distortion are also proposed. Experimental results conducted on several types of three-level converter prototypes including a gallium nitride based 115 Vac/650 Vdc/1.5-kW/450-kHz Vienna-type rectifier and a SiC MOSFET based 1-kV/10-kW/ 280-kHz three-level active neutral-point-clamped inverter confirm the presented effects and verify the associated analysis and solutions.

Junction temperature is an important design/operation parameter, as well as, a significant indicator of device's health condition for power electronics converters. Compared to its silicon (Si) counterparts, it is more critical for silicon carbide (SiC) devices due to the reliability concern introduced by the immaturity of new material and packaging. This paper proposes a practical implementation using an intelligent gate drive for online junction temperature monitoring of SiC devices based on turn-off delay time as the thermo-sensitive electrical parameter. First, the sensitivity of turn-off delay time on the junction temperature for fast switching SiC devices is analyzed. A gate impedance regulation assist circuit is proposed to enhance the sensitivity by a factor of 60 and approach 736 ps/°C tested in the case study with little penalty on the power conversion performance. Next, an online monitoring unit based on gate assist circuits is developed to monitor the turn-off delay time in real time with the resolution less than 104 ps. As a result, the micro-controller is capable of “reading” junction temperature during the converter operation. Finally, a SiC-based half-bridge inverter is constructed with an intelligent gate drive consisting of the gate impedance regulation circuit and online turn-off delay time monitoring unit. Experimental results demonstrate the feasibility and accuracy of the proposed approach.

As wide-bandgap (WBG) devices and applications move from niche to mainstream, a new generation of engineers trained in this area is critical to continue the development of the field. This paper introduces a new hands-on course in characterization of WBG devices, which is an emerging and fundamental topic in WBG-based techniques. First, the lecture-simulation-experiment format based course structure and design considerations, such as safety, are presented. Then, the necessary facilities to support this hands-on course are summarized, including classroom preparation, software tools, and laboratory equipment. Afterward, the detailed course implementation flow is presented to illustrate the approach of close interaction among lecture, simulation, and experiment to maximize students' learning outcomes. Finally, grading for students and course evaluation by students are discussed, highlighting the findings and potential improvements. Detailed course materials are provided via potenntial.eecs.utk.edu/WBGLab for educational use.

For some distribution networks equipped with smart switches such as Chattanooga Electric Power Board (EPB) system, they can island some areas of the network to mitigate the impact through defensive islanding. However, due to intermittency and uncertainty of renewable-based distributed energy resources (DERs), it is highly likely that the islanded areas would experience insufficient or surplus power. This problem can be relieved by changing the boundaries of islanded areas to incorporate neighbouring load sections (LSs) or disconnect some connected LSs. Considering penetration level and sharply changing rate of renewable energy, it is challenging to define suitable boundaries for islanded areas in real time. Therefore, a two-stage energy management system (EMS) is proposed in this study, which includes day-ahead scheduling stage as well as short-term and real-time control stages. In the first stage, the initial switch combinations of LSs and DERs’ scheduling are obtained through a mixed integer quadratic programming, whereas the second stage is based on rule-based power management algorithm. Finally, a model reduced from real EPB system is used for validating the proposed two-stage EMS. The results successfully verify the effectiveness and performance of the proposed EMS for addressing the energy management of islanded areas under defensive islanding.

This paper presents the characterization of the temperature-dependent short-circuit performance of a Gen3 10 kV/20 A silicon carbide (SiC) mosfet. The test platform consisting of a phase-leg configuration and a fast speed 10-kV solid state circuit breaker, with temperature control, is introduced in detail. A novel FPGA-based short-circuit protection circuit having a response time of 1.5 μs is proposed and integrated into the gate driver. The short-circuit protection is validated through the platform. The short-circuit characteristics for both the hard switching fault and fault under load (FUL) types at various dc-link voltages (from 500 V to 6 kV) are tested and discussed. The saturation current increases with dc-link voltage and achieves 360 A at 6 kV. Different from low voltage SiC devices, there is no current spike in FUL type of fault. The temperature-dependent short-circuit performance is also presented from 25 to 125 °C. The difference of short-circuit waveforms at various initial junction temperatures can be neglected. A thermal model of the 10-kV SiC mosfet is built for the junction temperature estimation during the short circuit and for analysis of the initial junction temperature impact on the short-circuit performance.

Battery energy storage systems (BESSs) tend to be too costly, restrictive, and require high maintenance for experimental use, but power system tests often need their representation. As a solution, we propose an all-in-one, reconfigurable BESS emulation tool for grid applications that only requires one three-phase voltage-source converter. This emulator provides chemistry-specific battery behavior like previous work, but it also includes the BESS's power electronics interface and control as well as automatic frequency and voltage support functions for the attached power system. Thus, it allows simple, plug-and-play BESS emulation for grid applications. This paper details the construction, verification, and use of the BESS emulator in an existing grid testbed and concludes that it provides an inexpensive, easy-to-use alternative to using real BESSs in power system experiments.

The design, implementation, and testing of a control system for a flexible microgrid (MG) is presented in this study. The MG controllers can be implemented in a real-world MG with multiple smart switches, photovoltaic panel system, and battery energy storage systems (BESSs). With the benefits from smart switches, the MG has unique characteristics such as dynamic boundary and flexible point of interconnection (POI) concepts. To control such a unique MG and realise the dynamic boundary, an MG central controller and two types of local controllers are implemented. Compared to the MG with fixed boundary, the MG with dynamic boundary can have smaller BESS capacity, better utilisation of renewable energy, and multiple POI options. Also, compared with IEEE Std 2030.7–2017, the topology identification and active and reactive power balance functions are newly designed to realise the dynamic boundary concept. The planned islanding and reconnection functions are modified to realise the flexible POI concept. These functions are introduced including the software architecture, cooperation, and interaction among them. Finally, a hardware-in-the-loop testing platform based on the Opal-RT real-time simulator is set up to verify the performance, realisation of the dynamic boundary, and flexible POI concepts with four comprehensive test scenarios.

Semiconductor devices based solid-state circuit breakers (SSCBs) are promising in the dc power distribution system as protective equipment for their ultrashort action time. This letter proposes a topology of SSCB using series connected silicon carbide (SiC) metal oxide semiconductor field effect transistors (mosfets), which only requires a single isolated gate driver. The SSCB has very low cost and high reliability because it only has 13 components including passive components and diodes apart from two SiC mosfets to achieve both balanced voltage distribution during short-circuit interruption duration and reliable positive gate voltage during on-state. The SSCB prototype is built and experimentally verified to interrupt 75 A short-circuit current under the dc-bus voltage of 1200 V within 1.5 μs.

This paper introduces the concept of modular design methodology for hardware design and development of motor drives. The modular design process is first introduced separating the hardware development into three parts: controller, mother board and phase-leg module. The control and circuit function can be decoupled from the phase-leg module development. The hardware update can be simplified with the phase-leg module development and verification. Two design examples are used to demonstrate this method: a DC-fed motor drive with Si IGBTs and an AC-fed motor drive with SiC devices. Design of DC-fed motor drive aims at developing the converter with customized IGBT package for high temperature. Experience with development of the converter with commercial IGBTs simplifies the process. As the AC-fed motor drive is a more complex topology using more advanced devices, the modular design method can simplify and improve the development especially for new packaged devices. Also, the modular design method can help to study the electromagnetic interference (EMI) issue for motor drives, which is presented with an extra design example.

The emergence of wide bandgap (WBG) semiconductor devices such as silicon carbide (SiC) and gallium nitride (GaN) devices promises to revolutionize next-generation power electronics converters. Featuring high breakdown electric field, low specific on-resistance, fast switching speed, and high junction temperature capability, these devices are beneficial for the efficiency, power density, reliability, and/or cost of power electronics converters. WBG devices have been employed in some commercial and industrial products with more applications expected in near future. However, extremely fast switching and other superior characteristics of WBG device, and high switching frequency/high voltage/high junction temperature operation, present new design challenges in gate drive and protection, packaging and layout, EMI suppression, and converter control, etc. Addressing these design and application issues is critical to the adoption, commercialization, and success of WBG based power electronics. This special issue intends to report the latest progress in these important areas.

This paper introduces series work of common-mode (CM) voltage reduction for the paralleled inverters. The paralleled inverters' phase-legs are connected through coupling inductors and the combined three-phase currents are provided to the load. Interleaving is an approach to reduce the CM voltage for the paralleled inverters but it cannot eliminate CM voltage. A novel pulse-width-modulation (PWM) method for paralleled inverters which can theoretically achieve zero CM voltage is developed. Considering the basic voltage vectors in each inverter, novel paralleled voltage vectors which have zero CM voltage are proposed to combine the reference voltage vector. The action time's distribution and voltage vectors' sending sequence for each inverter are also introduced. The proposed PWM method can make sure the voltage of the two inverters are balanced in each switching cycle and limits the circulating current through small coupling inductors. Similar to interleaving space vector PWM, the proposed zero CM PWM also has the ability to reduce the output current ripple and electromagnetic interference (EMI). Simulation and experimental results are provided to show the advantage of paralleled inverters in CM voltage reduction and validate the proposed method has good performance to reduce CM current and CM EMI noise.

A systematic study on a gallium nitride (GaN) high-electron-mobility transistor (HEMT) based battery charger, consisting of a Vienna-type rectifier plus a dc-dc converter, reveals a common phenomenon. That is, the high switching frequency, and high di/dt and dv/dt noise inside GaN converters may induce a dc drift or low frequency distortion on sensing signals. The distortion mechanisms for different types of sensing errors are identified and practical minimization techniques are developed. Experimental results on the charger system have validated these mechanisms and corresponding approaches, showing an overall reduction of input current total harmonic distortion (THD) by up to 5 percentage points and improved dc-dc output voltage regulation accuracy. The knowledge helps engineers tackle the troublesome issues related to noise.

Wide bandgap semiconductors are gradually being adopted in high power-density high efficiency applications, providing faster switching and lower loss, and at the same time imposing new challenges in control and hardware design. In this paper, a gallium nitride-based Vienna-type rectifier with SiC diodes is proposed to serve as the power factor correction stage in a high-density battery charger system targeting for aircraft applications with 800 Hz ac system and 600 V level dc link, where power quality is required according to DO160E standard. To meet the current harmonic requirement, PWM voltage distortion during the turn-off transient, is studied as the main harmonics contributor. The distortion mechanism caused by different junction capacitances of the switching devices is presented. A mitigation scheme considering the nonlinear voltage-dependent characteristics of these capacitances is proposed and then simplified from a pulse-based turn-off compensation method to a general modulation scheme. Simulation and experimental results with a 450 kHz Vienna-type rectifier demonstrate the performance of the proposed approach, showing a THD reduction from 10% to 3% with a relatively low-speed controller.

A Hardware Testbed(HTB) is developed for accurate and flexible emulation and testing of electrical power system and their control, measurement, and protection systems. In the HTB, modular and programmable power electronics converters are used to mimic the static and dynamic characteristics of electrical power components. This paper overviews the development, integration, and application of the HTB, covering emulation principle, hardware and software configuration, and example results of power system research using the HTB. The advantages of the HTB, compared with real-time digital simulation and downscaled hardware-based testing platform are discussed.

A transmission line emulator has been developed to flexibly represent interconnected ac lines under normal operating conditions in a voltage-source-converter-based power system emulation platform. As the most serious short-circuit fault condition, the three-phase short-circuit fault emulation is essential for power system studies. This paper proposes a model to realize a three-phase short-circuit fault emulation at different locations along a single transmission line or one of several parallel-connected transmission lines. At the same time, a combination method is proposed to eliminate the undesired transients caused by the current reference step changes while switching between the fault state and the normal state. Experiment results verify the developed transmission line three-phase short-circuit fault emulation capability.

The series connection of insulated gate bipolar transistors (IGBTs) allows operation at voltage levels higher than the rated voltage of one IGBT and has less power semiconductor costs compared to multilevel topologies. However, voltage unbalance during the switching transient is a challenge for series-connected device application. This paper presents an field-programmable gate array (FPGA)-based voltage balancing strategy for multiseries-connected high-voltage (HV)-IGBTs including an FPGA-based active voltage balancing control (AVBC) circuit integrated into the gate driver and the control for multiseries-connected IGBTs. The effectiveness of the control has been experimentally validated in a prototype using four 4.5 kV HV-IGBTs in series connection.

The temperature-dependent characteristics of the third-generation 10-kV/20-A SiC MOSFET including the static characteristics and switching performance are carried out in this paper. The steady-state characteristics, including saturation current, output characteristics, antiparallel diode, and parasitic capacitance, are tested. A double pulse test platform is constructed including a circuit breaker and gate drive with >10-kV insulation and also a hotplate under the device under test for temperature-dependent characterization during switching transients. The switching performance is tested under various load currents and gate resistances at a 7-kV dc-link voltage from 25 to 125 C and compared with previous 10-kV MOSFETs. A simple behavioral model with its parameter extraction method is proposed to predict the temperature-dependent characteristics of the 10-kV SiC MOSFET. The switching speed limitations, including the reverse recovery of SiC MOSFET's body diode, overvoltage caused by stray inductance, crosstalk, heat sink, and electromagnetic interference to the control are discussed based on simulations and experimental results.

Owing to the recent power outages caused by extreme events, installing battery energy storage and backup generators is important to improve resiliency for a grid-tied microgrid. In the design stage, the event occurrence time and duration, which are highly uncertain and cannot be effectively predicted, may affect the needed battery and backup generator capacity but are usually assumed to be pre-determined in utility planning tools. This study investigates the optimal battery and backup generator sizing problem considering the stochastic event occurrence time and duration for the grid-tied microgrid under islanded operation. The reliability requirement is quantified by the mean value of the critical customer interruption time in each stochastic islanding time window (ITW), whose length is the duration and the centre is the occurrence time. The stochastic ITW constraint is then transformed to a probability-weighted expression to derive an equivalent Mixed Integer Linear Programming model. Numerical simulations on a realistic grid-tied PV-based microgrid demonstrate that the total cost is reduced by 11.5% considering the stochastic ITW, compared with the deterministic ITW under the same reliability requirement.

Newly emerged gallium nitride (GaN) devices feature ultrafast switching speed and low on-state resistance that potentially provide significant improvements for power converters. This paper investigates the benefits of GaN devices in an LLC resonant converter and quantitatively evaluates GaN devices' capabilities to improve converter efficiency. First, the relationship of device and converter design parameters to the device loss is established based on an analytical model of LLC resonant converter operating at the resonance. Due to the low effective output capacitance of GaN devices, the GaN-based design demonstrates about 50% device loss reduction compared with the Si-based design. Second, a new perspective on the extra transformer winding loss due to the asymmetrical primary-side and secondary-side current is proposed. The device and design parameters are tied to the winding loss based on the winding loss model in the finite element analysis (FEA) simulation. Compared with the Si-based design, the winding loss is reduced by 18% in the GaN-based design. Finally, in order to verify the GaN device benefits experimentally, 400- to 12-V, 300-W, 1-MHz GaN-based and Si-based LLC resonant converter prototypes are built and tested. One percent efficiency improvement, which is 24.8% loss reduction, is achieved in the GaN-based converter.

This paper presents an intelligent gate drive for silicon carbide (SiC) devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control gate voltages and gate loop impedances of both devices in a phase-leg configuration during different switching transients. Compared to conventional gate drives, the proposed circuit has the capability of accelerating the switching speed of the phase-leg power devices and suppressing the crosstalk to below device limits. Based on Wolfspeed 1200-V SiC MOSFETs, the test results demonstrate the effectiveness of this intelligent gate drive under varying operating conditions. More importantly, the proposed intelligent gate assist circuitry is embedded into a gate drive integrated circuit, offering a simple, compact, and reliable solution for end-users to maximize benefits of SiC devices in actual power electronics applications.

With the increased cloud computing and digital information storage, the energy requirement of data centers keeps increasing. A high-voltage point of load (HV POL) with an input series output parallel structure is proposed to convert 400 to 1 VDC within a single stage to increase the power conversion efficiency. The symmetrical controlled half-bridge current doubler is selected as the converter topology in the HV POL. A load-dependent soft-switching method has been proposed with an auxiliary circuit that includes inductor, diode, and MOSFETs so that the hard-switching issue of typical symmetrical controlled half-bridge converters is resolved. The operation principles of the proposed soft-switching half-bridge current doubler have been analyzed in detail. Then, the necessity of adjusting the timing with the loading in the proposed method is analyzed based on losses, and a controller is designed to realize the load-dependent operation. A lossless RCD current sensing method is used to sense the output inductor current value in the proposed load-dependent operation. Experimental efficiency of a hardware prototype is provided to show that the proposed method can increase the converter's efficiency in both heavy- and light-load conditions.

Dead time significantly affects the reliability, power quality, and efficiency of voltage-source converters. For silicon carbide (SiC) devices, considering the high sensitivity of turn-off time to the operating conditions (> 5× difference between light load and full load) and characteristics of inductive loads (> 2× difference between motor load and inductor), as well as large additional energy loss induced by the freewheeling diode conduction during the superfluous dead time (~15% of the switching loss), then the traditional fixed dead time setting becomes inappropriate. This paper introduces an approach to adaptively regulate the dead time considering the current operating condition and load characteristics via synthesizing online monitored turn-off switching parameters in the microcontroller with an embedded preset optimization model. Based on a buck converter built with 1200-V SiC MOSFETs, the experimental results show that the proposed method is able to ensure reliability and reduce power loss by 12% at full load and 18.2% at light load (8% of the full load in this case study).

This paper develops a synchronous generator emulator by using a three-phase voltage source converter for transmission level power system testing. Different interface algorithms are compared, and the voltage type ideal transformer model is selected considering accuracy and stability. At the same time, closed-loop voltage control with current feed-forward is proposed to decrease the emulation error. The emulation is then verified through two different ways. First, the output waveforms of the emulator in experiments are compared with the simulation under the same condition. Second, a transfer function perturbation-based error model is obtained and redefined as the relative error for the amplitude and phase between the emulated and the target system over the frequency range of interest. The major cause of the error is investigated through a quantitative analysis of the error with varying parameters.

This paper presents a steady-state model of MMC for the second-order phase voltage ripple prediction under unbalanced conditions, taking the impact of negative-sequence current control into account. From the steady-state model, a circular relationship is found among current and voltage quantities, which can be used to evaluate the magnitudes and initial phase angles of different circulating current components. Moreover, in order to calculate the circulating current in a point-to-point MMC-based HVdc system under unbalanced grid conditions, the derivation of equivalent dc impedance of an MMC is discussed as well. According to the dc impedance model, an MMC inverter can be represented as a series connected R-L-C branch, with its equivalent resistance and capacitance directly related to the circulating current control parameters. Experimental results from a scaled-down three-phase MMC system under an emulated single-line-to-ground fault are provided to support the theoretical analysis and derived model. This new models provides an insight into the impact of different control schemes on the fault characteristics and improves the understanding of the operation of MMC under unbalanced conditions.

The double pulse test (DPT) is a widely accepted method to evaluate the dynamic behavior of power devices. Considering the high switching-speed capability of wide band-gap devices, the test results are very sensitive to the alignment of voltage and current (V-I) measurements. Also, because of the shoot-through current induced by Cdv/dt (i.e., cross-talk), the switching losses of the nonoperating switch device in a phase-leg must be considered in addition to the operating device. This paper summarizes the key issues of the DPT, including components and layout design, measurement considerations, grounding effects, and data processing. Additionally, a practical method is proposed for phase-leg switching loss evaluation by calculating the difference between the input energy supplied by a dc capacitor and the output energy stored in a load inductor. Based on a phase-leg power module built with 1200-V/50-A SiC MOSFETs, the test results show that this method can accurately evaluate the switching loss of both the upper and lower switches by detecting only one switching current and voltage, and it is immune to V-I timing misalignment errors.

Small-signal stability is an important concern in three-phase inverter-based ac power systems. The impedance-based approach based on the generalized Nyquist stability criterion (GNC) can analyze the stability related with the medium and high-frequency modes of the systems. However,. the GNC involves the right-half-plane (RHP) pole calculation of return-ratio transfer function matrices, which cannot be avoided for stability analysis of complicated ac power systems. Therefore, it necessitates the detailed internal control information of the inverters, which is not normally available for commercial inverters. To address this issue, this paper introduces the component connection method (CCM) in the frequency domain for stability analysis in the synchronous d-q frame, by proposing a method of deriving the impedance matrix of the connection networks of inverter-based ac power systems. Demonstration on a two-area system and a microgrid shows that: The CCM-enabled approach can avoid the RHP pole calculation of return-ratio matrices and enables the stability analysis by using only the impedances of system components, which could be measured without the need for the internal information. A stability analysis method based on d-q impedances, the CCM, and the determinant-based GNC is also proposed to further simplify the analysis process. Inverter controller parameters can be designed as stability regions in parameter spaces, by repetitively applying the proposed stability analysis method. Simulation and experimental results verify the validity of the proposed stability analysis method and the parameter design approach.

Hybrid ac/dc transmission extends the power transfer capacity of existing long ac lines closer to their thermal limit, by superposing the dc current onto three-phase ac lines through a zigzag transformer. However, this transformer could suffer saturation under unbalanced line impedance conditions. This paper introduces the concept of hybrid line impedance conditioner (HLIC) as a cost-effective approach to compensate for the line unbalance and therefore avoid saturation. The topology and operation principle are presented. The two-level control strategy is described, which enables autonomous adaptive regulation without the need of system-level control. Design and implementation are also analyzed, including dc-link capacitance as one of the key line conditioner components, HLIC installation, and protection under fault conditions. The cost study on this HLIC-based hybrid system is also performed to reveal the benefits of the solution. Simulation results and experimental results based on a down-scaled prototype are provided to verify the feasibility of the proposed approach.

One way to incorporate the increasing amount of wind penetration is to control wind turbines to emulate the behavior of conventional synchronous generators. However, the energy balance is the main issue for the wind turbines to be truly dispatchable by the power system operator such as the generators. This paper presents a comprehensive virtual generator control method for the full converter wind turbine, with a minute-level energy storage in the dc link as the energy buffer. The voltage closed-loop virtual synchronous generator control of the wind turbine allows it to work under both grid-connected and stand-alone condition. Power balance of the wind turbine system is achieved by controlling the rotor speed of the turbine according to the loading condition. With the proposed control, the wind turbine system can enhance the dynamic response, and can be dispatched and regulated by the system operator. The sizing design of the short term energy storage is also discussed in this paper. Experimental results are presented to demonstrate the feasibility and effectiveness of the proposed control method.

This paper presents the development of a scaled four-terminal high-voltage direct current (HVDC) testbed, including hardware structure, communication architecture, and different control schemes. The developed testbed is capable of emulating typical operation scenarios including system start-up, power variation, line contingency, and converter station failure. Some unique scenarios are also developed and demonstrated, such as online control mode transition and station re-commission. In particular, a dc line current control is proposed, through the regulation of a converter station at one terminal. By controlling a dc line current to zero, the transmission line can be opened by using relatively low-cost HVDC disconnects with low current interrupting capability, instead of the more expensive dc circuit breaker. Utilizing the dc line current control, an automatic line current limiting scheme is developed. When a dc line is overloaded, the line current control will be automatically activated to regulate current within the allowable maximum value.

Research on high voltage (HV) silicon carbide (SiC) power semiconductor devices has attracted much attention in recent years. This paper overviews the development and status of HV SiC devices. Meanwhile, benefits of HV SiC devices are presented. The technologies and challenges for HV SiC device application in converter design are discussed. The state-of-the-art applications of HV SiC devices are also reviewed.

Arm inductor in a modular multilevel converter (MMC) is used to limit the circulating current and dc short circuit fault current. The circulating current in MMC is dominated by second-order harmonic, which can be largely reduced with circulating current suppressing control. By analyzing the mechanism of the circulating current suppressing control, it is found that the circulating current at switching frequency becomes the main harmonic when suppression control is implemented. Unlike the second-order harmonic that circulates only within the three phases, switching frequency harmonic also flows through the dc side and may further cause high-frequency dc voltage harmonic. This paper develops the theoretical relationship between the arm inductance and switching frequency circulating current, which can be used to guide the arm inductance selection. The experimental results with a downscaled MMC prototype verify the existence of the switching frequency circulating current and its relationship with arm inductance.

Three-phase inverter-based multibus ac power systems could suffer from the harmonic instability issue. The existing impedance-based stability analysis method using the Nyquist stability criterion once requires the calculation of right-half-plane (RHP) poles of impedance ratios, which would result in a heavy computation burden for complicated systems. In order to analyze the harmonic stability of multibus ac systems consisting of both voltage-controlled and current-controlled inverters without the need for RHP pole calculation, this paper proposes two sequence-impedance-based harmonic stability analysis methods. Based on the summary of all major connection types including mesh, the proposed Method 1 can analyze the harmonic stability of multibus ac systems by adding the components one by one from nodes in the lowest level to areas in the highest system level, and accordingly, applying the stability criteria multiple times in succession. The proposed Method 2 is a generalized extension of the impedance-sum-type criterion to be used for the harmonic stability analysis of any multibus ac systems based on Cauchy's theorem. The inverter controller parameters can be designed in the forms of stability regions in the parameter space, by repetitively applying the proposed harmonic stability analysis methods. Experimental results of inverter-based multibus ac systems validate the effectiveness of the proposed harmonic stability analysis methods and parameter design approach.

The three-phase current source rectifier (CSR) features a step-down ac-dc voltage conversion function, smaller ac filter size compared with the traditional two-level voltage source rectifier, and inrush current limiting capability. However, large conduction loss of semiconductor devices has limited the wide application of traditional CSRs. In this paper, a new CSR topology, delta-type current source rectifier (DCSR), is proposed to reduce the conduction loss. The proposed rectifier has delta-type connections on its ac input side and its dc-link current can be shared by multiple devices at a given time. This paper introduces the DCSR's operation principle, modulation scheme, and design method. Based on the analysis, the conduction loss can be reduced by up to 20% with the proposed topology. An 8-kW prototype is then built to experimentally verify the performance of the DCSR.

This paper presents a comprehensive short-circuit ruggedness evaluation and numerical investigation of up-to-date commercial silicon carbide (SiC) MOSFETs. The short-circuit capability of three types of commercial 1200-V SiC MOSFETs is tested under various conditions, with case temperatures from 25 to 200 °C and dc bus voltages from 400 to 750 V. It is found that the commercial SiC MOSFETs can withstand short-circuit current for only several microseconds with a dc bus voltage of 750 V and case temperature of 200 °C. The experimental short-circuit behaviors are compared, and analyzed through numerical thermal dynamic simulation. Specifically, an electrothermal model is built to estimate the device internal temperature distribution, considering the temperature-dependent thermal properties of SiC material. Based on the temperature information, a leakage current model is derived to calculate the main leakage current components (i.e., thermal, diffusion, and avalanche generation currents). Numerical results show that the short-circuit failure mechanisms of SiC MOSFETs can be thermal generation current induced thermal runaway or high-temperature-related gate oxide damage.

Gallium nitride (GaN) power devices are an emerging technology that have only recently become available commercially. This new technology enables the design of converters at higher frequencies and efficiencies than those achievable with conventional Si devices. This paper reviews the characteristics and commercial status of both vertical and lateral GaN power devices, providing the background necessary to understand the significance of these recent developments. In addition, the challenges encountered in GaN-based converter design are considered, such as the consequences of faster switching on gate driver design and board layout. Other issues include the unique reverse conduction behavior, dynamic Rds,on, breakdown mechanisms, thermal design, device availability, and reliability qualification. This review will help prepare the reader to effectively design GaN-based converters, as these devices become increasingly available on a commercial scale.

Gallium nitride (GaN) heterojunction field-effect transistors are an enabling technology for high-density converter design. This paper proposes a three-level dc-dc converter with dual outputs based on enhancement-mode GaN devices, intended for use as a battery charger in aircraft applications. The charger can output either 28 or 270 V, selected with a jumper, to satisfy the two most common dc bus voltage requirements in airplanes. It operates as an LLC converter in the 28 V mode and as a buck converter in the 270 V mode. In both operation modes, the devices can realize zero voltage switching (ZVS). With the chosen modulation method, the converter can realize automatic voltage balancing of the flying capacitor and the frequency doubling function to act as an interleaved converter. For the LLC mode, the resonant frequency is twice the switching frequency of primary-side switches, and for the buck mode, the frequency of the output inductor current is also twice the switching frequency. This helps to reduce the size of magnetics while maintaining a low switching loss. Also, the converter utilizes a matrix transformer, with resonant parameters designed to reduce conduction loss and avoid ZVS failure. The operating principle of the converter is analyzed and then experimentally verified on a 1.5-kW prototype with 1 MHz resonant frequency.

High power density is a desirable feature of power electronics design, which prompts economic incentives for industrial applications. In this paper, a gallium nitride (GaN)-based 2-kVA single-phase inverter design was developed for the Google Little Box Challenge, which achieves a 102-W/in3 power density. First, the static and dynamic temperature-dependent characteristics of multiple SiC and enhancement-mode GaN FETs are investigated and compared. Based on the device testing results, several topologies of the inverter stage and different power decoupling solutions are compared with respect to the device volume, efficiency, and thermal requirements. Moreover, some design approaches for magnetic devices and the implementation of gate drives for GaN devices are discussed in this paper, which enable a compact and robust system. Finally, a dc notch filter and a hard switching full-bridge converter are combined as the proposed design for the prototype. A 2-kVA prototype is demonstrated, which meets the volume, efficiency, and thermal requirements. The performance of the prototype is verified by the experimental results.

A hardware testbed platform emulating multiple-area power system scenario dynamics has been established aiming at multiple time-scale real-time emulations. In order to mimic real power flow situations in the utility system, the load emulators have to behave like real ones in both their static and dynamic characteristics. A constant-impedance, constant-current, and constant-power (ZIP) model has been used for static load types, while a three-phase induction motor model has been built to represent dynamic load types. In this paper, ways of modeling ZIP and induction motor loads and the performance of each load emulator are discussed. Comparisons between simulation and experimental results are shown as well for the validation of the emulator behaviors. A real-time composite power load emulator is then demonstrated with desired characteristics and detailed transients for representing a power system PQ bus dynamics.

This paper overviews the silicon carbide (SiC) technology. The focus is on the benefits of SiC based power electronics for converters and systems, as well as their ability in enabling new applications. The challenges and research trends on the design and application of SiC power electronics are also discussed.

Double pulse test (DPT) is a widely accepted method to evaluate the switching characteristics of semiconductor switches, including SiC devices. However, the observed switching performance of SiC devices in a PWM inverter for induction motor drives is almost always worse than the DPT characterization, with slower switching speed, more switching losses, and more serious parasitic ringing. This paper systematically investigates the factors that limit the SiC switching performance from both the motor side and inverter side, including the load characteristics of induction motor and power cable, two more phase legs for the three-phase PWM inverter in comparison with the DPT, and the parasitic capacitive coupling effect between power devices and heat sink. Based on a three-phase PWM inverter with 1200 V SiC MOSFETs, test results show that the induction motor, especially with a relatively long power cable, will significantly impact the switching performance, leading to a switching time increase by a factor of 2, switching loss increase up to 30% in comparison with that yielded from DPT, and serious parasitic ringing with 1.5 μs duration, which is more than 50 times of the corresponding switching time. In addition, the interactions among the three phase legs cannot be ignored unless the decoupling capacitors are mounted close to each phase leg to support the dc bus voltage during switching transients. Also, the coupling capacitance due to the heat sink equivalently increases the junction capacitance of power devices; however, its influence on the switching behavior in the motor drives is small considering the relatively large capacitance of the motor load.

This paper presents a board-level integrated silicon carbide (SiC) mosfet power module for high temperature and high power density application. Specifically, a silicon-on-insulator (SOI)-based gate driver capable of operating at 200 °C ambient temperature is designed and fabricated. The sourcing and sinking current capability of the gate driver are tested under various ambient temperatures. Also, a 1200 V/100 A SiC mosfet phase-leg power module is developed utilizing high temperature packaging technologies. The static characteristics, switching performance, and short-circuit behavior of the fabricated power module are fully evaluated at different temperatures. Moreover, a buck converter prototype composed of the SOI gate driver and SiC power module is built for high temperature continuous operation. The converter is operated at different switching frequencies up to 100 kHz, with its junction temperature monitored by a thermosensitive electrical parameter and compared with thermal simulation results. The experimental results from the continuous operation demonstrate the high temperature capability of the power module at a junction temperature greater than 225 °C.

This paper presents the analysis and control of a multilevel modular converter (MMC)-based HVDC transmission system under three possible single-line-to-ground fault conditions, with special focus on the investigation of their different fault characteristics. Considering positive-, negative-, and zero-sequence components in both arm voltages and currents, the generalized instantaneous power of a phase unit is derived theoretically according to the equivalent circuit model of the MMC under unbalanced conditions. Based on this model, a novel double-line frequency dc-voltage ripple suppression control is proposed. This controller, together with the negative- and zero-sequence current control, could enhance the overall fault-tolerant capability of the HVDC system without additional cost. To further improve the fault-tolerant capability, the operation performance of the HVDC system with and without single-phase switching is discussed and compared in detail. Simulation results from a three-phase MMC-HVDC system generated with MATLAB/Simulink are provided to support the theoretical analysis and proposed control schemes.

Featuring modularity and high efficiency, a modular multilevel converter (MMC) has become a promising topology in high-voltage direct-current transmission systems. However, its distributed capacitors lead to a more complicated startup process than that of a two-level converter. To fully understand this issue, the charging loops of an MMC rectifier and an MMC inverter during an uncontrolled precharge period are analyzed in this paper, with special focus on the necessity of additional capacitor charging schemes. Moreover, a small-signal model of a capacitor charging loop is first derived according to the internal dynamics of the MMC inverter. Based on this model, a novel startup strategy incorporating an averaging capacitor voltage loop and a feedforward control is proposed, which is capable of an enhanced dynamic response and system stability without sacrificing voltage control precision. The design considerations of the control strategy are also given in detail. Simulation results from a back-to-back MMC system supplying passive loads and experimental results from a scaled-down MMC prototype are provided to support the theoretical analysis and the proposed control scheme.

This paper presents the paralleling operation of three-phase current-source rectifiers (CSRs) as the front-end power conversion stage of data center power supply systems based on 400-Vdc power delivery architecture, which has been proven to have higher efficiency than traditional ac architectures. A control algorithm of paralleled three-phase CSRs is introduced to achieve balanced outputs and individual rectifier module hot swap, which are required by power supply systems. By using silicon carbide (SiC) power semiconductors, SiC MOSFETs, and Schottky diodes, the power losses of the front-end stage are reduced, and the power supply system efficiency can be further increased. The prototype of a 19-kW front-end rectifier to convert 480 Vac,rms to 400 Vdc, based on three paralleled three-phase CSRs, is developed. Each CSR is an all-SiC converter and designed for high efficiency, and the front-end stage full-load efficiency is greater than 98% from experimental tests. The balanced outputs and individual converter hot swap are realized in the hardware prototype too.

Current ripple is generated by pulse width modulation (PWM) switching in multiphase voltage source converters (VSCs). This letter introduces a general and fast current ripple prediction method for multiphase VSCs with arbitrary phase numbers. An equivalent converter-load model is derived for the n -phase converter system. By combining the common-mode voltage of both converter terminal and load, the equivalent circuit for each phase can be modeled. The voltage dropping on the ac inductor can be calculated for the 2 n + 2 zones in each switching cycle based on the equivalent circuit for each phase. Then the current ripple can be reconstructed based on the linear di/dt model in each zone. Simulation examples of five- and six-phase converters prove that the current prediction method is accurate. With this real-time prediction method, the current ripple can be controlled in application. An application example of five-phase variable switching frequency PWM is introduced to control the peak current ripple and reduce the switching losses.

An analytical model has been developed for predicting the forced-air cooling system performance, including a detailed optimization process to minimize the total weight. With a design example in a high-density high-temperature SiC converter, the presented design method was verified through numerical simulations and experiments.

The three-phase pulsewidth-modulation (PWM) converter is one of the most widely used topologies for power conversion. In order to design PWM methods, the influence of PWM methods on the current ripple is needed. This paper studies the current ripple of a three-phase PWM converter with general PWM methods for the design and control of this kind of converter. The current ripple is analyzed with eight different Thevenin equivalent circuits for the eight different voltage vectors. Then, the current-ripple slope and effective time could be achieved for every period. The current ripple could be predicted with both peak and rms values. Analytical predicted results show that discontinuous PWM could generate obviously bigger current ripples than space vector PMW for both peak and rms values with the same conditions. Simulation and experiments are built to verify the analytical results, proving that the theoretical prediction is valid. This analysis provides the basis for the design and control of the PWM method for converters.

A thermally integrated packaging structure for an all silicon carbide (SiC) power module was used to realize highly efficient cooling of power semiconductor devices through direct bonding of the power stage and a cold baseplate. The prototype power modules composed of SiC metal-oxide-semiconductor field-effect transistors and Schottky barrier diodes demonstrate significant improvements such as low-power losses and low-thermal resistance. Direct comparisons to their silicon counterparts, which are composed of insulated gate bipolar transistors and PiN diodes, as well as conventional thermal packaging, were experimentally performed. The advantages of this SiC module in efficiency and power density for power electronics systems have also been identified, with clarification of the SiC attributes and packaging advancements.

To further reduce system costs and package volumes of hybrid electric vehicles, it is important to optimize the power module and associated cooling system. This paper reports the thermal performance evaluation and analysis of three commercial power modules and a proposed planar module with different cooling system. Results show that power electronics can be better merged with the mechanical environment. Experiments and simulations were conducted to help further optimization.

A multilayer planar interconnection structure was used for the packaging of liquid-cooled automotive power modules. The power semiconductor switch dies are sandwiched between two symmetric substrates, providing planar electrical interconnections and insulation. Two minicoolers are directly bonded to the outside of these substrates, allowing double-sided, integrated cooling. The power switch dies are orientated in a face-up/face-down 3-D interconnection configuration to form a phase leg. The bonding areas between the dies and substrates, and the substrates and coolers are designed to use identical materials and are formed in one heating process. A special packaging process has been developed so that high-efficiency production can be implemented. Incorporating high-efficiency cooling and low-loss electrical interconnections allows dramatic improvements in systems' cost, and electrical conversion efficiency. These features are demonstrated in a planar bond-packaged prototype of a 200 A/1200 V phase-leg power module made of silicon (Si) insulated gate bipolar transistor and PiN diodes.

In a phase-leg configuration, the high-switching-speed performance of silicon carbide (SiC) devices is limited by the interaction between the upper and lower devices during the switching transient (crosstalk), leading to additional switching losses and overstress of the power devices. To utilize the full potential of fast SiC devices, this paper proposes two gate assist circuits to actively suppress crosstalk on the basis of the intrinsic properties of SiC power devices. One gate assist circuit employs an auxiliary transistor in series with a capacitor to mitigate crosstalk by gate loop impedance reduction. The other gate assist circuit consists of two auxiliary transistors with a diode to actively control the gate voltage for crosstalk elimination. Based on CREE CMF20120D SiC MOSFETs, the experimental results show that both active gate drivers are effective to suppress crosstalk, enabling turn-on switching losses reduction by up to 17%, and negative spurious gate voltage minimization without the penalty of decreasing the switching speed. Furthermore, both gate assist circuits, even without a negative isolated power supply, are more effective in improving the switching behavior of SiC devices in comparison to the conventional gate driver with a -2 V turn-off gate voltage. Accordingly, the proposed active gate assist circuits are simple, efficient, and cost-effective solutions for crosstalk suppression.

This paper presents an active gate driver (AGD) for IGBT modules to improve their overall performance under normal condition as well as fault condition. Specifically, during normal switching transients, a di/dt feedback controlled current source and current sink is introduced together with a push-pull buffer for dynamic gate current control. Compared to a conventional gate drive strategy, the proposed one has the capability of reducing the switching loss, delay time, and Miller plateau duration during turn-on and turn-off transient without sacrificing current and voltage stress. Under overcurrent condition, it provides a fast protection function for IGBT modules based on the evaluation of fault current level through the di/dt feedback signal. Moreover, the AGD features flexible protection modes, which overcomes the interruption of converter operation in the event of momentary short circuits. A step-down converter is built to evaluate the performance of the proposed driving schemes under various conditions, considering variation of turn-on/off gate resistance, current levels, and short-circuit fault types. Experimental results and detailed analysis are presented to verify the feasibility of the proposed approach.

This paper proposes a novel packaging method for insulated-gate bipolar transistor (IGBT) modules based on the concepts of P-cell and N-cell. The novel packaging reduces the stray inductance in the current commutation path in a phase-leg module and hence improves the switching behavior. A P-cell- and N-cell-based module and a conventional module are designed. Using finite-element-analysis-based Ansys Q3D Extractor, electromagnetic simulations are conducted to extract the stray inductance from the two modules. Two prototype phase-leg modules based on the two different designs are fabricated. The parasitics are measured using a precision impedance analyzer. Finally, a double pulse tester based-switching characterization is performed to illustrate the effect of stray inductance reduction in the proposed packaging design. The experimental results show the reduction in overshoot voltage with the proposed layout.

Overcurrent protection of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) remains a challenge due to lack of practical knowledge. This paper presents three overcurrent protection methods to improve the reliability and overall cost of SiC MOSFET-based converters. First, a solid-state circuit breaker (SSCB) composed primarily by a Si IGBT and a commercial gate driver IC is connected in series with the dc bus to detect and clear overcurrent faults. Second, the desaturation technique using a sensing diode to detect the drain-source voltage under overcurrent faults is implemented as well. Third, a novel active overcurrent protection scheme through dynamic evaluation of fault current level is proposed. The design considerations and potential issues of the protection methods are described and analyzed in detail. A phase-leg configuration-based step-down converter is built to evaluate the performance of the protection schemes under various conditions, considering variation of fault type, decoupling capacitance, protection circuit parameters, etc. Finally, a comparison is made in terms of fault response time, temperature-dependent characteristics, and applications to help designers select a proper protection method.

This paper presents a novel hybrid output filter topology for the inverter-motor system. It is shown that the proposed filter drastically reduces the common mode (CM) voltage at the motor terminals. The proposed filter is composed of a conventional LC filter cascaded with an active motor CM impedance regulator. The active circuit, utilizing an integrated high-voltage op-amp, is very efficient in decreasing the motor CM equivalent capacitance, as well as damping the high common voltage on the motor terminal. Therefore, the motor impedance is also used as part of the filter, and the common voltage can be eliminated dynamically in the active impedance regulator by feedback control. Furthermore, the size of the passive filter can be reduced to a large extent. Experimental verification of the filter topology is provided with a laboratory system consisting of a 380-V inverter and a 0.37-kW induction motor.

High-temperature (HT) converters have gained importance in industrial applications where the converters operate in a harsh environment, such as in hybrid electrical vehicles, aviation, and deep-earth petroleum exploration. These environments require the converter to have not only HT semiconductor devices (made of SiC or GaN), but also reliable HT packaging, HT gate drives, and HT control electronics. This paper describes a detailed design process for an HT SiC three-phase PWM rectifier that can operate at ambient temperatures above 100°C. SiC HT planar structure packaging is designed for the main semiconductor devices, and an edge-triggered HT gate drive is also proposed to drive the designed power module. The system is designed to make use of available HT components, including the passive components, silicon-on-insulator chips, and auxiliary components. Finally, a 1.4 kW lab prototype is tested in a harsh environment for verification.

Compared with the widely used constant switching frequency pulse-width-modulation (PWM) method, variable switching frequency PWM can benefit more because of the extra freedom. Based on the analytical expression of current ripple of three-phase converters, variable switching frequency control methods are proposed to satisfy different ripple requirements. Switching cycle Ts is updated in DSP in every interruption period based on the ripple requirement. Two methods are discussed in this paper. The first method is designed to arrange the current ripple peak value within a certain value and can reduce the equivalent switching frequency and electromagnetic interference (EMI) noise; the second method is designed to keep ripple current RMS value constant and reduce the EMI noise. Simulation and experimental results show that variable switching frequency control could improve the performance of EMI and efficiency without impairing the power quality.

In this paper, a fully integrated silicon carbide (SiC)-based six-pack power module is designed and developed. With 1200-V, 100-A module rating, each switching element is composed of four paralleled SiC junction gate field-effect transistors (JFETs) with two antiparallel SiC Schottky barrier diodes. The stability of the module assembly processes is confirmed with 1000 cycles of -40°C to +200°C thermal shock tests with 1.3°C/s temperature change. The static characteristics of the module are evaluated and the results show 55 mΩ on-state resistance of the phase leg at 200°C junction temperature. For switching performances, the experiments demonstrate that while utilizing a 650-V voltage and 60-A current, the module switching loss decreases as the junction temperature increases up to 150°C. The test setup over a large temperature range is also described. Meanwhile, the shoot-through influenced by the SiC JFET internal capacitance as well as package parasitic inductances are discussed. Additionally, a liquid cooled three-phase inverter with 22.9 cm × 22.4 cm × 7.1 cm volume and 3.53-kg weight, based on this power module, is designed and developed for electric vehicle and hybrid electric vehicle applications. A conversion efficiency of 98.5% is achieved at 10 kHz switching frequency at 5 kW output power. The inverter is evaluated with coolant temperature up to 95°C successfully.

The low power losses of silicon carbide (SiC) devices provide new opportunities to implement an ultra high-efficiency front-end rectifier for data center power supplies based on a 400-Vdc power distribution architecture, which requires high conversion efficiency in each power conversion stage. This paper presents a 7.5-kW high-efficiency three-phase buck rectifier with 480-Vac,rms input line-to-line voltage and 400-Vdc output voltage using SiC MOSFETs and Schottky diodes. To estimate power devices' losses, which are the dominant portion of total loss, the method of device evaluation and loss calculation is proposed based on a current source topology. This method simulates the current commutation process and estimates devices' losses during switching transients considering devices with and without switching actions in buck rectifier operation. Moreover, the power losses of buck rectifiers based on different combinations of 1200-V power devices are compared. The investigation and comparison demonstrate the benefits of each combination, and the lowest total loss in the all-SiC rectifier is clearly shown. A 7.5-kW prototype of the all-SiC three-phase buck rectifier using liquid cooling is fabricated and tested, with filter design and switching frequency chosen based on loss minimization. A full-load efficiency value greater than 98.5% is achieved.

This article presents the development and experimental performance of a 10-W, all-silicon carbide (SiC), 250 °C junction temperature, high-powerdensity, three-phase ac-dc-ac converter. The electromagnetic interference filter, thermal system, high-temperature package, and gate drive design are discussed in detail. Tests confirming the feasibility and validating the theoretical basis of the prototype converter system are described. Over the last 20 years, advances in industrial and research efforts in electronic power conversion have steadily been moving toward higher power densities, which has resulted in improvements in converter system performance; reductions in physical size; and reductions in mass, weight, and cost. However, this pushes the limits of the existing control, packaging, and thermal management technology for power converter systems.

A Si insulated-gate bipolar transistor (IGBT) phase-leg module is developed for operating at 200°C in hybrid electric vehicle applications utilizing the high temperature packaging technologies and appropriate thermal management. The static and switching electrical characteristics of the fabricated power module are tested at various temperatures, showing that the module can operate reliably with increased but acceptable losses at 200°C. The criterion on thermal performance is given to prevent thermal runaway caused by fast increase of the leakage current during a high temperature operation. Afterward, the thermal management system is designed to meet the criterion, the performance of which is evaluated with experiment. Furthermore, two temperature-sensitive electrical parameters, on-state voltage drop and the switching time, are employed for thermal impedance characterization and the junction temperature measurement during converter operation, respectively. Finally, a 10-kW buck converter prototype composed of the module assembly is built and operated at the junction temperature up to 200°C. The experimental results demonstrate the feasibility of operating Si device-based converters continuously at 200°C.

This paper presents a reliability-oriented design (ROD) procedure for three-phase power converters in aircraft applications. These require the highest reliability levels for all its components-as high as space applications; hence the need to maximize the reliability of three-phase power converters, which are in increasing demand and use in commercial and military aircrafts as a result of the more-electric aircraft (MEA) initiative. Specifically, the proposed procedure takes reliability up-front in the design process of power converters, carrying out the design in three steps. First, the identification of critical system components; second, the assessment of reliability factors such as risk analysis, failure mode analysis, and fishbone diagrams; and third, the actual design, which is carried out by minimizing system complexity and stress, and by the use of the most reliable components, materials, and structures. To this end, reliability models were developed for all critical components based on the military handbook MIL-HDBK-217F, and field and vendor data. For verification purposes, the paper includes the ROD of a 60 kW three-phase power converter for aircraft applications together with experimental results of the prototype constructed.

This paper presents a complete design methodology for the sensorless vector control of permanent-magnet synchronous machine (PMSM) motor drives in fan-type applications. The proposed strategy is built over a linear asymptotic state observer used to estimate the PMSM back EMF and a novel tracking controller based on a phase-locked loop system, which, by synchronizing the estimated and actual d-q frames, estimates the rotor speed and position. This paper presents the complete derivation of all associated control loops, namely, state observer; tracking controller; d-q-axis current regulator; speed controller; an antisaturation control loop, which provides inherent operation in the flux-weakening region; and all corresponding antiwindup loops. Detailed design rules are provided for each of these loops, respectively verified through time-domain simulations, frequency-response analysis, and experimental results using a three-phase 7.5-kW PMSM motor drive, validating both the design methodology and the expected performance attained by the proposed control strategy.

This paper presents a control method to minimize the total flux in the integrated interphase inductors of paralleled, interleaved three-phase two-level voltage-source converters (VSCs) using discontinuous space vector modulation (DPWM). Specifically, different inductor structures used to limit circulating currents are introduced and compared, and the structure and flux distribution of two types of integrated interphase inductors are analyzed in detail. Based on that, a control method to minimize the total flux in such integrated interphase inductor is proposed for a parallel converter system using interleaved DPWM. The method eliminates the circulating currents during the peak range of the converter output currents; hence the total flux is minimized and only determined by the system load requirements. This control method introduces very limited additional switching actions, which do not significantly affect the converter electrothermal design. Experimental results verify the analysis and the feasibility of the proposed control method.

Robust system control design and seamless transition between various modes of operation are paramount for multifunctional converters in microgrid systems. This paper proposes a control system for single-phase bidirectional PWM converters for residential power level microgrid systems which is robust and can tolerate transitions between the different modes of operation. This is achieved by means of a common inner ac current-loop. Each of the operating modes has an individually designed outer loop performing the corresponding regulation tasks, most commonly including the ac voltage and the dc voltage regulation. A modified , phase-locked loop (PLL) system is used for system-level operation with both small steady-state error and fast response; and a novel islanding detection algorithm based on PLL stability is proposed to facilitate the transition between grid-connected mode and stand-alone mode. Finally, a frequency-response based design procedure for the proposed control system is presented in detail for all operating modes, and its performance is verified experimentally using a DSP-controlled 6 kW 120 V rms (ac)/ 300 V (dc) laboratory converter prototype.

Fault detection and protection is an important design aspect for any power converter, especially in high-power high-voltage applications, where cost of failure can be high. The three-level dc-dc converter and its varied derivatives are attractive topologies in high-voltage high-power converter applications. The protection method can not only prevent the system failure against unbalanced voltage stresses on the switches, but also provide a remedy for the system as faults occur and save the remaining components. The three-level converter is subject to voltage unbalance in certain abnormal conditions, which can result in switch overvoltage and system failure. The reasons for the unbalanced voltage stresses are fully investigated and categorized. The solutions to each abnormal condition are introduced. In addition to the voltage unbalance, the three-level converters can be protected against multiple faults by the proposed protection method through monitoring the flying capacitor voltage. Phenomena associated with each fault are thoroughly analyzed and summarized. The protection circuit is simple and can be easily implemented, while it can effectively protect the three-level converters and its derivatives, which has been verified by the experiment with a three-level parallel resonant converter.

To take full advantage of silicon carbide semiconductor devices, high-temperature device packaging needs to be developed. This paper describes potential defects from design and fabrication procedures, and presents a systematic electrical evaluation process to detect such defects. This systematic testing procedure can rapidly detect many defects and reduce the risk in high-temperature packaging testing. A multichip module development procedure that uses this testing procedure is also presented and demonstrated with an example.

It is well known that single-phase pulse width modulation rectifiers have second-order harmonic currents and corresponding ripple voltages on the dc bus. The low-frequency harmonic current is normally filtered using a bulk capacitor in the bus, which results in low power density. However, pursuing high power density in converter design is a very important goal in the aerospace applications. This paper studies methods for reducing the energy storage capacitor for single-phase rectifiers. The minimum ripple energy storage requirement is derived independently of a specific topology. Based on the minimum ripple energy requirement, the feasibility of the active capacitor's reduction schemes is verified. Then, we propose a bidirectional buck-boost converter as the ripple energy storage circuit, which can effectively reduce the energy storage capacitance. The analysis and design are validated by simulation and experimental results.

This paper presents a control method to limit the common-mode (CM) circulating current between paralleled three-phase two-level voltage-source converters (VSCs) with discontinuous space-vector pulsewidth modulation (DPWM) and interleaved switching cycles. This CM circulating current can be separated into two separate components based on their frequency; the high-frequency component, close to the switching frequency, can be effectively limited by means of passive components; the low-frequency component, close to the fundamental frequency, embodies the jumping CM circulating current observed in parallel VSCs. This is the main reason why it is usually recommended not to implement discontinuous and interleaving PWM together. The origin of this low-frequency circulating current is analyzed in detail, and based on this, a method to eliminate its presence is proposed by impeding the simultaneous use of different zero vectors between the converters. This control method only requires six additional switching actions per line cycle, presenting a minimum impact on the converter thermal design. The analysis and the feasibility of the control method are verified by simulation and experimental results.

A crucial component of grid-connected converters is the phase-locked loop (PLL) control subsystem that tracks the grid voltage's frequency and phase angle. Therefore, accurate fast-responding PLLs for control and protection purposes are required to provide these measurements. This paper proposes a novel feedback mechanism for single-phase PLL phase detectors using the estimated phase angle. Ripple noise appearing in the estimated frequency, most commonly the second harmonic under phase-lock conditions, is reduced or eliminated without the use of low-pass filters, which can cause delays to occur and limits the overall performance of the PLL response to dynamic changes in the system. The proposed method has the capability to eliminate the noise ripple entirely and, under extreme line distortion conditions, can reduce the ripple by at least half. Other modifications implemented through frequency feedback are shown to decrease the settling time of the PLL up to 50%. Mathematical analyses with the simulated and experimental results are provided to confirm the validity of the proposed methods.

The problem of electromagnetic interference (EMI) plays an important role in the design of power electronic converters, especially for airplane electrical systems. This paper explores techniques to reduce EMI noise in three-phase active front-end rectifier. The Vienna-type rectifier is used as the object. The design approach introduced in this paper is using a high-density EMI filter to satisfy the EMI standard. Design methodology is introduced in the paper by a three-stage LC- LC-L filter structure. In particular, the cause of high noise at high frequencies is studied in experiments, and the coupling effect of the final-stage capacitor and inductors is investigated. In order to reduce the EMI noise in the mid-frequency range, the application of random pulsewidth modulation (PWM) is also presented. The performance of random PWM in a Vienna-type rectifier is verified by theoretical analysis and experimental results. The approaches discussed in this paper significantly reduce the EMI noise in the Vienna-type rectifier, and therefore, the filter size can also be reduced.

This paper comprehensively investigates and compares different multiloop linear control schemes for single-phase pulsewidth modulation inverters, both in stationary and synchronous (d -q) frames, by focusing on their steady-state error under different loading conditions. Specifically, it is shown how proportional plus resonant (P + R) control and load current feedback (LCF) control can, respectively, improve the steady-state and transient performance of the inverter, leading to the proposal of a PID + R + LCF control scheme. Furthermore, the LCF control and capacitive current feedback control schemes are shown to be subject to stability issues under second and higher order filter loads. Additionally, the equivalence between the stationary frame and d -q frame controllers is discussed depending on the orthogonal term generation method, and a d-q frame voltage control strategy is proposed eliminating the need for the generation of this orthogonal component. This is achieved while retaining all the advantages of operating in the synchronous d-q frame, i.e., zero steady-state error and ease of implementation. All theoretical findings are validated experimentally using a 1.5 kW laboratory prototype.

The SiC JFET is an attractive semiconductor device due to its superior switching performance and high-temperature operating capability. Its shoot-through protection remains a challenge due to the limited practical knowledge existent on this device and due to its inherent normally on nature. Addressing this limitation, this paper presents a novel shoot-through protection scheme in which a bidirectional switch, compounded by a Si insulated-gate bipolar transistor (IGBT) and a relay,is embedded into the dc-link midpoint in order to detect and clear shoot-through faults, taking advantage of the well-known desaturation protection schemes of IGBTs to protect SiC JFETs. This paper describes in detail the proposed protection mechanism and its circuit design, presenting as well the experimental results that verified the effectiveness of the proposed scheme using, first, Si MOSFETs and second, a 10-kW ac-ac converter system using SiC JFETs.

This article presents the development and experimental performance of a 10-kW high-power-density three-phase ac-dc-ac converter. The converter consists of a Vienna-type rectifier front end and a two-level voltage source inverter (VSΓ)To reduce the switching loss and achieve a high operating junction temperature, the SiC JFET and SiC Schottky diode are used. Design considerations for the phase-leg units, gate drivers, integrated input filter-combining electromagnetic interference (EMI) and boost inductor stages-and the system protection are described in full detail. Experiments are carried out under different operating conditions, and the results obtained verify the performance and feasibility of the proposed converter system.

Common-mode (CM) choke saturation is a practical problem in CM filter applications. It is generally believed that the leakage inductance of CM chokes makes the core saturated. This paper analyzes two new mechanisms for CM choke saturation due to CM voltage, and these mechanisms are verified in experiment. CM choke saturation is particularly important for motor drive systems, which have a high CM voltage and comparably higher stray grounding capacitance. A model is established to describe the relationship between the CM voltage and the volume of the CM magnetic components. According to the analysis, line impedance stabilization networks (LISNs) play an important role in the design of CM magnetic components.

This paper presents the design, development, and testing of a phase-leg power module packaged by a novel planar packaging technique for high-temperature (250°C) operation. The nanosilver paste is chosen as the die-attach material as well as playing the key functions of electrically connecting the devices' pads. The electrical characteristics of the SiC-based power semiconductors, SiC JFETs, and SiC Schottky diodes have been measured and compared before and after packaging. No significant changes (<;5%) are found in the characteristics of all the devices. Prototype module is fabricated and operated up to 400 V, 1.4 kW at junction temperature of 250°C in the continuous power test. Thermomechanical robustness has also been investigated by passive thermal cycling of the module from -55°C to 250°C. Electrical and mechanical performances of the packaged module are characterized and considered to be reliable for at least 200 cycles.

High-frequency common-mode (CM) electromagnetic-interference (EMI) noise is difficult to suppress in electronics systems. EMI filters are used to suppress CM noise, but their performance is greatly affected by the parasitic effects of the grounding paths. In this paper, the parasitic effects of the grounding paths on an EMI filter's performance are investigated in a motor-drive system. The effects of the mutual inductance between two grounding paths are explored. Guidelines for the grounding of CM EMI filters are derived. Simulations and experiments are finally carried out to verify the theoretical analysis.

Terminal models have been used for various applications. In this paper, a three-terminal model is proposed for electromagnetic-interference (EMI) characterization. The model starts with a power electronic system at a particular operating condition and creates a unique linearized equivalent circuit. Impedances and current/voltage sources define the noise throughout the entire EMI frequency spectrum. All parameters needed to create the model are clearly defined to ensure convergence and maximize accuracy. In addition, the accuracy of the model is confirmed up to 100 MHz for a dc-dc boost converter using both simulation and experimental validation.

This letter presents a novel integration approach for the electromagnetic interference choke. A low-permeability differential-mode (DM) choke is placed within the open window of the common-mode (CM) choke. Both chokes share the same winding structure. With the proposed approach, the footprint of inductors is greatly reduced, and high-DM inductance can be achieved. First, small-signal measurement is carried out to demonstrate the design concept and the symmetry of the proposed structure. Then large-signal experimental results verify the attenuation characteristics, as well as the thermal performance.

This paper begins with an analysis of the common-mode (CM) noise in a motor drive system. Based on the developed CM noise model, two cancellation techniques, CM noise voltage cancellation and CM noise current cancellation, are discussed. The constraints and impedance requirements for these two cancellation methods are investigated. An active filter with a feedforward current cancellation technique is proposed, implemented, and tested, and techniques to improve the performance of active filters are explored. It is found that due to the limitations of speed, power loss, and gain bandwidth of active filters, active electromagnetic interference (EMI) filters are not good at suppressing high di/dt or high amplitude noise current. Hybrid filters that include a passive filter and an active filter are proposed to overcome the shortcomings of active filters. Hybrid EMI filters are investigated based on the impedance requirements and frequency responses between the passive and active filters. The experiments show that the proposed active filter can greatly reduce noise by up to 50 dB at low frequencies (LFs), and therefore, the corner frequency of the passive filter can be increased considerably; as a result, the CM inductance of the passive filter is greatly reduced. The power loss of the proposed active EMI filter can be well-controlled in the experiments.

This paper presents strategies to reduce both differential-mode (DM) and common-mode (CM) noise using a passive filter in a dc-fed motor drive. The paper concentrates on the type of grounding and the components to optimize filter size and performance. Grounding schemes, material comparison between ferrite and nanocrystalline cores, and a new integrated filter structure are presented. The integrated structure maximizes the core window area and increases the leakage inductance by integrating both CM and DM inductances onto one core. Small-signal and large-signal experiments validate the structure, showing it to have reduced filter size and good filtering performance when compared with standard filters at both low and high frequencies.

This paper presents a comprehensive analysis studying the impact of interleaving on harmonic currents and voltages on the ac side of paralleled three-phase voltage-source converters. The analysis performed considers the effects of modulation index, pulsewidth-modulation (PWM) schemes, and interleaving angle. Based on the analysis, the impact of interleaving on the design of ac passive components, such as ac line inductor and electromagnetic interference (EMI) filter, is discussed. The results show that interleaving has the potential benefit to reduce ac passive components. To maximize such a benefit, the interleaving angle should be optimized according to the system requirements, including total harmonic distortion limit, ripple limit, or EMI standards, while considering operating conditions, such as modulation index and PWM schemes. Experimental results have verified the analysis results.

In order to help device selection and optimal application in high-power-density converter designs, a new power semiconductor device figure of merit (FOM)-power density FOM-is proposed, with consideration of power device conduction and switching losses, thermal characteristics, and package. The FOM is derived based on the device theory, and its validity and usefulness are demonstrated with a practical design example.

This paper proposes a variable-frequency zero-voltage-switching (ZVS) three-level LCC resonant converter that is able to utilize the parasitic components of the high turns-ratio transformer. By applying a three-level structure to the primary side, the voltage stress of the primary switches is half of the input voltage. Low-voltage MOSFETs with better performance can be used in this converter, and zero-current-switching (ZCS) is achieved for rectifier diodes. By applying a magnetic integration technique, only one magnetic component is required in this converter. The power factor concept of resonant converters is proposed and analyzed, and a novel constant power-factor control scheme is proposed. Based on this control strategy, the circulating energy of resonant converters is considerably reduced. High efficiency can be obtained for high-voltage high-power charging applications. The operation principle of the converter is analyzed and verified on a 700-kHz, 3.7-kW prototype, with which a power density of 72 W/inch3 is achieved.

This paper investigates low-frequency beat and harmonics in grid-connected three-level pulsewidth-modulated (PWM) voltage-source converters with low switching frequencies. The impact of switching frequencies and switching sequence, as well as mitigation techniques, are studied. Different from some recent results, the analysis confirms the advantages of selecting switching frequency, as an odd-triplen multiple of the grid operating frequency, for eliminating imbalance and undesirable even-order harmonics, which can negatively impact the dc-link neutral-point balance in a three-level converter. Tests and analysis show that low-frequency subharmonic beat can occur in a carrier-based PWM converter when the switching frequency is low and is an imperfect multiple of the grid frequency. Recognizing the beat as interaction of the switching sequence and switching frequency, mitigation techniques to reduce the beat and associated harmonics are investigated and verified through experiments. A simple displacement of switching frequency from the odd-triplen multiple of the grid frequency can effectively suppress the beat with an asynchronous PWM scheme.

This paper presents a new frequency-domain method for predicting conducted electromagnetic-interference (EMI) noise in AC switching power converters whose switching conditions vary during an operating period. Based on an equivalent modular-terminal-behavioral (MTB) frequency-domain EMI source model developed for one switching period at a given operating point, the proposed approach superposes MTB models for different operating zones in the frequency domain to predict EMI noise for the entire operating period. Compared with the various existing modeling approaches, including physics-based or behavioral time-domain and frequency-domain methods, the proposed method is efficient, accurate, and more suitable for the system-level EMI study. The use of the methodology for both differential-mode and common-mode EMI-noise prediction is investigated. Verification was carried out through simulations and experiments using a half-bridge AC converter. This modular modeling approach can be applied to many other types of converters, including three-phase pulse-width-modulation inverters, as well as converters with different switching control schemes.

Negative-sequence (NS) current sharing among different grid-forming (GFM) sources is a critical issue in islanded microgrids (MGs). Existing sharing strategies only focus on the NS current distribution among inverter-based resources (IBRs). However, existing approaches have not fully considered the NS current sharing among IBRs and SGs and are easily affected by line impedances. In this paper, a leader-follower-based approach is proposed for the NS current sharing among IBRs and SGs. The leader IBR, attempting to regulate the bus NS voltage to zero, generates the total NS current references. The NS current references are distributed to follower IBRs. After the IBRs’ NS currents track the references, the SGs’ NS currents is subsequently determined. The proposed control strategy is verified through both simulation and experimental testing on a converter-based hardware testbed.

The 10-kV SiC device imposes high insulation requirements on the corresponding power stage design. As the voltage stress and clearance distance increases, achieving a compact design of the converter will be challenging. In this paper, a compact power stage design is realized by adopting a new heatsink configuration. With the new heatsink configuration, a field shaping structure is proposed to suppress concentrated electric field close to the edges, so that the clearance between heatsinks can be reduced. Simulation and experimental tests have validated the design. The proposed design has been tested up to 6250 V/10 A, and the gate drive and bus-bar design are also discussed in this paper.

To dissipate heat effectively, a sufficient cooling system is required for a five-level MMC (Modular Multilevel Converter) based on 10 kV, 100 A power modules. However, achieving efficient heat dissipation necessitates a large cooling system, which in turn reduces the overall power density of the converter. Additionally, ensuring proper insulation between the high voltage switching devices and cooling components poses another challenge. This paper addresses these issues by presenting a detailed numerical design procedure for liquid cooling and selecting appropriate coolant with high dielectric strength. Air cooling with specific clearance and creepage distances is also presented. These two types of cooling methods are compared in terms of thermal performance, size, cost and installation effort. The effectiveness of the design is validated through experimental measurements.

This paper presents the design of a megawatts (MW) level modular multilevel converter (MMC) phase-leg for 13.8 kV medium voltage (MV) grid based on Wolfspeed 10 kV SiC MOSFET XHV-9 half bridge module. Compared with the 10 kV SiC single die discrete device, the 10 kV SiC multi-die module has higher di/dt, higher dv/dt (for loss reduction), and more stringent protection requirement, posing new challenges on the MW-level MV power converter design based on this 10 kV SiC module. Detailed MMC submodule and system design to address these challenges are presented. A protection strategy for this 10 kV SiC MOSFET power module is proposed, which can detect the short circuit within 200 ns and effectively limit short circuit current to within 200 A for short circuit fault at 6 kV dc voltage. Hardware is built and experimental results of the MMC submodule test at 6 kV dc voltage, MMC phase-leg test at 12 kV dc voltage, and 8-level converter test up to 23 kV are demonstrated and verify the effectiveness of the presented design.

This paper presents the switching cell design for medium voltage (MV) flying capacitor converter (FCC) with emerging 10 kV SiC MOSFET using a 5-level FCC for the 13.8 kV MV grid as an example. The design of flying capacitors and decoupling capacitors to achieve compact size, loop inductance minimization, high voltage insulation, and good scalability is discussed. The flying capacitor switching cell double pulse test (FCC-DPT) concept is proposed for switching evaluation. With detailed switching loop characterization and analysis, the switching speed of this 10 kV 20 A SiC MOSFET discrete device is pushed to exceed 100 V/ns. Hardware of the 5L-FCC phaseleg is built and continuous power test experimental results up to 23 kV dc voltage are demonstrated.

As the enabler of the direct current (DC) power distribution system, DC solid-state circuit breaker (DC-SSCB) has been extensively studied at the breaker-level (e.g., topology, energy absorption circuit, gate driver, and control) with limited system-level considerations, which is also crucial. This paper provides an all-in-one solution with integrated circuitries as the fault detector, actuator for semiconductor’s operating status regulation, and coordinated control to seamlessly transition from one mode to another (e.g., normal mode, precaution mode, i2t mode, and interruption mode). This allows the developed SSCB to limit system fault current not exceeding short-circuit current rating (SCCR) and take different responses under different fault cases. First, two improved fault detection circuits are introduced to better serve the SSCB application. Second, four operation modes are proposed for SSCB to realize system-friendly functions. Third, by leveraging four different operation modes, a control strategy is demonstrated to take different actions based on different fault cases. Finally, the feasibility and the effectiveness of the proposed system-friendly 200V/10A SSCB is validated with experimental results.

Existing Rogowski coil sensors suffer from insufficient measurement bandwidth, which limits their ability to accurately capture the switching transient current of wide-bandgap devices. A combination Rogowski coil is proposed to extend the overall measurement bandwidth to address this limitation. This concept involves combining the self-integrating region of a shielded Rogowski coil with its differentiating region. The selection of suitable geometrical parameters is crucial as it directly affects the measuring performance, including bandwidth and sensitivity. This paper explores the methodology of employing a multi-objective optimization workflow to design Printed Circuit Board (PCB) shielded Rogowski Coils. Eight geometrical parameters are considered as design variables to maximize the objective functions. Utilizing the distributed model of the shielded PCB Rogowski coil, the geometry of the PCB shielded Rogowski coil is optimized using JMP. The factors that have a significant impact on bandwidth and sensitivity are identified through the optimization process. To validate the proposed optimized approach, an optimized current sensor is designed, prototyped, and tested. A comparison is made between the optimized design and state-of-the-art alternatives to assess its performance.

Gallium Nitride (GaN) high electron mobility transistors (HEMTs) are superior for cryogenically cooled solid-state circuit breakers (SSCBs) in future aircraft applications owing to their low on-resistance and high saturation current. However, during the high current turn-off, it is found that potential voltage and current ringing could happen to damage the device. In this paper, the turn-off failure mechanism of 650V/ 150A GaN bare dies are analyzed, which could be due to the instability of paralleled switching cells in one GaN bare die. A solution is proposed to use an RC snubber to reduce the overlap of $v_{ds}$ and $i_{d}$ in the turn-off process to avoid the unstable region where the hard-switching trajectory goes through. Experiments are conducted to verify the effectiveness of the proposed solution. With the reduced overlap between $v_{ds}$ and $i_{d}$, the GaN HEMT successfully turns off the 550 A objective current.

Operating power converters at cryogenic temperature (<-153°C) can improve efficiency and power density. However, the reliable operation of power converters depends on satisfactory performance of all critical components at cryogenic temperature. While most of the critical components have been studied at cryogenic temperatures, some electronic components necessary for electrical isolation in signal circuits of a medium voltage power converter are yet to be evaluated extensively. This work studies the cryogenic performance of isolated auxiliary power supplies (APS), digital isolators, fiber optics, and isolation amplifiers to identify the well-performing candidates and to investigate the possible reason of failures at cryogenic temperatures. It is observed that some isolated APS with high isolation voltage and isolation amplifiers can work satisfactorily at cryogenic temperatures. The digital isolators are found to be more suitable for cryogenic operation than fiber optic links, even though the latter has better noise immunity.

To increase the current interrupting capability for the DC solid-state circuit breaker (DC-SSCB), power semiconductors need to possess a higher pulse current. Moreover, for the power electronics protection system, it is also important to enable the system with a fault current limitation capability. Accordingly, this paper aims to design an intelligent gate drive for DC-SSCB, which can operate in cryogenic conditions to increase interrupting capability of the SSCB. Meanwhile, the proposed intelligent gate drive also enables the SSCB to operate in the current limitation mode to limit the overcurrent in the aviation system. The current limitation mode can help the aviation system limit the inrush current during startup and realize fault ride-through for the healthy part when the fault occurs. Finally, test results based on a 200V/150A SSCB with the current limitation mode prototype verify the proposed intelligent gate drive design for SSCB with cryogenic cooling.

The significant on-resistance reduction, the faster switching speed, and the capability of being operated at a higher current at cryogenic temperature make Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) attractive to cryogenically cooled power electronics applications. Moreover, the positive temperature coefficient of on-resistance makes GaN HEMTs suitable for the parallel operation. In this article, the design of a solid-state circuit breaker (SSCB) with two 650V/150A GaN HEMTs in parallel is presented. The designed SSCB circuit is tested at cryogenic temperature (<-153°C). -The results demonstrate the capability of the SSCB module with paralleled GaN-HEMTs to interrupt high current (1000A) at cryogenic temperature.

Asynchronous microgrid (ASMG) with a power conditioning system (PCS) is a promising solution for future microgrids (MGs). High voltage (HV, >3.3 kV) SiC device-based PCS is becoming more and more popular in the ASMG PCS implementation. PCS with HV SiC MOSFETs can realize higher control frequencies with lower losses to bring numerous system-level benefits, which have not been fully investigated in the existing literature. In this paper, the active power filtering (APF) capability of the HV SiC-based PCS for both grid and MG power quality improvement is discussed and demonstrated. A harmonic impedance-based APF algorithm is proposed for MG-side PCS. The PCS APF functions are demonstrated on a 10 kV SiC MOSFET-based PCS prototype with the modular multi-level converter (MMC) topology to 19th-order harmonic currents.

The global carbon footprint from the aviation sector is seeing a steep increase in the past half-century. To combat this challenge, electrifying the aircraft is a promising solution. Howbeit, the idea of aircraft electrification is introducing various dc power distribution architectures, increasing the complexity of aircraft electric power systems (EPS). The aircraft EPS is of low voltage and makes the system handle huge currents. Alongside this, the next-generation aircraft power system demands faster and more reliable protection. Solid-state circuit breakers (SSCBs) offer fast fault interruption capability and make the protection system compact. This article proposes a modified Q-Z-source (MQZSCB) dc circuit breaker (DCCB) topology that employs a thyristor as the main fault-interrupting device and uses a coupled inductor for its commutation during faults. Also, it employs fewer components, thereby reducing the weight/volume of the system, which benefits the design aspects of the aircraft. The proposed topology can interrupt the fault approximately within $400\mu {\mathrm{s}}$. Moreover, this topology is advantageous to the existing QZSCB by mitigating the issues of negative current flow through the load, especially during reclosing, and unwanted power flow to the load during the QZSCB commissioning. The proposed solution also enables reduced current stress on the thyristor during reclosing. A prototype rated at 270V/10A has been developed to address the issues and validate the performance of the proposed MQZSCB.

In this paper, an 850 V dc to 13.8 kV ac 100 kW modular multilevel three-phase four-wire dc/ac converter based on 10 kV SiC MOSFETs is designed and demonstrated. The design considerations of key components, including the dc-link, device cooling, gate driver, isolated gate driver power supply (GDPS), medium voltage (MV) ac filter inductor, MV and medium frequency transformer, and the mechanical design are discussed. Two converters are designed, and two prototypes are developed, to study the converter paralleling operation and scalability. Both converters are fully tested up to their voltage and power ratings. However, the two converters are not identical. Based on the design and test results of the first converter, the MV power stage, transformer design, GDPS, as well as the low voltage power stage in the second converter are improved for smaller size and/or higher efficiency. Compared to the version 1 converter, the version 2 converter achieves 49% volume reduction and 2 percentage point efficiency improvement, with a peak efficiency of 98.4% at the rated power.

High penetration of inverter-based resources (IBRs) in the grid increases the need for them to provide similar grid support functions as traditional synchronous generators (SGs). The virtual synchronous generator (VSG) is an effective approach to controlling IBRs to behave like SGs. However, previous VSG IBRs, with their limited inverter overcurrent capability, cannot mimic the SGs during faults and other high current transient conditions. As a result, these IBRs cannot provide the same level of voltage support, black start, protection, and transient stability as traditional SGs. This paper realizes the VSG inverter with overcurrent and fault handling capability so that it provides grid support as the SG even during grid transients. The 6th-order SG model is adopted considering the sub-transient performance, and the inverter control is discussed. The implementation is fully tested with both simulation and experiment in different fault types (balanced and unbalanced) and fault impedances. The results show that with the 6th-order model and control, the VSG inverter can perform the same as the SG even during grid faults. This verifies that VSG IBRs can provide grid support as the SG even during grid faults.

This paper, to the best knowledge of the authors, for the first time reports the packaging of a 100kW three-level active neutral point clamped (3L-ANPC) phase leg power module for electric vehicle (EV) traction inverter applications using 650V/150A e-mode gallium nitride high-electron-mobility transistors (GaN HEMTs). Compared with two-level (2L) half bridge power module, the main challenges of packaging a 3L-ANPC phase leg power module are high number of switches (6 switches vs 2 switches) and multiple commutation loops (1 commutation loop vs 4 commutation loops). In addition, there are four switches involved in the two long commutation loops. Those parasitic loop inductances must be minimized simultaneously. Those challenges are addressed by meticulous packaging of the power module, featuring low power loop inductances, double-sided cooled power module, low junction-to-coolant thermal resistance, symmetrical layout for the two parallel dies of each switch and mechanical robustness, etc. The simulated loop inductances are 1.92nH for the short loops and 5.21nH for the long loops, respectively; resulting in a 471V and 540V of turn-off voltage spikes in a double pulse test simulation at 400V/200A. The simulated junction-to-coolant thermal resistances are 0.37°C/W and 0.53°C/W for different switches, respectively.

The parasitic capacitance of a power module baseplate provides a path for displacement current during the switching transient of the power module, which causes extra switching loss and EMI noise. It becomes an increasing concern especially for emerging 10 kV SiC MOSFET modules due to their high voltage and fast switching speed. This paper presents an in-depth analysis of 10 kV SiC MOSFET module baseplate parasitic capacitance impact on switching loss. The turn-on switching energy is divided into four parts, and the module baseplate parasitic capacitance impact on each part of the energy is analyzed. In addition to a constant capacitive energy (i.e., $\displaystyle \frac{1}{2}$ CV2), the module baseplate parasitic capacitance also introduces extra V-I overlap energy during voltage fall stage of the turn-on switching transient because it increases voltage fall time. This portion of loss is modeled and quantified. The module baseplate parasitic capacitance impact on switching loss is experimentally evaluated at 6 kV dc voltage and 0 to 50 A currents. This 10 kV SiC MOSFET module baseplate capacitance contributed loss is in the 5-10% range.

In this paper, a 50-kW 1-kV/6.25-kV medium voltage dual-active-bridge (DAB) transformer has been designed and tested. The shell-type transformer structure with stacked small cores is selected to integrate the leakage inductance and reduce the eddy current loss. Dry-type insulation with selective shielding is adopted and both winding-to-ground and winding turn-to-turn insulation are considered. The transformer geometry-based design procedure is discussed to achieve high efficiency and power density considering the effect of eddy current loss and insulation constraint. Tests up to the full voltage and power were performed and the DAB transformer achieved 99.66% full-load efficiency and 13.5 kW/L density for the transformer.

This paper presents temperature sensitive electrical parameters (TSEPs) selection for a 10 kV silicon carbide (SiC) MOSFET power module. Static parameters including ON-state resistance and threshold voltage are introduced. A double pulse test (DPT) platform is built to test the power module on a hotplate, and the switching transient behavior in a temperature range from 25℃ to 125℃ is analyzed in detail. Various parameters during turn on and turn off are measured and compared based on their temperature linearity and sensitivity. Load current and gate resistance impacts on measurement are discussed, as well as comparisons to low voltage SiC MOSFETs.

This paper presents a low cost Si IGBT circuit breaker for protection of the Wolfspeed 10 kV XHV-9 half bridge SiC MOSFET module. Based on the 10 kV SiC module short circuit (SC) protection requirement, both current limiting and desaturation protection are needed for this IGBT breaker. Voltages balancing for series-connected IGBTs and effective current limiting of this IGBT breaker during SC transient are discussed. Detailed modes transition between the 10 kV SiC module and the IGBT breaker during SC transient is analyzed. Demonstration of the 10 kV SiC module with the IGBT breaker SC test and continuous power test at 6 kV voltage are presented.

This paper presents a half-bridge submodule design based on a 10 kV SiC MOSFET XHV-9 power module. The design of the gate driver, isolated power supply, and busbar are presented. High voltage insulation capability, fast short circuit protection, and resilience to EMI of the designed submodule are demonstrated through continuous power tests at 6.5 kV, 57 A and through a short circuit test. This submodule verification facilitates the adoption of high-voltage SiC MOSFETs in medium-voltage (MV) converters, shedding light on highly efficient power conditioning systems (PCS) for grid applications.

A hybrid microgrid is an attractive concept that aims to deliver energy to local ac and dc loads, reducing the strain imposed on the electrical grid. A hybrid microgrid of a flexible manufacturing plant consists of dc and ac loads, and distributed energy resources interfaces with the distributed grid through a power conditioning system to enable grid support capabilities and control power flow. To evaluate the controller functions of the hybrid microgrid, an appropriate testing platform is required. In this paper, the plant is emulated via a converter-based hardware testbed. The developed hardware testbed serves as a realistic model of the flexible manufacturing plant to test the controls and different scenarios to address potential issues or challenges with the control strategies and algorithms before system deployment. In addition, the hardware testbed provides the opportunity to validate the system’s response under different operating conditions in a controlled environment, leading to a more robust and reliable system design.

A solid-state circuit breaker (SSCB) needs to have very high efficiency comparable to its mechanical counterpart, and GaN offers highest conduction loss reduction at cryogenic temperatures. So, cryogenic cooling of future EAP is leveraged to design a 750V/100A SSCB module with an efficiency target higher than 99.9% and high over-current capability. The cryogenically cooled SSCB module design is developed in this paper, including key components selection and module design considerations. Experimental results are provided to validate the capability of the designed SSCB module to interrupt 10x of rated current at cryogenic temperatures (<-153°C).

Solid state circuit breaker (SSCB) with high efficiency and high gravimetric power density is required for Electrified Aircraft Propulsion (EAP). A cryogenically cooled GaN device based SSCB module is developed for EAP system. The SSCB module is suitable for medium voltage direct current (MVDC) applications and is designed with low-weight modular cold plates. Each module is rated for 750V, 100A and achieves a power density of 329 kW/kg. The design of the SSCB module structure, thermal design, and insulation design are discussed. Experimental results of interrupting an over-current fault of ~10x of the rated current by the SSCB module is provided to validate its operation at cryogenic temperature.

Parasitic capacitance of dc/dc transformers interfacing the cascaded H-Bridge (CHB) converter can introduce extra switching losses. A switching loss reduction method with diode clamped grounding for dc/dc transformers connecting CHB is proposed in this paper. The transformer grounding is connected to diode clamping circuit on the low voltage dc link to partially cancel the voltage charging/discharging the parasitic capacitances. Simulation and test have been demonstrated that the proposed method has reduced 53% of the parasitics induced loss and $\sim$ 6% of the total converter loss in the setup with one simple diode half-bridge clamping circuit added on each converter cell.

Microgrids help facilitate the integration of renewable energy in distribution-level grids and increase the resilience of the electric grid to extreme weather, especially in rural areas. Compared to traditional microgrids, a networked microgrid leverages multiple grid-forming sources to form a potential meshed grid and is more flexible in operation. This paper demonstrates the simulation modeling of an actual networked microgrid located in Adjuntas, Puerto Rico. The model contains representations of power inverters that connect the battery energy storage systems and photovoltaic generation systems to the networked microgrid and is capable of simulating fast grid transients as well as long-term operation of the networked microgrid. The modeling technique for power inverters allows the time-efficient simulation of the microgrid with a minimal penalty on model accuracy.

With the increasing penetration level of renewable sources and power electronics loads in modern power systems, accurate and computationally efficient models are needed. Black-box model (BBM) could be a useful method in such systems. However, not very extensive research efforts have been made for power electronics BBM so far, and existing works mostly focus on steady-state operation, neglecting the important transient behaviors such as load transients, voltage transients, and faults. This paper presents a comparative study of three commonly used nonlinear BBM approaches for transient behaviors of power electronics converters. Comparison methods are proposed, and the evaluations are conducted under different transients using a grid-connected single-phase photovoltaic inverter. The findings of this study provide valuable references for further feasibility investigations on implementing BBMs in large-scale power electronics-rich power systems.

The converter level automatic layout is challenging because multiple types of components need to adhere to different placement rules. This paper proposes an implementation method for computers to automatically layout three three-phase voltage source converters. The proposed method utilizes a hierarchical tree to establish layout rules and prioritize components. The layout optimization process involves employing simulated annealing (SA) based heuristic optimization for the phase leg and applying specialized algorithms for different component groups. The layout of the phase leg is optimized for a minimum switching loop inductance. The layout of other components is solved as a floor plan problem or by directly following the design rules defined in the hierarchical tree. The whole converter layout can be visualized, and the switching node capacitance can be extracted. These parasitics enable more accurate switching performance evaluation for the design tool applications. Moreover, the proposed layout design can be easily extended to other types of converters.

Microgrids (MGs) with dynamic boundaries and multiple source locations have been proposed as a future MG concept, which requires sophisticated control and coordination. Testing of MG controllers in a realistic environment becomes essential for the efficient and reliable deployment of such MGs. A converter-based testing platform has been proposed for MG controller evaluation, which requires well-modeled emulators. However, as a core component, existing battery energy storage system (BESS) emulators in the literature cannot meet the testing needs of the M G with dynamic boundaries and multiple source locations. In this paper, a BESS emulator for controller testing of M G with dynamic boundaries and multiple source locations is developed, considering controller functions, different operation modes, and transition coordination. Experimental results are conducted to verify the developed emulator on a converter-based testbed.

The emerging 10 kV SiC MOSFET brings great benefits for medium and high voltage applications, and is drawing increased research attention. Accurate switching transient modeling of the 10 kV SiC MOSFET is critical for successful application. Curve tracer is usually used to extract parameters needed for device modeling. However, the transconductance extracted from curve tracer is tested at low voltage, which is different from the transconductance during actual high voltage turn-on switching transient because of short channel effect and drain induced barrier lowering effect. Moreover, the gate-drain capacitance extracted from curve tracer is tested at static off-state, which is also different from the gate-drain capacitance during dynamic turn-on switching transient as the MOSFET channel is turned on in this process. Conventional models based on curve tracer tests show obvious discrepancies compared to experiments. This paper investigates and characterizes the high voltage transconductance and dynamic gate-drain charge of the 10 kV SiC MOSFET during turn-on switching transient. An improved turn-on switching transient model considering these factors is proposed. Experiments with the 10 kV 20 A SiC MOSFET are conducted and verify the accuracy of the proposed improved model.

With the development of the modulation strategies for dual-active-bridge (DAB) converters, single-phase-shift (SPS), dual-phase-shift (DPS) and triple-phase-shift (TPS) have been proposed aiming at the realization of zero-voltage-switching (ZVS) or elimination of the reactive power at different power and voltage. While the previous work mainly focuses on the steady-state operation or the small-signal model for one specific modulation strategy, the real practice requires modulation strategies to switch among SPS, DPS and TPS frequently during the load transients, which can cause a current spike and dc-bias current in the transformer. Therefore, a smooth transition among different modulations is necessary. This paper proposes a duty-cycle compensation method to eliminate such current spike and DC bias. The implementation of the proposed method in the control loop is also discussed. Finally, the experimental results are provided to validate the performance of the duty-cycle compensation method.

Medium voltage SiC devices facilitate the development of medium voltage grid-connected power electronics converters. However, it is difficult to test these converters directly on the real medium voltage grid, especially considering abnormal grid conditions, such as grid voltage and frequency variation, and different converter operation modes, such as grid-connected mode and islanded mode. This paper introduces the design and implementation of a medium voltage testbed, which supports tests of medium voltage converters in both grid-connected and islanded mode tests. In the grid-connected mode, the testbed can provide up to 13.8 kV grid voltage, can support the four-quadrant operation, and can emulate different grid conditions, such as voltage and frequency variation. In the islanded mode, the converter under test works as a voltage source and the testbed emulates a three-phase balanced or unbalanced load. Experiment test results are provided to validate the design and capability of the testbed.

The DC measurement capability and high- frequency bandwidth are vital aspects for current sensors to accurately capture the switching current behavior of wide bandgap devices. However, typical Rogowski coil (RC) current sensors lack DC sensing capability resulting in inaccurate low- frequency measurement results. This paper presents a concept of combinational RC with improved DC measurement capability without intruding the power loop area for double pulse test (DPT) systems. The DC current sensor and the RC are placed at different locations to capture the low-frequency and high-frequency switching current, respectively. An analog adder circuit is used to combine the two sensing results, thereby extending the measurement bandwidth of the RC without increasing the insertion parasitic inductance. The frequency-domain measurement of the combinational RC with DC sensors verifies the extended DC measurement bandwidth. In the paper, the switching current measured from a half-bridge SiC power module under DPT has been used as an example to demonstrate the enhanced measurement capability of this combinational RC avoiding an increase of extra parasitic.

Medium-voltage (MV) dual-active-bridge (DAB) converters have become an emerging technology thanks to high-voltage silicon carbide (SiC) devices and nanocrystalline magnetic materials. However, the need of phase-shift inductance and insulation requirements for the MV DAB may complicate the design of the transformer and the MV DAB converter, which can also induce higher loss and occupy more space. In this paper, the leakage integration and insulation techniques are discussed for a 6.7-kV/850-V DAB converter, meeting both the inductance and insulation requirements of the MV DAB converter. Ferrite cores with air gaps are inserted between the LV and MV windings without introducing high loss, and the MV winding is selectively shielded to avoid high parasitics and meet the insulation requirement. Test results have verified the effectiveness of this design.

In this paper, to reduce the power loss caused by the parasitic capacitances of medium voltage medium frequency transformers in a two-stage dc/ac converter, including a dual active bridge (DAB)-based dc/dc stage and a cascaded H-bridge (CHB)-based dc/ac stage, a PWM strategy is proposed for the dc/ac stage. For each H-bridge, by shifting the high switching frequency to one half-bridge and having the other half-bridge switching at the fundamental frequency of the ac voltage, equivalent frequencies of transformer terminal-to-ground voltages are reduced. As a result, the frequencies of charging and discharging current to the parasitic capacitance are reduced, and therefore the loss caused by the parasitic capacitances is reduced. Compared to the conventional phase-shift PWM, the proposed PWM strategy can reduce the parasitic capacitance loss by about 75%. Experimental test results of one phase in the 13.8 kV/ 100 kW converter prototype are provided to validate the approach.

The transformer flux unbalance in dual-active-bridge (DAB) converters is a critical issue due to the electrical parameter and modulation mismatch, and load or control transients. Compared to low voltage DAB converters, the unbalance problem in medium voltage DAB converters may cause more severe problem, and become more difficult to deal with, because of the high operating voltage and insulation requirement. In this paper, a flux balancing strategy for a medium voltage (MV) DAB converter is proposed, including the transformer design with ferrite gap, current harmonic-based unbalance detection, as well as the flux balancing control scheme. With the proposed ferrite gap, nonlinear magnetizing current and its modeling are induced. Then, by analyzing the current harmonics, the flux unbalance level can be detected, and hence controlled. Test results have verified the proposed method in a MV DAB converter.

An asynchronous microgrid (ASMG) with silicon carbide (SiC) MOSFET-based power conditioning system (PCS) is an attractive option for future microgrids, which can potentially improve microgrid dynamic performance and grid power quality. To support future microgrids’ needs for higher power, scaling PCS power via paralleling multiple modules or converters is a potential solution. In this paper, a strategy for scalable ASMG PCS operation is proposed. MMC-based PCSs are implemented to demonstrate the proposed strategy, including MMC paralleling operation analysis and corresponding control functions. Experimental results are provided to demonstrate the scalable PCS operation at 25 kV rated voltage.

Asynchronous microgrid (ASMG) is a microgrid concept where the ac microgrid is connected to a utility grid through a power conditioning system (PCS). The development of high voltage (HV, >3.3 kV) silicon carbide (SiC) MOSFET technology promotes the implementation of ASMG PCS converters. However, the system-level benefits from SiC MOSFETs have not been well studied for this application. This paper discusses ASMG system stability enhancement resulting from HV SiC MOSFET-based PCS converters. HV SiC MOSFET-based PCS converters can achieve high control frequency, which can benefit the potential harmonic instability caused by the digital control delay. A detailed theoretical analysis is provided, and experimental results for the stability enhancement capability are demonstrated on a converter-based hardware testbed (HTB).

This paper provides an analysis of the desat protection for high voltage (>3.3 kV) SiC MOSFETs from the perspective of noise immunity. The high positive dv/dt with long voltage rise time generated by high voltage SiC MOSFETs is identified as a major threat to noise immunity of the desat protection circuitry. The impact of numerous influencing factors is analyzed, such as parasitic inductance, damping resistance, and clamping impedance. In some cases, small parasitic capacitances (<0.01 pF) between the drain terminal with high dv/dt and protection circuitry dominate the noise immunity of the desat protection circuitry with high-impedance voltage divider. The noise immunity margin is derived quantitatively to guide the noise immunity improvement. Different noise immunity enhancement methods are developed and validated with experimental results, including adding a shielding layer, reducing clamping impedance, and decreasing voltage divider impedance.

Medium voltage (MV) asynchronous microgrids have numerous unique benefits over regular synchronous MV ac microgrids. This paper focuses on a MV transformer less asynchronous microgrids power conditioning system (PCS) using 10 kV SiC MOSFETs. The benefits of a 10 kV SiC MOSFET based PCS include simplified topology, higher control bandwidth, and hence more advanced control functions, although it is still challenging to apply 10 kV SiC MOSFETs with their associated much faster switching speed in MV systems. A modular design approach is adopted in the design and implementation of the PCS as well as its controller. The sophisticated grid functions of the asynchronous microgrid PCS are supported by a hierarchical modular control system. A 100 kVA back-to-back transformer less PCS for a 13.8 kV MV grid is developed and tested at rated voltage and power.

Numerous testing of power electronics converters with various load types/conditions shall always be conducted before finalizing the design parameters, wherefore load emulator, also known as active power electronics load or dc/ac electronic load, is superior to passive load and real load in terms of testing flexibility and cost especially in high voltage, high power applications. This paper proposes a concept that by paralleled operation of modular multilevel converters, a versatile testing platform for dc-ac/ac-dc voltage source converters, so called Reconfigurable Ac Load Emulator, can cover extremely wide range of operation voltage and frequency while effectively emulating different types/conditions of load. The emulator enables faster, more efficient and flexible testing of power electronics converters. Both simulation and experiments prove the feasibility.

The Dual-Active-Bridge (DAB) converter transformer flux unbalance, or dc bias, could be a critical issue due to the mismatches of converter circuit parameters and control transients. In this paper, a steady-state flux balancing scheme, based on the second-order harmonic of magnetizing current has been proposed. The relationship between steady-state flux/magnetizing current unbalance and its harmonic contents has been analyzed, with which a new current sensing method and control strategy are introduced. The proposed magnetizing current sensing method can be implemented for both unity and complicated fractional turns ratios, without high sensitivity to dc offset from the analog circuitry. The proposed scheme has been validated with experimental results on 850-V/850-V DAB converters within a system, as well as in an 850-V/6700-V medium voltage DAB unit.

Low-voltage ride-through is one of the grid requirements for grid-connected converters, and during the transient of grid voltage change, a large inrush current could be induced due to the control delay of the converter. This inrush current is more severe in SiC-based multi-level converters due to the small filter inductance, which is selected based on harmonics consideration. In this paper, a PWM mask method is used to limit the inrush current of a cascaded H-bridge-based grid-connected converter during the transient of grid voltage change. Simulation and experiment results are provided to validate this method.

The surge voltage induced by lightning will generate an inrush current in a grid-connected converter. It may not be large in Si-based converters because of the large grid side inductive filter. However, for SiC-based multi-level converters, the inrush current could be very large due to the small filter inductance, which is selected based on the current harmonic consideration. Most previous work focuses on system-level lightning protection while the converter-level impact, especially the internal components of the converter, is rarely discussed. This paper presents the analysis of the impact of the lightning surge on a 10 kV SiC MOSFET-based 13.8 kV three-phase four-wire grid-connected converter. The IEEE arrester model and the combined wave generator model in IEC 61000-4-5 standard are used to evaluate the inrush current, DC-link overvoltage, and component-to-ground potential of the converter. Analysis and simulation results have been provided to demonstrate the impact of lightning on the grid-connected converter. It is found that large inrush current occurs due to the small filter inductance, and the neutral-to-ground impedance impacts both the inrush current and the neutral point-to-ground potential.

Medium voltage SiC devices facilitate direct (without 50/60 Hz transformer) connection of the power electronics converter to the medium voltage grid using simple topology. Compared to the insulation design of medium voltage inductors that have been widely used in the power system, the insulation design of directly connected medium voltage converter filter inductors has more challenges. Although some works has been done discussing that, the grid insulation requirements on converter filter inductors are rarely discussed. This paper introduces the insulation design of a grid-side filter inductor for a 13.8 kV power conditioning system converter. The grid insulation requirements, including the short-duration power frequency overvoltage and the lightning impulse voltage, are considered in the design. To meet the requirements, the layer-to-layer insulation, winding-to-core/ground insulation, the air gap discharge between the winding and the core, as well as the local electrical field have been taken into consideration. Experimental tests are provided to validate the design.

Recent research reveals that gallium nitride (GaN) devices achieve significantly reduced on-state resistance and faster switching speed operating at cryogenic temperature. These characteristics enable GaN-based power converter to achieve higher efficiency and power density and make GaN device an excellent candidate for cryogenic power electronics applications. However, overcurrent and short-circuit capability of GaN device at cryogenic temperature have not been evaluated. This paper characterizes a 650V-30A enhancement-mode GaN high-electron mobility transistor (HEMT) and experimentally evaluated the overcurrent and short-circuit capability at cryogenic temperature. Testing results show that this GaN HEMT achieves >5X conduction loss reduction and 30% switching loss reduction at cryogenic temperature. Moreover, GaN HEMT is capable of operating at around 4X of rated current at cryogenic temperature. The short-circuit capability at cryogenic temperature is similar to that at room temperature. Both the device failure threshold dc voltage and short-circuit withstand time are almost unchanged at cryogenic temperature.

This work evaluates the overcurrent capability of 600V Gallium Nitride (GaN) Gate Injection Transistor (GIT) under different time durations and initial junction temperatures in a non-destructive approach. Setups and procedures are established to control drain current, time duration and junction temperature. The degradation of the device is examined after each overcurrent test. Gate-to-source voltage, drain-to-source voltage and drain current are measured for each test. Based on the test results, maximum withstand current, It-curve, I²t-curve, and maximum withstand energy are determined for 600V GaN GIT. The results can be applied to the design of GaN-based converters for transient and overload conditions, as well as dc solid-state circuit breakers.

In power electronics-based power systems (PEPSs), small-signal stability is an important factor for system design and operation, where the impedance-based approach is often used. However, unlike small-scale PEPSs with simple and straightforward impedance models, it would take much more efforts to derive the large-scale PEPSs impedance model, which is very complicated and sometimes may get wrong results due to the elimination of right-half plane (RHP) poles during the impedance aggregation process. To simplify the derivation procedure and analyze the small-signal stability of large-scale PEPSs, this paper proposes a nodal admittance matrix (NAM) based area partition method. In this method, the large-scale PEPS is divided into several sub-areas, and the stability is analyzed within the sub-area first, and then the interconnection stability among these sub-areas is analyzed. The proposed method is scalable and can help to locate the weakest areas/converters that may cause instability in the whole system. In this paper, the concept of the proposed method and its application to an example system are introduced. Experimental results are also given to validate the effectiveness of the proposed method.

Existing current sensors suffer from insufficient measurement bandwidth or large insertion area to continuously monitor the switching transient current of wide-bandgap devices. A combinational Rogowski coil concept is proposed here, where the self-integrating region of a shielded Rogowski coil is combined with its differentiating region. The overall measurement bandwidth is effectively extended by the self-integrating region. The design methodology for the shielded Rogowski coil, especially the parasitic elements and error analysis, is discussed. Finally, a prototype is demonstrated with a sensitivity is 5.0 mΩ and a bandwidth of 200 MHz. The measurement in a SiC power module double pulse shows it can faithfully capture the transient current while introducing little interference.

A flexible combined heat and power (F-CHP) concept, enabled by a power electronics-based power conditioning system (PCS), has been recently proposed as a cost-effective way for supporting the grid with high penetration of renewable energy sources. To verify the design, control, and performance of the overall system, a laboratory-scale testbed is essential. This paper focuses on the development of a power electronics-based testbed for such a F-CHP system. The developed testbed can test the control, grid-connected mode operation, islanded mode operation, and mode transitions, including planned/unplanned islanding and reconnection, of the F-CHP system. In the grid-connected mode, both the steady state and transients of the ac grid can be emulated, and various grid support functions can be tested with the help of the developed PCS converter. In the islanded mode, the external ac loads can also be supported by the F-CHP system. Also, the central controller, which is implemented in a NI CompactRIO, can be tested. Experimental test results for the grid-connected mode, islanded mode, and mode transitions are provided to validate the testbed design.

This paper presents an automated design tool for three-phase motor drives. The design tool integrates state-of-the-art design algorithms and component models to reduce paper design efforts for engineers. The converter is optimized for minimum weight considering comprehensive design constraints and conditions configured by users. The software is modular so that some component models can be selected by users based on design speed and accuracy considerations. The user interface (UI) of the tool is developed with the App designer, and both the design algorithms and models are implemented by M-script in MATLAB. Besides, eight databases for components, including devices, passives, and cooling, are built with commercially available products and can be managed by users. The final design results can be visualized in detail. A case study is presented to show how the design tool works.

Grid-forming inverters (GFMs) based on active power-frequency droop control and reactive power-voltage droop control have been developed in recent years, which can generate voltage and frequency references for islanded power systems or microgrids to improve system-wide synchronization and power-sharing capability. It is known that the control delays in GFMs may cause system harmonic instability. To eliminate this issue, virtual impedance techniques are normally adopted. This paper gives a comprehensive examination of the impacts of virtual impedance control block Zv in GFMs on system stability. It is revealed that although Zv is effective in eliminating system harmonic stability, it may ruin system synchronization stability as a side effect. To compensate for the negative impacts caused by Zv, an active power-angle control block is added into the conventional droop control. Design criteria are also proposed accordingly to ensure system stability over the entire frequency range. Simulations and experimental testing are conducted to validate the analysis and the proposed design guidelines. It can be concluded that the Zv control-caused grid-synchronization instability issues can be eliminated with an appropriate active power-angle droop design.

In future aircraft electric power systems (EPSs), the dc distribution is regarded as a promising substitution for conventional ac distribution because of the reduced weight. However, the assessment of weight reduction is usually obtained under the system static performance requirements. Dynamical requirements, including small-signal stability, normal load transient, and abnormal transient have not been fully considered. Therefore, this paper aims at bridging this gap by providing a design example under comprehensive system requirements to study the impacts of dynamical requirements on dc and ac, separately. It is seen that if only static requirements are considered, dc EPS is lighter than ac mainly due to the lighter feeders. But if dynamical requirements are factored in, the notional dc EPS will need additional energy storage systems (ESS) and protection devices because it lacks energy storage capability and has faster fault current dynamics intrinsically, comparing with the notional ac EPS.

A pulse-width modulation (PWM) voltage source converter is a vital asset in aircraft electrification. These converters operate using fast (10-100kHz) switching power semiconductors. Partial discharge (PD) that occurs in insulation due to this PWM voltage is difficult to detect due to the transient noise of the voltage switching which obscures the smaller partial discharge signal. The PWM voltage also features high dv/dt and along with the high switching frequency increases the stress on the insulation system. Partial discharge is more likely to occur in greater quantity due to PWM voltage, but more difficult to detect. This paper studies the effect that PWM voltage has on insulation due to the high switching frequency and dv/dt. In order to achieve this goal, PWM Voltage testing platform is designed and electrically isolated detection methods are examined for effectiveness in the presence of PWM voltage noise.

Paralleling and interleaving power converters allows higher power rating as well as reduced output harmonics. However, circulating currents occur in the parallel interleaved converters and degrade system performance. Coupled inductor is usually used to suppress high frequency circulating currents. The coupled inductor design is strongly impacted by the maximum flux linkage in the magnetic core of coupled inductor. This paper aims to minimize the high frequency flux linkage of coupled inductor for parallel interleaved three-level inverters. A carrier based PWM which achieves lowest coupled inductor maximum flux linkage for all modulation indexes is proposed. The coupled inductor flux linkage reduction of the proposed modulation is verified by experimental results on two parallel interleaved three-level active neutral point clamped inverters.

In paralleled three-phase three-level voltage source inverters, sometimes the currents of paralleled inverters need to be separately adjusted to control power sharing, and the reference vectors will differ in phase and amplitude. In other cases, although the current references of the paralleled inverters are set to be the same, the d-axis and q-axis current closed-loop control outputs of each converter cannot be exactly the same due to the asymmetry in hardware or software. As a result, the reference vector of each inverter may also be different in terms of phase and amplitude. When conventional three-level space vector pulse width modulation (SVPWM) is applied, periodical jump can be observed in the phase current of each inverter and the zero sequence circulating current (ZSCC). This paper investigates the current jump phenomenon in paralleled three-level inverters with space vector modulation (SVM). The mechanism that causes the current jump is illustrated. A modulation method to eliminate this current jump is proposed. Simulation and experimental results are presented to verify the effectiveness of the proposed method and conducted analysis.

This paper presents the modeling and analysis of zero common-mode voltage (ZCMV) pulse width modulation with dead-time for three-level voltage source inverters. Analytical model to calculate phase output voltage harmonic of three-level inverter with ZCMV modulation is developed. With ZCMV modulation, the common-mode voltage (CMV) of a three-level inverter can be eliminated in theory. However, CMV reduction performance is limited by dead-time in practical applications. Hence, the harmonic characteristics of CMV is modeled and analyzed considering dead-time. Experiments are conducted on a three-level neutral point clamped inverter with ZCMV modulation, and verify the accuracy of developed models.

The residential air-conditioner (A/C) is one of the most widespread load types for a household in the U.S., and it is reported that the malfunction of A/C load influences the performance of the transmission network. However, the lack of accurate modeling of A/C loads limits the effectiveness of evaluating power system dynamic performance and grid stability analysis. A real-time power emulator for an A/C motor using a three-phase voltage source inverter (VSI) is proposed in this paper, which emphasizes the "point-on-wave" characteristics of the A/C load. The proposed VSI based A/C emulator is advantageous since it demonstrates an accurate dynamic performance without sacrificing the computational resources and simulation time. The experimental results verify the accuracy of the A/C load emulator. Furthermore, the fault-induced delayed voltage recovery (FIDVR) events are emulated and analyzed in a multiconverter based hardware test bed (HTB) by using the proposed A/C load emulator. In addition, experiments emulating the dynamic response of the A/C load driven by the power electronics (PE) interface is also performed in the HTB, verifying that the application of PE-interface-driven A/C motor can contribute to alleviating the FIDVR event.

Medium voltage (MV) power converters using high voltage (HV) Silicon Carbide (SiC) power semiconductors result in great benefits in weight, size, efficiency and control bandwidth. However, HV SiC MOSFET based converters suffer from high dv/dt (>100 V/ns). Under high dv/dt environment, sensors are easily interfered due to the power electronic device’s fast switching. In this paper, the noise coupling mechanism in a submodule (SM) voltage sensor is analyzed, and the impact of SM voltage sensor noise on MMC phase-leg operation is discussed. A simulation model and a 10 kV SiC MOSFET based MMC prototype with 25 kV dc-link are built to validate the analysis of the impact.

This work focuses on improving voltage sensor noise immunity in a high voltage and high dv/dt environment. This is demonstrated in a 10 kV SiC MOSFET based Modular Multilevel Converter phase leg. The design is improved through several iterations while employing methodologies such as shielding, PCB layout techniques, improving the signal-to-noise ratio, and reducing the bandwidth of the sensor to reduce the noise impact of the high dv/dt of the SiC device. The impact of each methodology on the design is stressed, and the final version of the sensor shows significant improvement in noise immunity while offering the best high voltage design available.

In a modular multilevel converter (MMC) working as a rectifier, digital controllers are widely adopted and usually have three control loops: an inner ac current loop, an outer dc voltage loop, and a circulating current suppression loop. The main design constraint on these control loops is the control delay, which may cause system instability. A few previous papers have analyzed this issue, but only MMC inverter with circulating current proportional integral (PI) control was investigated. In this paper, the generation mechanism of control delay in each control loop of an MMC rectifier is analyzed. Small-signal loop gain models for all the three loops are developed. Based on the control loop models, design cases are examined, and a delay compensation scheme is implemented as an example. Both simulations and experiments validate the effectiveness of the analytical models.

This paper focuses on a robust 10 kV SiC MOSFET gate driver with an improved desaturation protection scheme for overcurrent protection. The gate driver is designed for 10 kV/20 A SiC MOSFETs in a modular multilevel converter (MMC) submodule. The gate driver has short circuit protection, status feedback in every switching cycle, dead time insertion, and undervoltage lockout (UVLO) function to support robust continuous operation of the MOSFET and converter. Practical design considerations are elaborated to achieve these functions. With a digital blanking time of 600 ns, the improved desat protection achieves a response time of <350 ns under hard switching fault (HSF), and a response time of <200 ns under fault under load (FUL) and flashover fault. All functions of the gate driver are fully validated in a MMC submodule with a rated dc-link voltage of 6.5 kV.

Asynchronous microgrid with PCS converter is a new microgrid concept with potentially better performance compared to conventional microgrid. In this paper, a PCS converter controller is designed and tested fully considering different grid requirements including different microgrid operation modes as well as normal and fault grid conditions. The controller architecture and functions are presented. The developed controller is tested on a scaled converter-based hardware test-bed.

Junction temperature is one of the most critical indicators not only for the converter design and operation but also for power devices’ reliability. Online monitoring of junction temperature can provide useful information for converter control, protection, and maintenance. In this paper, an intelligent gate driver with online Tj monitoring capability is developed for SiC MOSFETs. The turn-on delay time is selected as the thermal sensitive electrical parameter (TSEP) for online Tj estimation. Moreover, a gate resistance regulation unit is implemented with 10 times sensitivity improvement to increase the measurement accuracy. Then, an edge-detection-based online turn-on delay time measurement with 200 ps resolution is designed and integrated into the gate driver. In the end, a double pulse test (DPT) platform is applied to collect the calibration curves offline. A SiC-based half-bridge inverter is also built to demonstrate the functionality and performance of the online junction temperature monitoring system. Resultantly, this intelligent gate driver can accurately estimate devices junction temperature during inverter operation.

To reduce the volume and weight of differential-mode (DM) inductors, the leakage inductance of a toroidal common-mode (CM) choke is ofen used as partial DM inductance. However, the accurate prediction of the leakage inductance of CM chokes through an analytical model is difficult, making the determination of remaining DM inductance difficult. This paper proposes a modeling method with the analogy between reluctances (or magnetic fields) and capacitances (or capacitive fields). The proposed method is verified by the leakage inductance comparison between the proposed model and simulation results for two CM cores with different turns numbers and wire gauges, and it demonstrated the proposed model can achieve the errors within 15% compared with simulation results for all cases.

Due to the high saturation flux density and the high initial permeability, toroidal nanocrystalline cores are widely applied in the common-mode (CM) inductor design for high power applications. Compared with the flat permeability curve of ferrite cores up to several MHz, the permeability of nanocrystalline cores with a high initial value drops at only around 100 kHz. In addition, the imaginary permeability of nanocrystalline can provide a considerable impedance to achieve the noise attenuation compared with ferrite, being neglected in the inductance-oriented design approach. To achieve a more accurate design result, the paper proposes an impedance-based design approach with considering both frequency-dependent and imaginary permeability of nanocrystalline cores. The required impedance of a CM inductor is derived by the equivalent circuits at a specific frequency. Then, with the frequency-dependent permeability model, the turns number can be calculated by providing enough impedance using both the inductance produced by the real permeability and the resistance produced by the imaginary permeability. After sweeping the frequencies from 150 kHz to 2 MHz in the EMI range, the final turns number will be determined. The proposed design approach is validated with noise measuring in a 10 kW ANPC converter.

A programmable device driver platform capable of driving most power semiconductor devices and adapting to both voltage source and current source driving schemes is demonstrated here. It enables driving most power electronics devices, including Si IGBT, SiC MOSFET, SiC BJT and GaN HFET. Two-level or multi-level voltage source driving as well as current source driving are also demonstrated to showcase its capability. The programmable driver platform allows user to quickly drive devices and evaluate their performance in dynamic characterization. It also provides a tool for users to quickly optimize their gate driving performance in power electronics converters.

Variable speed drives (VSDs) have been gaining more popularity in recent years, since they not only improve the motor load performance, but also can provide grid frequency support after a grid disturbance. However, the existing open loop grid frequency control scheme restricts the power support performance provided by VSDs. In this paper, a closed loop primary frequency support scheme adopted by the VSD is proposed for grid frequency enhancement. Additionally, a real-time power emulator for a passive-front-end VSD using a three-phase voltage source converter (VSC) is developed, which is used for analog testing environment. The developed VSD load emulator demonstrates an accurate dynamic performance without sacrificing the computational resources and simulation time. The accuracy of the VSD load emulator has been verified by experimental results. Furthermore, the grid frequency support provided by VSD loads is performed in the multi-converter based hardware test-bed (HTB) by using the proposed VSD power emulator.

The behavior of 10 kV SiC MOSFETs during a flashover fault condition is investigated comprehensively. A larger turn-off gate resistance R_g,off is recommended for 10 kV SiC MOSFETs without Kelvin source to avoid very asymmetrical gate resistance, while a small R_g,off is recommended for 10 kV SiC MOSFETs with Kelvin source. Guidelines regarding gate loop inductance and selecting an external capacitor across gate and source terminal are also provided. 10 kV SiC MOSFETs have much higher energy loss under flashover fault compared to typical short circuit faults. The required response time for short circuit protection to safely clear flashover fault should be at least 350 ns shorter than the response time designed to clear conventional short circuit faults.

CURENT's grid emulator contains multiple inverters to mimic the behaviors of several grid elements. The filtering inductor at the ac terminal of an inverter filters out the switching ripple current. However, the voltage on the point of common coupling (PCC) still contains switching harmonics. A decoupling capacitor at the PCC can effectively suppress the switching ripple voltage and improve voltage quality of the grid emulator. This paper provides a reduced order model of the multi-inverter system. With this reduced model, the PCC voltage harmonics can be derived. The decoupling capacitor of the PCC is designed to suppress the switching ripple based on the reduced model. Simulation and experimental results are provided to validate the proposed model and the decoupling capacitor design.

A test scheme is designed to qualify MMC submodules based on 10 kV SiC MOSFETs comprehensively, including thermal design, insulation design, and operation under high dv/dt. In the test scheme, the essential step is the continuous test realized with the proposed ac-dc continuous test circuit with two MMC submodules in series. With the designed modulation scheme, two cascaded submodules are leveraged to generate high dv/dt. The submodule under test has to continuously withstand 2X normal dv/dt of 10 kV SiC MOSFETs, which could occur during the MMC converter operation. Higher dv/dt can also be generated to fully test the submodule. An open loop voltage balancing method is adopted to simplify the continuous test setup. Simulation and experimental results are provided to validate the proposed test scheme.

The fast development of the 10-kV SiC MOSFET demands for high-insulated gate drive power supply (GDPS) with low inter-winding-capacitance, low load-regulation-rate, and high conversion-efficiency. This paper presents a comparative study of primary-side-regulated (PSR) and secondary-side-regulated (SSR) GDPS for 10-kV SiC MOSFETs. Design considerations, including high-insulated transformer design, output voltage regulation scheme, and control IC selection, are evaluated. To verify the theoretical analysis, two types of GDPSs are fabricated and tested in the lab, and the experimental results show that the PSR GDPS has better performance because of lower inter-winding-capacitance, lower load-regulation-rate, and higher conversion efficiency.

Grid-connected full bridge inverters typically have a bulky electrolytic dc capacitor to absorb the unbalanced power from the ac side. The electrolytic capacitors are vulnerable and normally have shorter lifetime than other components in the converter. In most full-bridge inverter applications, the dc voltage is required to be relatively constant. However, in reactive power compensation applications, such as solid-state variable capacitor (SSVC), the constant dc-bus voltage is unnecessary since the dc bus is floating. This paper proposes a three-phase dc capacitor-less SSVC, which removes the electrolytic dc capacitor from the circuit by releasing the constraints on dc bus voltage fluctuation. The dc voltage is supported by ac side voltage directly. The remaining dc capacitance has a value of only 3% compared to that of the conventional three-phase SSVC. The proposed three-phase dc capacitor-less SSVC is validated by simulation.

Asynchronous microgrid with power condition system (PCS) converter is a potential future application area of medium voltage converters. However, there has been only limited research focusing on actual implementation of PCS converters. This paper describes the controller development of a 13.8 kV, silicon carbide (SiC) MOSFET-based dc/ac four-wire modular multi-level converter (MMC) for an asynchronous microgrid considering grid requirements. Control architecture and detailed central and phase controller functions are discussed. Experimental results under balanced and unbalanced load conditions are demonstrated.

Virtual synchronous generator (VSG) control allows renewable energy sources to behave like traditional synchronous generators under grid disturbances. Under large disturbances, due to the limitation of output current from grid interfacing power electronic converters, VSG controlled sources may output less active power than the emulated SG. Analysis of a single machine infinite bus system shows that the limited current would impair the system transient stability by increasing the acceleration area during a short circuit fault, and decreasing the deceleration area after it. A mitigation method is then proposed to compensate the negative impacts. Experiments with an emulated downscaled multiple machine system are shown to demonstrate the feasibility of the proposed method.

Fast electric vehicle(EV) charging stations have become one of the fastest-growing penetrated power electronics (PE) interfaced loads to the electric power system. The lack of accurate model of the fast EV charger in transient stability (TS) simulation tools limits the effectiveness of power system dynamic performance evaluation and stability analysis. In this paper, The electromechanical model of a fast EV charging unit is proposed, which is suitable for large-scale power system dynamic analysis in TS simulators. The EV charger model is simplified to guarantee a balance between model accuracy and simplicity. The validity of the proposed model has been demonstrated by a comparative study with the benchmark model created in PSCAD/EMTDC.

Power electronic converter will be a key enabler for future electrified aircraft propulsion system. In aircraft applications, superconducting technologies such as superconducting motors and generators along with supporting power systems will grow in importance. Utilizing cryogenic cooling for power converter potentially can significantly improve the inverter system efficiency and specific power. This paper presents the cooling, hardware, and testing of a cryogenically-cooled MW inverter developed for electrified aircraft propulsion system. The 1 MVA full load testing with cryogenic cooling is demonstrated. The developed inverter system achieves 18 kVA/kg specific power and 99% efficiency, which provides a promising solution to achieve high power density and efficiency for future electrified aircraft propulsion system.

The emerging medium voltage (MV) silicon carbide (SiC) devices (e.g. 10 kV SiC MOSFET) have higher voltage ratings, higher switching speed, lower switching loss, and higher temperature capability than mature MV silicon (Si) devices. Using MV SiC devices in grid power electronics converters may reduce the converter size leading reduced converter and system cost; and it may also improve the grid control and support functions provided by converters as a result of faster switching and control bandwidth. It is important to systematically assess the impact of using MV SiC devices on grid power electronics from both the converter and system standpoint side. This paper focuses on evaluating converter level benefits of SiC through Si- and SiC-based converter benchmark design. Converter size is used as the metric, and size comparison is conducted for different applications, voltage levels, and power ratings. It is found that SiC-based converters' sizes are reduced because of the simplification of topologies and smaller passives. In most topologies, SiC-based converters need smaller capacitors and smaller magnetics than Si based converters because of higher switching frequency. The impact is a strong function of topology, voltage and power rating. The size reduction of one topology may even change for different applications because of different operating conditions.

To analyze the small-signal stability of a power-electronics-based dc distribution system, it is important to know the converter input and output impedances. In a physical system, the converter impedances are measured for stability analysis in different ways. Many impedance measurement methods require dedicated frequency analysis equipment and/or are not suitable for high-power applications. This paper proposes one practical and easy-to-use solution for dc impedance measurement, which does not need any dedicated equipment or any extra power supply. Instead, it uses a two-level voltage source converter, which is usually available in a hybrid dc grid, to inject small perturbations into the system under test. Then the dc terminal voltage and current waveforms are measured by oscilloscopes and imported to MATLAB for further handling. Fast Fourier transform and system identification techniques are conducted to get the non-parametric impedance transfer functions. Simulation and experimental results are also given to validate the effectiveness of this approach.

This paper presents the converter design and cost comparison between Gallium Nitride (GaN)-based and Silicon (Si)-based 4.5-kW single-phase inverters. For fair comparison, both inverters are optimized under the same requirement as a practical Si PV inverter. The cost of the components are based on the component prices at high quantity. The study shows that although the cost of active devices and heatsink is higher for GaN-based inverter, the overall cost can be $ 19 (10%) lower than Si-based counterpart by using switching frequency 6 times higher, which drastically shrinks the passive filters. A GaN-based prototype is built and tested to verify the design.

Solid State Circuit Breakers (SSCBs) protect equipment in power systems during short circuit and overload. Evaluating the i²t capability of devices can be critical to the overload protection design of the SSCB. Previous methods used the junction-to-case dynamic thermal impedance to estimate the i²t capability. However, the overall dynamic thermal impedance can be influenced by the thermal management. In this paper, we investigated the influence of the heatsink on the dynamic thermal performance of the power switch. More importantly, we presented an experimental method to characterize the i²t capability of devices under the worst operating condition for the SSCB. The on-resistance of the switch is measured to predict the junction temperature with an improved voltage sensing circuit. Then, by applying over-current pulses with various current levels and pulse lengths, the relationship between the i²t value of over-current pulses and the junction temperature rise of the device can be investigated. The presented method has been verified to characterize the i²t capability of a SiC power module.

In power electronics design, the selection of power semiconductors mainly considers the voltage and current ratings, power loss, and operating frequency capability. However, in the paper design stage, the impacts of switching speed and busbar or PCB layouts related geometries design on the converter system are not considered comprehensively, which may introduce a trial-and-error procedure of selecting the gate resistance in the implementations due to overvoltage and cooling capability issues. To shrink the design gaps between the paper design and implementations, with advanced modeling methods and design automation programs, this paper proposes a systematic design approach for power semiconductors selection and cooling system design considering the impacts of switching speed and power-loop layout. The discrete-time switching behavior model for the switching speed prediction and automatic geometry creation program for the power-loop layout are developed to determine the gate resistance in the paper design stage, and the partial element equivalent circuits (PEEC) numerical modeling method is adopted to extract the parasitic inductance for the created geometries. After the determination of gate resistances for the selected device and topology, a multi-variable switching loss scaling method with the discrete-time switching behavior model is used to get the more accurate device losses for the cooling design. A complete design iteration and related verifications are also given in this paper.

This paper generalizes the design of ac-side filter using both coupled and non-coupled inductors for the single-phase full-bridge inverter. The relationship between the filter performance and the ratio of coupled and non-coupled inductance is derived and validated. By sweeping the ratio of inductance, the tradeoffs among weight, EMI attenuation, and loss are discussed. The study also demonstrates a holistic optimization of the filter for a 4.5 kW GaN-based single-phase inverter. Two designs were implemented, tested, and compared in the inverter prototype.

Unstable switching transient oscillation can be detrimental or destructive to power electronics converters. As switching speed increases, the impact of parasitic components became more severe and may lead to unexpected switching behavior. The large-signal and nonlinear nature of the switching transients limits the use of small-signal analysis where operating points must be carefully selected. The Lyapunov function based on Brayton-Moser's mixed potential method is applied here to analyze the self-turn-on phenomena in MOSFETs' turn-off transient. It is shown that the switching transient can be expressed as a gradient descent of a mixed potential function. The large-signal stability theorem provides a metric to quantitatively evaluate the switching transient stability. Comparison with the experimental results shows it can effectively predict the significance of the unstable oscillation and explain the root cause of the self-turn-on phenomena.

The short-circuit robustness of 600 V/30 A GaN gate injection transistors (GITs) was evaluated under various operating conditions to determine the worst-case short-circuit scenario. Although a decrease in maximum short-circuit current was observed with higher bus voltage, the short-circuit withstand time decreases dramatically. At room temperature and a bus voltage of 500 V, the short-circuit withstand time is as short as 160 ns as opposed to 220 ns at 400 V. The withstand time also depends on the maximum short-circuit current and can be extended significantly by reducing the drain current during a short-circuit event. The devices were shown to withstand a short-circuit event for considerably longer period with an elevated initial junction temperature as a result of lower drain current. With short-circuit current reduced from 110 A to 70 A, the withstand time was increased from 215 ns at 25°C to over 10 μs at 150°C and Vdc= 400 V. A gate-sensing protection scheme for GaN GIT was evaluated over various operating conditions and shown to successfully protect devices in less than 150 ns after short-circuit condition up to Tj = 150°C and Vdc= 500 V.

A fast and reliable overcurrent protection scheme is crucial for the converter reliability. It is also critical for double pulse test stations where newer devices or even engineering samples are tested, and device failures can be costly. A fast overcurrent protection scheme using the direct current measurement in the double pulse test is demonstrated and 7.55 ns fault response delay time is achieved. The total fault clearing time is determined by the fault signal propagation and device switching speed. Around 100 ns and 60 ns fault clearing time is achieved for SiC and GaN devices, respectively. The much faster protection can potentially simplify the gate driver design and reduce the energy rating of the coaxial shunt resistor. Since the overcurrent detection is directly attached to the current measurement, its impact on the measurement bandwidth is also discussed.

In this paper, a variable frequency soft-switching control for a three-level half bridge (TLHB) buck converter is proposed to achieve wide-range output battery charging function without losing zero voltage switching (ZVS) or high efficiency. The adopted variable frequency triangle-current-modulation (TCM) is based on dc measurement and average-model calculation, thus able to realize ZVS operation fully digitally without current zero-crossing-detection (ZCD) circuits. A top-level average current or output voltage feedback controller further ensures the desired power or output voltage regulation. Experimental results from a GaN based TLHB prototype have shown the reliable TCM control and smooth transition of ZVS operation through the charging procedure.

An analytical model for the device drain-source turn-on overvoltage in three-level active neutral point clamped (3L-ANPC) converters is established in this paper. Considering the two commutation loops in the converter, the relationship between the turn-on overvoltage and the loop inductances is evaluated. The line switching frequency device usually exhibits higher overvoltage, while the high switching frequency device is not strongly influenced by the multiple loops. A 500 kVA 3L-ANPC converter using SiC MOSFETs is tested, and the model is verified with the experimental results.

In paralleled voltage source inverters (VSI), circulating current has both high frequency and low frequency components, and its spectrum highly depends on the modulation scheme. Previous research has mostly focused on the circulating current suppression for paralleled two-level VSIs. Little literature exists on similar analysis for paralleled three-level VSIs using space vector modulation. A detailed circulating current spectrum on full frequency range has not been well developed. This paper presents an improved analytical model for three-level space vector modulation (SVM), considering the impacts of regularly sampled reference and dead time. Then, circulating harmonic currents are determined across the full frequency range for various interleaving angles of two three-level ANPC inverters. The calculated harmonics are also verified by experimental results.

With conventional voltage source gate drives (VSG), the switching speed of SiC MOSFETs is difficult to increase due to large internal gate resistance, high Miller voltage, and limited gate voltage rating. This paper analyzes the requirement of current source gate drive (CSG) for SiC MOSFETs and proposes a CSG that can improve the switching speed and reduce switching loss. With the introduction of bi-directional switches, the influence of the large internal gate resistance of the SiC MOSFET can be mitigated, and sufficient gate current can be guaranteed throughout the switching transient. Therefore, the switching time and loss is reduced. The CSG can be controlled to be a VSG during steady state so the current of the gate drive is discontinuous and the stored energy of the inductor can be returned to the power supply to reduce gate drive loss. Double pulse tests are conducted for a SiC MOSFET with both conventional VSG and the proposed CSG. Testing results show that the switching loss of the proposed CSG is less than one third of the conventional VSG at full load condition.

High power inverters will be a key enabler for future aircraft based on hybrid electric or turbo-electric propulsion as envisioned by NASA and Boeing. Cooling a power electronics converter to low temperature, e.g. using cryogenic cooling, can significantly improve the efficiency and power density of a power conversion system. This paper presents the design of a MW cryogenically-cooled power inverter for electric aircraft applications. The power semiconductor and magnetic component characterization, inverter topology and power stage design, modulation and control, EMI noise reduction and filters design, and cooling system design are illustrated. A MW-level inverter prototype has been assembled and tested. The experimental results verify the functionality of the inverter.

Paralleling power electronics inverters is an effective way to increase dc-ac system power level. Accurately synchronized switching action and independent closed-loop regulator are necessary to prevent circulating current in paralleled inverters. There are many challenges for the controller design, when the number of paralleled inverters is large, and control period gets short for high switching frequency applications. This paper presents a single controller design based on DSP + FPGA that is suitable for paralleling multiple inverters. A simple synchronization scheme between DSP and FPGA based on universal parallel port (UPP) is proposed to eliminate the synchronization delay among inverters, and independent control of each converter can also be implemented. The controller is built for a system consisting of 4 paralleled three-level, three-phase high frequency ANPC inverters using space vector modulation, and it can be easily adopted to other topologies and modulations. Experimental results have demonstrated the effectiveness of this controller.

The adoption of SiC devices in high power applications enables higher switching speed, which requires lower circuit parasitic inductance to reduce the voltage overshoot. This paper presents the design of a busbar for a 500 kVA three-level active neutral point clamped (ANPC) converter. The layout of the busbar is discussed in detail based on the analysis of the multiple commutation loops, magnetic canceling effect, and DC-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. The results match with each other, and the inductances of small and large loop are 6.5 nH and 17.5 nH respectively, which is significantly lower than the busbars of NPC type converters in other references.

The four-leg topology has been applied to two-level inverters for common-mode (CM) noise elimination. To achieve zero common-mode voltage (CMV), the zero vector typically used in the two-level inverter is not allowed. As a result, the reference cannot be synthesized by nearest three vectors, which introduces a penalty in dc voltage utilization and current THD. This paper applies the fourth-leg to three-level neutral point clamped (NPC) inverter fed motor drives. Unlike the case in the two-level inverter, the reference can be synthesized by the nearest three vectors while zero CMV can be achieved at the same time in a three-level inverter with the fourth-leg. The topology and modulation are presented. The fourth-leg filter structures are investigated, and a fourth-leg filter structure which decouples the fourth-leg from the main circuit power level is proposed for high power applications. The experiment results on a three-level NPC inverter show that with the fourth-leg and presented modulation applied, the CM noise has been significantly reduced, and around 25 dB attenuation can be observed at the first noise peak in the electromagnetic interference (EMI) frequency range.

This paper presents a comprehensive analytical analysis of the ac and dc side harmonics of the three-level active neutral point clamped (ANPC) inverter with space vector modulation (SVM) scheme. An analytical model to calculate the harmonics of a three-level converter with SVM is developed. The ac side output voltage harmonics and dc side current harmonics characteristics are calculated and analyzed. With the developed models, the impact of interleaving on both sides harmonics are studied which considers the modulation index, interleaving angle, and power factor. The analysis provides guideline for interleaving angle optimization to reduce the ac side power filter and dc side dc-link capacitor. The relationship between electromagnetic interference (EMI) filter corner frequency and switching frequency is also analytically derived which provides guideline for switching frequency and EMI filter design optimization. Two paralleled three-level ANPC inverters are constructed and experimental results are presented to verify the analytical analysis.

With the development of wide band-gap (WBG) technology, the switching speed of power semiconductor devices increases, which makes circuits more sensitive to parasitics. For three-level active neutral point clamped (3L-ANPC) converters, the over-voltage caused by additional non-active switch loop can be an issue. This paper analyzes the multiple commutation loops in 3L-ANPC converter and summarizes the impact factors of the device over-voltage. The nonlinearity of the output capacitance of the device can significantly influence the over-voltage. A simple control without introducing additional hardware circuit or complex software algorithm is proposed to attenuate the effect of the nonlinear output capacitance. Multi-pulse test is conducted for a 3L-ANPC converter built with silicon carbide (SiC) MOSFETs. With the proposed control, the testing results show that the peak drain-source voltage of both active and non-active switches is reduced by more than 20% compared to the conventional control.

This paper presents the coupled inductor design for interleaved three-level active neutral point clamped (ANPC) inverter considering electromagnetic interference (EMI) noise reduction. Compared to two-level case, the scenarios involved in the three-level space vector modulation (SVM) are more complicated when analyzing the volt-seconds of the coupled inductor for paralleled three-level inverter. At system level, the purpose of converter interleaving is to reduce EMI noise and ripple current in most applications, and coupled inductor design should consider the needs of EMI noise reduction and EMI filter design. These issues are discussed in this paper. The relationship between circulating current and EMI noise is illustrated. EMI filter corner frequency as a function of interleaving angle is analytically derived, and optimal interleaving angle for maximum common-mode (CM) filter and differential-mode (DM) filter corner frequencies is discussed. Coupled inductor design methodology for interleaved three-level inverters with SVM is then presented. Experiments on two interleaved ANPC inverters are conducted. The results verify the coupled inductor design. With the derived optimal interleaving angle, the CM and DM EMI noise are significantly reduced.

This paper presents harmonic analysis of common-mode reduction (CMR) modulation for three-level voltage source inverters. The analytical model to calculate the harmonics of CMR modulation with arbitrary PWM sequence is developed. The impact of alternative PWM sequences of CMR modulation on harmonics is investigated. New three-state and four-state PWM sequences of CMR are proposed which spread the energy centered in the carrier frequency in the conventional CMR, and thus reduce the voltage peaks in frequency domain. Experiments are conducted on a three-level neutral point clamped inverter. Experiment results verify the developed analytical model and harmonic analysis.

The modular multilevel converter (MMC) is regarded as a competitive choice for future dc grids at high and medium voltage levels. To study the dc grid stability, a few MMC dc impedance models have been proposed, but their accuracy is limited by the assumption of ideal submodule voltage or neglecting the circulating current control. In this paper, a more accurate MMC dc impedance model is developed considering both the submodule capacitor voltage and circulating current dynamics. Simulation and experiment results indicate that the developed model matches with the actual MMC better than state-of-art models and can predict the dc system stability correctly.

The performance of the gate drive power supply (GDPS) greatly impacts the safety and reliability of the gate drive for power semiconductor power devices. This paper focuses on the design of isolated gate driver power supply for 10 kV silicon-carbide (SiC) MOSFET for medium-voltage (MV) applications. Different insulation schemes are compared for the high-voltage insulated transformer in GDPS. Impact factors for transformer interwinding capacitance are analyzed, with which, a low inter-winding capacitance design approach is proposed for the high-voltage insulated transformer. Furthermore, an upward-voltage-reference based voltage regulation scheme is proposed for achieving good load regulation without output voltage feedback. Finally, a 20-kV-insulated GDPS is built and tested, and experimental results are presented to verify the effectiveness of the design approach.

The newly emerged 10 kV MOSFETs will be a game changer for the next generation medium-voltage (MV) power converters. While the unique feature of the fast switching speed benefits the development of high efficiency and high power-density MV converters, high dv/dt will be imposed on the power devices and passive components, which will result in accelerated insulation degradation and extreme EMI. This paper investigates the high dv/dt resulting from dead-time insertion in the modular multilevel converter (MMC). For reducing dv/dt, a multiple-step commutation scheme is proposed, in which, the submodules that transfer from bypass-state to insert-state are one-by-one commutated with those transferring from insert-state to bypass-state before the remaining unpaired submodules. Finally, the proposed multiple-step commutation scheme is verified on a single-phase MMC with 10-kV SiC MOSFET.

To overcome the limitations of digital simulation (numerical oscillation, limited computing capability of processors, etc.), a converter-based hardware test-bed was developed at CURENT for real-time power grid emulation. However, distribution systems especially microgrids cannot be emulated and tested on the existing hardware test-bed. This paper develops a microgrid test-bed based on the existing hardware test-bed to enable controller testing for microgrids with dynamic boundary. The design and realization of the microgrid hardware test-bed are introduced. The experimental results of the microgrid controller tests are also provided.

Medium voltage (MV) power converters using high voltage (HV) Silicon Carbide (SiC) power semiconductors result in great benefits in weight, size, efficiency and control bandwidth. However, challenges still exist on the components design considering HV insulation and noise immunity requirements in the MV SiC based power converter. A 5-level MMC based transformer-less grid-connected dc/ac converter is developed for 13.8 kV medium voltage grid using 10 kV SiC MOSFETs. The key components, including gate driver with high dv/dt immunity and fast reliable protection, isolated power supply with low parasitic capacitance, voltage/current sensors with high noise immunity, and passives following related insulation standard are provided. A 25 kV dc-link phase-leg is demonstrated, and the experimental results are presented.

This paper focuses on the design and testing of a half bridge submodule based on discrete 10 kV/20 A SiC MOSFETs for a modular multilevel converter (MMC). The rated dc bus voltage of the submodule is 6.5 kV, and the MOSFETs switch with dv/dt up to 100 V/ns. Design considerations and challenges for components in the submodule are presented, especially the gate driver to support the robust continuous operation and the submodule voltage sensor. Systematic testing procedures are developed to fully test the submodule up to 6.5 kV. High voltage insulation and high dv/dt are tackled throughout the design and testing. The designed submodule is validated in the continuous switching test at 6.5 kV with dv/dt up to 100 V/ns.

Virtual synchronous generator control provides a potential solution to connect power electronics interfaced sources to the power system. With its flexible control, the emulated inertia may be adaptively changed to enhance system small-signal stability. However, previously proposed methods may have adverse impact to system transient stability. This paper proposes to improve the methods by using wide-area measurements, namely center of inertia frequency. Experimental results are presented to both demonstrate the limitations of previous control schemes, and the effectiveness of the proposed one. The practical implementation of this method is discussed.

This paper focuses on the testing approach and validation of a 10 kV SiC MOSFET based Modular Multilevel Converter (MMC) phase-leg meant to interface to a 13.8 kV microgrid. Many of the difficulties associated with testing high-voltage SiC converters are shared regardless of topology, thus the testing setup and challenges associated with it are emphasized while the converter is only briefly summarized. Each component is individually verified, and the entire system is tested up to its rated dc link voltage and power, 25 kV and 35 kVA, respectively.

A microgrid with dynamic boundary can expand or shrink its boundary depending on available local distributed energy resources (DER). Compared to conventional microgrid with fixed boundary, it can lead to better DER utilization and improved reliability. Previous literature has only considered the operation of a microgrid with a single island that is energized by stable voltage sources. This paper introduces control function designs that can effectively synchronize islands inside a dynamic boundary microgrid, depending on the operation status of each voltage source inside the islands. An overview of the components and rationale within the control function designs is provided, and hardware-in-the-loop simulation results are analyzed to demonstrate the effectiveness of the control functions.

The paper aims to resolve the converter loss discrepancy between calculation and testing results by considering five factors: impacts of parasitic capacitance on switching loss, parameter variation of devices, time-varying power dissipation and junction temperature, thermal modeling using Finite Element Analysis, and some practical issues of the passive components. A 4.5 kW hard-switching inverter prototype using GaN devices was used as an example to demonstrate the improvement of loss model. The results show that after considering the above factors, loss discrepancy reduces from 35.7 W (35%) to 1.4 W (4%) at heavy load and, from 3.9 W (28%) to 2.6 W (less than 16%) at light load.

This paper proposes an adaptive control strategy for passivity or phase compensation of inverter output admittance or impedance based on online detection of resonance frequency, so that inverters can be stably integrated into power grids with unknown system information or time-varying structures. The resonance frequency is detected by online fast Fourier transform (FFT) analysis of inverter current within the inverter controller. The passivity of output admittance of current-controlled inverters at the resonance frequency is compensated by emulating a virtual parallel resistor through an additional voltage feed-forward path with a band-pass filter. The phase of output impedance of voltage-controlled inverters at the resonance frequency is compensated by inserting a notch filter in the current feed-forward path. Experimental results validate the effectiveness of the proposed adaptive impedance compensation method in resonance damping and stable integration of inverters into unknown systems.

For medium to high power application, due to the soft saturation and relatively higher saturation flux density, the powder and amorphous cores are commonly chosen for the DM inductors to achieve high power density in the EMI filter design. One of the issues of these materials is their permeability variation with operating current bias. Even for ac application, the three-phase currents at different switching cycles during one line cycle varies greatly, which leads to a variable DM inductance at different time intervals during one line cycle. Since the three-phase system has the unequal instantaneous currents for three phases, current-bias dependent permeability will cause the unbalanced DM inductance/impedance which converts DM noise to CM noise, also called mixed-mode (MM) noise. In this paper, the characteristics of current-bias dependent permeability are investigated for several commonly adopted DM core materials. In addition, a time domain variable inductance model considering current-bias characteristics is developed and applied to evaluate its impacts on the CM noise and the CM filter design. The phenomenon and proposed model are experimentally verified on a 10 kW three-level ANPC converter.

The accurate leakage inductance modeling of common mode chokes (CMCs) can reduce trial-and-error filter debugging efforts and help avoid the saturation issue caused by the leakage flux. However, the analytical leakage inductance model is difficult to derive due to the complex leakage flux distribution. This paper presents a data-driven approach to model the CMC leakage inductance. A large amount of the leakage inductance data is collected by sweeping the selected input variables for the 3D finite element method (FEM) simulation. Then the data is trained by Artificial Neutral Network (ANN) to regress the nonlinear relationship between the leakage inductance and selected input variables. To verify the proposed method, core ZW4310TC is selected to model the relationship between the leakage inductance and winding parameters. Three CMCs with core ZW4310TC were built with different winding parameters and their leakage inductances were measured to verify the model. Compared with a previous analytical model, the error was reduced from 42.9% to 1.3% at the case where the previous model has the worst accuracy.

Coaxial shunt resistors are very useful for measuring the ultra-fast current in wide-bandgap device switching transients. One of their major drawbacks is the relatively large parasitic inductance. The traditional coaxial shunt resistors are reviewed and the relationship between energy rating and parasitic inductance is determined. The parasitic inductance can be greatly reduced with a lower energy rating. A measurement method for characterizing their up to GHz bandwidth is also reported. Lower than expected bandwidth was observed and a fix using measured transfer characteristics is therefore described.

This paper proposes a simple and accurate design method for air gapped inductors. Using inductor models with fringing effect, the proposed method systematically evaluates possible combinations of cores, turn numbers, and air gap lengths within the given constraints, including core geometries and magnetic saturation. Design examples show that the proposed method reduces the number of turns as well as the core size compared to the conventional methods. The method features simplicity in both algorithm and calculation since it only requires a small number of iteration loops. Various models involved in inductor design, including inductance, flux density, loss and thermal, can be readily incorporated into the proposed method.

Sorting algorithm is required for operating modular multilevel converter (MMC) with nearest level modulation, to keep the unbalanced submodule capacitor voltage within an acceptable range. Several sorting algorithms have been proposed in previous literatures. However, very few papers discussed about how to select the execution frequency of a sorting algorithm. This paper aims to investigate on the impact of the execution frequency in sorting algorithm on the output voltage harmonics, average switching frequency, submodule capacitor voltage fluctuation of an MMC using nearest level modulation. Multiple MMC models with different number of submodules are built in MATLAB/Simulink. Three different types of sorting algorithms are implemented, and evaluated at various execution frequencies as well as different operating points. Conclusions drawn from the extensive simulations show that to select a sorting algorithm and its execution frequency, all three performance criterions should be considered simultaneous and a minimum execution frequency is always required.

Wide bandgap (WBG) semiconductor devices and cryogenic cooling are key enablers for highly-efficient ultra-dense power electronics converters, which are critical for future more electric aircraft applications. For the development and optimization of a cryogenically-cooled converter, an understanding of power semiconductor characteristics, especially for emerging WBG devices, is critical. This paper focuses on WBG device characterization at cryogenic temperatures. First, the testing setup for cryogenic temperature characterization is introduced. Then several WBG device candidates (e.g., 1200-V SiC MOSFETs and 650-V GaN HEMTs) are characterized from room to cryogenic temperatures. The test results are presented with trends summarized and analyzed, including on-state resistance, breakdown voltage, and switching performance.

Switching transient overvoltage is inevitable in hard switching applications, and the faster switching speed of SiC MOSFETs suggests even worse overvoltage. This paper focuses on the turn-on overvoltage. To understand its nature, the switching transient is analyzed, and it shows the turn-on overvoltage is largely independent of load current condition. This phenomenon is verified by characterizing the turn-on overvoltage of a SiC MOFET and a SiC Schottky diode. Finally, a SPICE-based model is also built to understand the switching transient more accurately, and the modeling method can accurately predict the turn-on overvoltage and help select device voltage rating.

Dead-time, device output capacitance, and other non-ideal characteristics cause voltage error for the midpoint PWM voltage of the semiconductor phase-leg employed in a voltage-source inverter (VSI). Voltage-second balancing is a well-known concept to mitigate this distortion and improve converter power quality. This paper proposes a unique voltage-second balancing scheme for a SiC based voltage source inverter using online condition monitoring of turn-off delay time and drain-source voltage rise/fall time. This data is sent to the micro-controller to be used in an algorithm to actively adjust the duty cycle of the input PWM gate signals to match the voltage-second of the non-ideal output voltage with an ideal output voltage-second. The monitoring system also allows for this implementation to eliminate the need for precise current sensing and allows for the implementation to be load independent. Dynamic current sensing is still a developing technology, and each load has a unique effect on the output voltage distortion. Test results for a 1 kW half-bridge inverter implementing this monitoring system and voltage-second balancing scheme show a 70% enhancement on the error against the ideal fundamental current value of the output current and a 2% THD improvement on the output current low frequency harmonics.

In this paper, an extra junction capacitance and its associated switching commutation path are identified in three-level ac/dc converters, which were previously overlooked due to the off-state of the related device in half line cycle. The impact of this effect on power loss is analyzed, showing an underestimated switching loss in the traditional loss calculation of three-level converters. Through a proposed loss re-evaluation approach based on energy data of conventional double pulse tester (DPT), the corrected loss matches experimental results obtained from a 450kHz 650 V Gallium Nitride (GaN) based Vienna-type rectifier, showing 17.4% additional switching loss due to this effect. And the dominant extra switching loss is found to be Coss loss instead of overlap loss in WBG converters. Thefore, the effect is severe in high swtiching frequency high-speed wideband gap (WBG) based three-level converters.

As wide bandgap (WBG) semiconductors are gradually adopted for high switching frequency high power-density power converter, new challenges arise from control to hardware design. In this paper, an improved input current sampling method is proposed for three-phase rectifiers to avoid sampling noises when rectifiers are operated at high speed and high switching frequency. Experimental results obtained from a 450-kHz enhancement-mode Gallium Nitride (GaN) high-electron-mobility transistor (HEMT) based three-phase three-level Vienna-type rectifier demonstrate the good performance of the sampling method.

Data centers consume an ever-increasing amount of electricity because of the rapid growth of cloud computing and digital information storage. A high voltage point of load (HV POL) converter is proposed to convert the 400-VDC distribution voltage to 1-VDC within a single stage to increase the power conversion efficiency. A six-phase input series output parallel (ISOP) connected structure is implemented for the HV POL. The symmetrical controlled half bridge current doubler is selected as the converter topology in the ISOP structure. The full load efficiency is improved by 4% points compared with state of the art products. A voltage compensator has been designed in order to meet the strict dynamic voltage regulation requirement. A laboratory prototype has been built, and experimental results have been provided to verify the proposed HV POL with a single power conversion stage can meet the dynamic voltage regulation requirement for an on-board power supply with higher efficiency compared to the conventional architecture.

Although SiC MOSFETs show superior switching performance compared to Si IGBTs, it is unknown whether SiC MOSFETs have the same advantage over Si super junction (SJ) MOSFETs such as CoolMOS. This paper analyzes the switching performance in different switching cell configurations and summarizes the impact factors that influence switching loss. A double pulse test is conducted for a SiC MOSFET and a CoolMOS with the same voltage and current rating. In the FET/diode cell structure, a SiC Schottky diode is used as the upper device to eliminate the reverse recovery, and the testing results show that the SiC MOSFET has 2.4 times higher switching loss than the Si CoolMOS. This can be explained by the smaller transconductance and the higher Miller voltage of the SiC MOSFET. On the other hand, the Si CooMOS has 10 times higher switching loss than the SiC MOSFET in the FET/FET cell structure because of the significant turn-on loss caused by the poor reverse recovery of its body diode.

Due to the low availability, high cost, and limited performance of high voltage power devices in high voltage high power applications, series-connection of low voltage switches is commonly considered. Practically, because of the dynamic voltage unbalance and the resultant reliability issue, switches in series-connection are not popular, especially for fast switching field-effect transistors such as silicon (Si) super junction MOSFETs, silicon carbide (SiC) JFETs, SiC MOSFETs, and gallium nitride (GaN) HEMTs, since their switching performance is highly sensitive to gate control, circuit parasitics, and device parameters. In the end, slight mismatch can introduce severe unbalanced voltage. This paper proposes an active voltage balancing scheme, including 1) tunable gate signal timing unit between series-connected switches with <; 1 ns precision resolution by utilizing a high resolution pulse-width modulator (HRPWM) which has existed in micro-controllers; and 2) online voltage unbalance monitor unit integrated with the gate drive as the feedback. Based on the latest generation 600-V Si CoolMOS, experimental results show that the dynamic voltage can be automatically well balanced in a wide range of operating conditions, and more importantly, the proposed scheme has no penalty for high-speed switching.

Understanding the CM inductor core saturation mechanism and reducing core flux density is critical for CM inductor design optimization. Instead of a time domain method, this paper introduces frequency domain spectrum concept for CM inductor core saturation analysis and design optimization, which will provide designers a better understanding of CM inductor design. First, both core permeability and converter modulation index's opposite influence on DM flux density and CM flux density are identified. Then, CM flux density is further investigated based on the spectrum concept. Three components in the CM inductor which may cause large CM flux density and core saturation are summarized: (1) switching frequency related components, (2) impedance resonance frequency related components, and (3) modulation frequency related components. Each component is investigated for CM flux density reduction and filter design optimization. A connecting AC and DC side midpoint with notch filter structure is proposed to reduce modulation frequency related components. Experiment results are presented to verify the proposed concept and method.

Attenuation performance of an EMI filter can be significantly degraded by coupling, parasitics, and frequency-dependent nonlinearity of magnetic cores. In this paper, the effect due to mutual capacitive coupling in filter structures with T-shape joint is identified and investigated. Its mechanism indicates that this coupling is the dominant cause of performance degradation in T-shape filters. PCB slits and grounded shielding are proposed as two effective mitigation solutions, respectively, and are further combined to improve filter transfer gain up to 40 dB along the high frequency range. Experimental results obtained from a three-phase LCL common-mode (CM) filter verify the significant impact of this coupling and the effectiveness of the proposed mitigation methods.

Superconducting technologies such as motors together with the supporting cryogenic power electronic system are growing in importance in aircraft applications. It is critical to understand the influence of low temperature on filters of the power converter system in these applications. Also, it is worthwhile to investigate whether the converter system can achieve higher efficiency and high power density by utilizing the provided low temperature cooling environment. This paper conducted a comprehensive magnetic core characterization at low temperature to understand the core properties and support filter design at low temperature. The ferrite and nanocrystalline material are characterized from room temperature to cryogenic temperature in a wide range of operating frequencies. The results show that the permeability of ferrite material decreases by a factor of 7~8 and the core loss increases more than 10 times when operating at very low temperature. The permeability of nanocrystalline material decreases to 60% and the core loss increases 1.5~2.5 times when operating at very low temperature. The saturation flux density of both materials has slight increase at low temperature. Based on tested data, a case study of inductor design considering the low temperature cooling environment is presented to illustrate the influence of low temperature on inductor design.

To operate a converter at cryogenic temperatures, understanding the characteristics of power semiconductor devices is critical. This paper presents the characterization of state-of-the-art 1.2 kV SiC MOSFETs from leading manufacturers at cryogenic temperatures. The testing setup consisting of a cryogenic chamber, and a liquid nitrogen Dewar is introduced. With a curve tracer and double pulse test, comprehensive characterization of the SiC MOSFETs including both static and switching performance is conducted and evaluated. Test results indicate the on-resistance increases while the breakdown voltage remains relatively constant at cryogenic temperatures. Other characteristics like threshold voltage and switching loss vary significantly at cryogenic temperatures among devices from different manufacturers.

Zero sequence circulating current (ZSCC) exists when paralleled inverters have common dc and ac sides without isolation. Most of the prior work on the ZSCC analysis and suppression depended on paralleled two-level inverters. The scenarios involved in the three-level converters are more complicated. This paper investigates the ZSCC in paralleled three-level active neutral point clamped (ANPC) inverters. The mechanisms causing potential ZSCC jump in three-level paralleled ANPC inverters are analyzed. The ZSCC patterns of different interleaved modulation schemes for three-level converters are illustrated. Then, the active vector dividing concept is extended to three-level converters, and a modulation scheme is proposed to reduce the high frequency ZSCC in three-level converters. Experiments have been conducted on two paralleled three-level inverters. The current jump in ZSCC is observed and mitigated. The ZSCC with proposed modulation scheme is reduced to less than half of the ZSCC with conventional continuous space vector modulation (CSVM) scheme.

Unlike conventional passive or active filters, an impedance balancing circuit reduces the common-mode (CM) electromagnetic interference (EMI) noise by establishing an impedance balancing bridge. The EMI noise can be significantly reduced when the impedance bridge is designed to be well balanced. This paper investigates impedance balancing circuits in Dc-fed motor drive systems where both DC input and AC output need to meet EMI standards and thus EMI filters are needed for both sides. An impedance balancing circuit is proposed to reduce both DC and AC side CM noise. Two auxiliary branches are added to the conventional passive filters to establish an impedance bridge and reduce CM noise. The design criteria are presented, and the impact of the proposed impedance balancing circuit on both sides CM noise are investigated. It shows that the proposed impedance balancing circuit can reduce DC side and AC side CM noise based on different mechanisms. The CM noise reduction performance of the proposed method does not depend on the motor and cable models. Experiment results are presented to demonstrate the feasibility and effectiveness of the proposed method.

One of the popular converter topologies applied in high power dc-ac applications is the three-level active neutral point clamped (ANPC). Owing to relatively low switching frequency and slow switching speed of these topologies in high power applications, the commutation loop analysis in these topologies has not been fully conducted, and the over-voltage issue of non-active switches has not been thoroughly analyzed. This paper reveals an over-voltage issue on non-active switches in three level inverters due to multi-commutation loop. The detailed mode analysis during the commutation and related over-voltage issue are given. Finally, Si-based ANPC with 140 kHz switching frequency and SiC-based ANPC converters with 280 kHz switching frequency and high switching speed are tested respectively to compare and verify the over-voltage issue for non-active switches.

In order to evaluate the feasibility of newly developed GaN devices in a cryogenic-cooled converter, this paper characterizes a 650 V enhancement-mode Gallium-Nitride heterojunction field-effect transistor (GaN HFET) at cryogenic temperatures. The characterization includes two parts: static and dynamic characterization. The results show that this GaN HEMT is an excellent device candidate to be applied in cryogenic-cooled applications. For example, transconductance at cryogenic temperature is 2.5 times of one at room temperature, and accordingly, peak di/dt during turn-on transients at cryogenic temperature is around 2 times of that at room temperature. Moreover, the on-resistance of the channel at cryogenic temperature is only one-fifth of that at room temperature.

A power converter based transmission line emulator has been developed for the hardware test-bed (HTB) platform, which emulates power systems by mimicking the system components with universal three-phase voltage source converters. In power grids, transmission line series compensation devices are utilized to enhance the power delivery capability and controllability by regulating the equivalent impedance of a transmission line. This paper proposes a method of mimicking variable capacitors and inductors to combine the series compensation device emulation into the transmission line emulator so that various power system scenarios can be studied. Simulation and experiment results verify the effectiveness of the transmission line emulation with integrated series compensation devices.

To better utilize the existing electric power grid distribution network automation of smart switches, a microgrid can expand or shrink its electrical boundary according to available renewable generation. Previous literature only focused on the design of a microgrid with a dynamic boundary, but without considering real-time operation. This paper proposes a microgrid controller that enables operation of microgrid with dynamic boundary and can be integrated into the existing distribution automation system. The architecture of the control system is introduced, and the essential functions such as online topology assessment and synchronization are presented. Simulation results are given to demonstrate the feasibility of the proposed controller.

The short circuit performance of a 3rd generation 10 kV/20 A SiC MOSFET with short channel is characterized in this paper. The platform consisting of a phase-leg configuration, which can test both hard switching fault (HSF) and fault under load (FUL) types of fault, is introduced in detail. A Si IGBT based solid state circuit breaker is developed for short circuit test. The short circuit protection having a response time of 1.5 μs is validated by the test platform. The short circuit characteristics for both the HSF and FUL types at 6 kV DC-link are presented and analyzed.

Modular multilevel converters (MMCs) have been widely adopted for high voltage direct current (HVDC) applications and have been targeted for use in future dc grids as well. However, most of the MMC research is still limited to digital simulations or relied on hardware demonstrations with a specific setup and limited number of submodules (SMs). In this paper, a MMC test-bed with 10 SMs in each arm is developed that has flexible reconfiguration of the MMC topologies, switching frequencies, and passive element parameters. The MMC test-bed hardware construction, control scheme, and communication architecture are described, and typical MMC scenarios are conducted to verify its multiple functions.

In a converter based on 10 kV SiC MOSFETs, major sources of parasitic capacitance are the anti-parallel junction barrier schottky (JBS) diode, heat sink, and load inductor. A half bridge phase leg test setup is built to investigate these parasitic capacitors' impact on the switching performance at 6.25 kV. Generally these parasitic capacitors slows down both turn-on and turn-off transient and can cause significant increase in switching energy loss. The impact of the parasitic capacitor in the load inductor is analyzed, which has either very short wire or long wire in series. Switching performance of the phase leg with two different thermal designs are compared to investigate the impact of the parasitic capacitor due to the heat sink. The large parasitic capacitor due to the large drain plate of discrete 10 kV SiC MOSFET for heat dissipation can result in 44.5% increase in switching energy loss at low load current.

Practical distribution system contains many nodes and short branches. As a result, a more efficient and stable distribution state estimation (DSE) algorithm is needed to properly handle the inverse operation of its large-scale ill-conditioned information matrix. This paper proposed a two-stage DSE algorithm to transform the inverse operation into addition and multiplication operations in a recursive manner. It includes pseudo measurement preprocessing in the offline stage where an approximate linear estimator is adopted to relieve most of computation burdens, and real-time correction in the online stage where a nonlinear estimator is used to update the estimation. Numerical results of the method applied to both IEEE standard test systems and an actual distribution system show the accuracy and effectiveness of the proposed algorithm.

The frequency decoupling effect of the voltage source converter (VSC)-based high voltage dc (HVDC) transmission makes frequency support unavailable between two ac subsystems interconnected by the HVDC link. Recently, several algorithms have been proposed and demonstrated to improve the ac system stability by implementing inertia emulation (IE) functions in the HVDC VSC stations. However, the capability of the VSC-HVDC to achieve the IE control is not clear. According to the previous research, the IE control strategy has been studied without concerning the impact of the practical control process, which will introduce some time delay into the IE realization. In this paper, a detailed multi-terminal HVDC VSC control module, including the phase-locked loop (PLL) and low pass filter (LPF), is considered in order to analyze the multi-terminal HVDC network impact on the IE performance. The analysis indicates that the frequency performance of the ac network with IE integrated HVDC transmission can be nearly as good as that directly connected with the ac subsystem which involves a high penetration of conventional generation units, except for the short time delay introduced by the VSC control modules. The effectiveness of IE performance will be compromised if the response delay is significant. The simulation results have verified the analysis.

Battery energy storage systems (BESSs) are commonly used for frequency support services in power systems because they have fast response times and can frequently inject and absorb active power. Lithium-ion (Li-ion) BESSs dominate the grid energy storage market now, but Vanadium redox flow (VRB) BESSs are predicted to contend in future markets for large-scale storage systems. Previously, a Li-ion BESS emulator has been developed for a grid emulation system known as the Hardware Testbed (HTB), which consists of converters controlled to emulate different power system components. In this paper, we develop a VRB BESS emulator with a VRB-specific internal battery model and a power electronics interface similar to that of the Li-ion BESS emulator. Then, we compare the effectiveness of the VRB and Li-ion technologies for primary frequency regulation and inertia emulation applications. It is concluded that these two technologies are virtually indistinguishable from the power system's perspective when conducting these services over a short period of time.

The impact of the body diode and the anti-parallel junction barrier Schottky (JBS) diode on the switching performance of the 3rd generation 10 kV SiC MOSFET from Wolfspeed/Cree is investigated in detail at various junction temperatures. The switching performance with and without the anti-parallel JBS diode is tested by specific layout design of the 10 kV MOSFET module. The body diode of the 10 kV SiC MOSFET has excellent reverse recovery performance from 25°C to 125 °C, indicating it is a suitable candidate for freewheeling diode. The application of anti-parallel JBS diode will slow down the turn-off transient and result in lower turn-off dv/dt and higher turn-off energy loss, while its impact on the turn-on transient is not significant.

The dead-time in voltage source converters can have significant impact on power quality and efficiency, and because these losses scale proportionally with switching frequency, it is important to study the impact of these losses in wide bandgap based converters, like SiC and GaN. This paper focuses on the impact of dead-time on the total loss of a 5 kW, single phase, GaN-based inverter, and an experimental model of dead-time losses for various dead-times was developed based on static and dynamic characterization results. The results show that in a GaN-based voltage source inverter (VSI), a 100 ns dead-time setting can attribute up to 30% additional switching loss and is a strong function of load current level and temperature. A comparison of losses between fixed and adaptive dead-time was studied, and an optimal fixed dead-time setting based on the analysis was implemented and verified in experiment.

This paper presents a new boundary condition for designing phase legs when using the decoupling capacitance method. New SiC MOSFETs have much higher short-circuit currents-over 14X datasheet rating-then comparable Si IGBT devices. The energy draw on the decoupling capacitance due to this can be a large step input that over-voltages the device if not accounted for. Decoupling capacitance requirements have previously been based on switching conditions during normal operation and may not be sufficient for high current devices or modules. Furthermore, fast protection work has focused on lower current discrete devices whereas this issue becomes more prevalent in higher current configurations. Analysis of device over-voltage during short-circuit events is presented along with new sizing guidelines for DC link decoupling capacitance.

This paper presents the occurrence of potentially destructive oscillation in paralleled power MOSFETs during short-circuit events. Paralleling discrete power devices is desirable in many designs in order to increase power output. Short circuits cause high voltages, saturation current and local temperatures creating unstable environments within devices. Current redistribution can occur between device gates in this environment which can excite oscillation in parallel circuitry if not properly accounted for. Analysis of the phenomenon including experimental results are presented along with mitigation steps.

Middle-point inductance Lmiddle can be introduced in power module designs with P-cell/N-cell concept. In this paper, the effect of middle-point inductance on switching transients is analyzed first using frequency domain analysis. Then a dedicated multiple-chip power module is fabricated with the capability of varying Lmiddle. Extensive switching tests are conducted to evaluate the device's switching performance at different values of Lmiddle. Experiment result shows that the active MOSFET's turn-on loss will decrease at higher values of Lmiddle while its turn-off loss will increase. Detailed analysis of this loss variation is presented. In addition to switching loss variation, it is also observed that different voltage stresses are imposed on the active switch and anti-parallel diode. Specifically, in the case of lower MOSFET's turn-off, the maximum voltage of lower MOSFET increases as Lmiddle goes up; however, the peak voltage of anti-parallel diode decreases significantly. The analysis and experiment results will provide design guidelines for multiple-chip power module package design with P-cell/N-cell concept.

In this paper, a low parasitic inductance SiC power module with double-sided cooling is designed and compared with a baseline double-sided cooled module. With the unique 3D layout utilizing vertical interconnection, the power loop inductance is effectively reduced without sacrificing the thermal performance. Both simulations and experiments are carried out to validate the design. Q3D simulation results show a power loop inductance of 1.63 nH, verified by the experiment, indicating more than 60% reduction of power loop inductance compared with the baseline module. With 0Ω external gate resistance turn-off at 600V, the voltage overshoot is less than 9% of the bus voltage at a load of 44.6A.

This paper introduces a dead-time optimization technique for a 2-level voltage source converter (VSC) using turn-off transition monitoring. Dead-time in a VSC impacts power quality, reliability, and efficiency. Silicon carbide (SiC) based VSCs are more sensitive to dead-time from increased reverse conduction losses and turn-off time variability with operating conditions and load characteristics. An online condition monitoring system for SiC devices has been developed using gate drive assist circuits and a micro-controller. It can be leveraged to monitor turn-off time and indicate the optimal dead-time in each switching cycle of any converter operation. It can also be used to specify load current polarity, which is needed for dead-time optimization in an inverter. This is an important distinction from other inverter dead-time elimination/optimization schemes as current around the zero current crossing is hard to accurately detect. A 1kW half-bridge inverter was assembled to test the turn-off time monitoring and dead-time optimization scheme. Results show 91% reduction in reverse conduction power losses in the SiC devices compared to a set dead-time of 500ns switching at 50 kHz.

While fast switching brings many benefits, it also presents unwanted ringing during switching transient. In this paper, an increasing magnitude ringing phenomenon is observed during the MOSFET turn-off transient. The unusual phenomenon is replicated in simulation and it is found the MOSFET channel is turned on again after it is turned off. The major cause to this unexpected turn on is found to be common source inductance and a moderate 3 nH one in simulation replicates the severe self-turn-on ringing observed in experiment. This paper reveals the detrimental effect of common source inductance in fast switching. Therefore, Kelvin source connection in circuit and package design is strongly recommended.

Cooling a converter to low temperatures, e.g. using cryogenic cooling, can significantly improve the efficiency and density of a power conversion system. For the development and optimization of a cryogenically-cooled converter, an understanding of power semiconductor characteristics is critical. This paper focuses on the characterization of high-voltage, high-speed switching, power semiconductors at cryogenic temperature. First, the testing setup for cryogenic temperature characterization is introduced. Three testing setups are established for cryogenic switch characterization, including: 1) on-state resistance and forward voltage drop of the body diode, 2) leakage current and breakdown voltage, and 3) switching characteristics. For each testing set up, the corresponding testing configurations, hardware setups, and practical considerations are summarized. Additionally, the test results at cryogenic temperature are illustrated and analyzed for 650-V Si CoolMOS. It is then demonstrated that when the cryogenic temperature test results are compared to that of room temperature, the device performance varies significantly; for example: on-state resistance reduces by 63%, breakdown voltage drops by 31%, switching time decreases and switching energy loss decreases by 26%. Furthermore, the peak dv/dt during transient switching at cryogenic temperature exceeds 100 V/ns which is comparable to the emerging wide bandgap Gallium Nitride devices.

Silicon Carbine (SiC) based power semiconductor devices have increased voltage blocking capability, in the meantime, satisfactory switching performance as compared to conventional Silicon (Si) devices. This paper focuses on the latest generation 10 kV / 20 A SiC MOSFETs and investigates their protection schemes and temperature-dependent switching characteristics. A high voltage double pulse test platform is constructed including solid state circuit breaker, gate drive and hot plate under device under test (DPT) for temperature-dependent characterization. A behavioral model is established to analytically investigate switching performance of 10 kV SiC MOSFETs, and the temperature-dependent factors are studied in detail. The experimental results under various load currents and gate resistances from 25 C to 125 C at 7 kV dc-link voltage are presented.

Preparing power systems to better accommodate renewable energy sources has become increasingly more important as penetration levels rise, and energy storage systems are excellent for suppressing the fluctuations of renewable and for providing other ancillary services to the grid. The Hardware Testbed (HTB) is a novel converter-based grid emulator created for studying the needs associated with high renewable penetration, but the system currently lacks battery storage capability. This paper proposes a configurable Lead Acid and Lithium Ion battery storage emulator equipped with a two-stage power electronics interface, which is capable of independent active and reactive power control as well as inertia emulation. Each part of the emulator is described in detail, in terms of both the models used and the control algorithms governing them. The emulator's behavior is simulated, tested, and confirmed to function correctly with the HTB and will be used to study scenarios in which battery storage can be used to support renewables and other dynamic power system needs.

A hardware test-bed (HTB) has been developed to realize power system emulation by mimicking the system components with universal three-phase voltage source converters (VSCs). The VSC-based transmission line emulator has also been successfully developed to flexibly represent interconnected ac lines under normal operating conditions. As the most serious short-circuit fault condition, the three-phase short-circuit fault emulation is essential for power system studies. This paper proposes a model to realize the three-phase short-circuit fault emulation within the emulated transmission line. At the same time, a combination method is proposed to eliminate the undesired transients caused by the current reference step changes while switching between the fault state and normal state.

Hybrid ac/dc transmission can increase the power transfer capability of long ac transmission lines. High voltage dc (HVDC) converters are needed, and the line-commutated converter (LCC) is used considering the dc fault current controllability. However, zero-sequence current can be generated due to the coupled transmission lines, and it will flow into the HVDC converters as a fundamental frequency current component on dc side (i60). The LCC will convert i60 to dc current components on the ac side, which may cause potential converter transformer saturation. This paper analyzes the influence of coupled transmission lines on i60 and the converter transformer saturation and proposes two possible solutions to avoid converter transformer saturation. The simulation results verify the effectiveness of the proposed methods.

Multi-terminal dc (MTDC) grid has been considered as a promising future transmission and distribution system architecture, especially for remote renewable energy integration. However, short-circuit faults can be more detrimental to dc grids than ac grids. The lack of effective and economical dc circuit breakers and potential significant impact of dc fault on the connected ac system have become the main barrier for the dc grid application. This paper analyzes the major differences of dc grid and ac grid under short-circuit fault conditions. After that, the dc fault impact on the connected ac system is evaluated by comparing with an equivalent multi-terminal ac (MTAC) grid. Simulation results indicate that the dc fault impact on the connected ac system stability can be small if fast dc circuit breakers or full-bridge modular multi-level converters (MMCs) are employed. The impact of equivalent multiple ac faults on the connected ac system is small under the defined system scenarios.