The current limiting function enables the solid-state circuit breaker (SSCB) to have proper protection coordination. It allows sustained overcurrent for a certain period while preventing the fast fault current increase in dc systems. For the conventional method of using switches alone to limit the current, the high loss results in a short withstand time and low current limiting capability of the SSCBs. In this letter, a control strategy is proposed to utilize the energy absorption component to handle the major part of the energy during the current limiting stage to increase the current limiting capability for series-connected SSCB switching cells. The proposed method is experimentally verified to have more than 3X current limiting withstand time compared to the conventional control strategy in a case study.

High bandwidth sensors are required to measure the wide-bandgap devices' transient behavior because of their fast switching speed. In addition to high bandwidth, the current sensor must introduce little extra parasitic inductance to the switching power loop. The analysis of conventional shunt resistors shows the key to high bandwidth is the coaxial structure and its parasitic inductance is proportional to its transient heat energy rating. By combining the structure of coaxial shunt resistor and alumina substrate surface mount thin film resistors, a novel surface mount coaxial shunt resistor is introduced. Experimental measurement verifies its capability of achieving very high bandwidth while introducing very low parasitic inductance. The design can achieve up to 2.23-GHz measurement bandwidth while keeping its parasitic inductance as low as 0.12 nH. Application in gallium nitride heterojunction-field-effect-transistors double pulse test shows it can faithfully capture the transient current waveform while introducing little interference to the switching behavior.

This article establishes an analytical model for the device drain-source overvoltage related to the two loops in three-level active neutral point clamped (3L-ANPC) converters. Taking into account the nonlinear device output capacitance, two common modulation methods are investigated in detail. The results show that the line switching frequency device usually has higher overvoltage, and the switching speed of the high switching frequency device is not strongly influenced by the multiple loops. By keeping the nonactive clamping switch off, the effect of the nonlinear device output capacitance can be significantly mitigated, which helps reduce the overvoltage. Moreover, the loop inductance can be reduced with vertical loop layout and magnetic cancellation in the printed circuit board and busbar design. A 500-kVA 3L-ANPC converter using silicon carbide mosfets was built and tested. The experimental results validate the overvoltage model of the two modulation methods as well as the busbar design. With the nonactive clamping switch off, the overvoltage of both the high and line switching frequency devices is significantly reduced, which helps achieve higher switching speed.

In order to evaluate the feasibility of newly developed gallium nitride (GaN) devices in a cryogenically cooled converter, this article characterizes a 650-V enhancement-mode GaN high-electron mobility transistor (GaN HEMT) at cryogenic temperatures. The characterization includes both static and dynamic behaviors. The results show that this GaN HEMT is an excellent device candidate to be applied in cryogenic-cooled applications. For example, transconductance at cryogenic temperature (93 K) is 2.5 times higher than one at room temperature (298 K), and accordingly, peak di/dt during turn-on transients at cryogenic temperature is around 2 times of that at room temperature. Moreover, the ON-resistance of the channel at the cryogenic temperature is only one-fifth of that at room temperature. The corresponding explanations of performance trends at cryogenic temperatures are also given from the view of semiconductor physics. In addition, several device failures were observed during the dynamic characterization of GaN HEMTs at cryogenic temperatures. The ultrafast switching speed-induced high di/dt and dv/dt at cryogenic temperatures amplify the negative effects of parasitics inside the switching loop. Based on failure waveforms, two failure modes were classified, and detailed failure mechanisms caused by ultrafast switching speed are given in this article.

To better support the superconducting propulsion system in the future aircraft applications, the technologies of high-power high switching frequency power electronics systems at cryogenic temperatures should be investigated. This article presents the development of a 40-kW cryogenically cooled three-level active neutral point clamped inverter with 3 kHz output line frequency and 140 kHz switching frequency. Si mosfets are characterized at cryogenic temperatures, and the results show that they have promising performance such as lower on-resistance and switching loss. The design of the inverter is presented in detail with the special consideration of the cryogenic temperature operation. Moreover, a packaging and integration architecture is designed and fabricated to demonstrate the feasibility and performance of the inverter in the lab. It is able to achieve no leakage with good thermal and air insulation. With the inverter and packaging, the experimental results show that the inverter operates properly at cryogenic temperatures. The loss is measured at different load conditions, and the loss analysis is given, which shows that the cryogenically cooled inverter has 30% less loss than operating at room temperature.

Paralleling three phase three-level inverters is gaining popularity in industrial applications. However, analytical models for the harmonics calculation of a three-level neutral point clamped (NPC) inverter with popular space vector modulation (SVM) are not found in the literature. Moreover, how interleaving angle impacts the dc- and ac-side harmonics and electromagnetic interference (EMI) harmonics in parallel interleaved three-level inverters and how to optimize interleaving angle to reduce these harmonics have not been discussed in the literature. Furthering previous study, this article presents the modeling, analysis, and reduction of harmonics in paralleled and interleaved three-level NPC inverters with SVM. Analytical models for harmonic calculation are developed, and the dc-side harmonics characteristics of an NPC inverter are identified. The impact of interleaving angle on the ac-side voltage and dc-link current harmonics of parallel interleaved three-level NPC inverters is comprehensively studied. The impact of switching frequency and interleaving angle on EMI harmonics is also illustrated. Optimal interleaving angle ranges to reduce these harmonics are derived analytically. The developed models and harmonic reduction analysis are verified experimentally with two paralleled and interleaved three-level NPC inverters.

The attenuation performance of an electromagnetic interference filter can be significantly degraded by coupling, parasitics, and frequency-dependent nonlinearity, especially in high frequency (HF) range. This article reveals and investigates a mutual capacitive coupling effect in the popular filter structures with T-shaped joint. The mechanism is explained and the impact on filter attenuation is analyzed, which show this coupling is the dominant cause of performance degradation of T-shaped filters and a major cause for other T-shape-related filters. The effect patterns for both common-mode (CM) and differential-mode (DM) filters are analytically derived and further examined in multistage filter structures. Mitigation solutions using PCB slits and grounded shielding are proposed to improve filter transfer gain up to 30 dB in the HF range. A topological strategy is also presented, further enhancing filter attenuation. In addition, the impact of relative positions of the inductors on the coupling capacitance is discussed, and five positions are experimentally studied and compared. Experimental results obtained from three-phase LCL and LCLC filters verify the significance of this coupling and the effectiveness of the mitigation methods.

In order to apply power electronics systems to applications such as superconducting systems under cryogenic temperatures, it is necessary to investigate the characteristics of different parts in the power electronics system. This article reviews the influence of cryogenic temperature on power semiconductor devices including Si and wide bandgap switches, integrated circuits, passive components, interconnection and dielectric materials, and some typical cryogenic converter systems. Also, the basic theories and principles are given to explain the trends for different aspects of cryogenically cooled converters. Based on the review, Si active power devices, bulk Complementary metal-oxide-semiconductor (CMOS) based integrated circuits, nanocrystalline and amorphous magnetic cores, NP0 ceramic and film capacitors, thin/metal film and wirewound resistors are the components suitable for cryogenic operation. Pb-rich PbSn solder or In solder, classic printed circuit boards material, most insulation papers and epoxy encapsulant are good interconnection and dielectric parts for cryogenic temperatures.

This paper studies how an outer fractional winding can impact the equivalent parallel capacitance (EPC) of a differential-mode inductor, which is a critical passive component in a power electronic converter to combat with electromagnetic noises, and proposes a winding scheme that can reduce EPC and increase inductance, achieving both high-frequency filtering performance and high density. To perform these studies, a comprehensive layer capacitance model based on energy equivalence principle is established, which decouples EPC contribution among three elements, i.e., outer fraction layer, layer-to-layer, and layer-to-core, thus enabling the impact evaluation of different winding elements and schemes. Experimental comparison results have validated the accuracy of this EPC model and excellent performance of the proposed winding scheme with EPC reduction by 4×. It reveals that contrary to previous understanding, the inverse winding, in fact, is more effective for EPC reduction than the direct winding in most of the partial layer scenarios, and that by using this scheme with the outer fraction layer, 45% higher inductance and slightly less EPC can be achieved, compared to the single-layer winding design.

Three-level converters are more susceptible to parasitics compared with two-level converters because of their complicated structure with multiple switching loops. This paper presents the methodology of busbar layout design for three-level converters based on magnetic cancellation effect. The methodology can fit for 3L converters with symmetric and asymmetric configurations. A detailed design example is provided for a high power three-level active neutral point clamped (ANPC) converter, which includes the module selection, busbar layout, and DC-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. The results match with each other, and the inductances of short and long loops are 6.5 nH and 17.5 nH respectively, which are significantly lower than the busbars of NPC type converters in other references.

Middle-point inductance Lmiddle can be introduced in multiple-chip power module package designs. In this paper, the effect of middle-point inductance on switching transients is analyzed first using a frequency-domain analysis. Then a dedicated multiple-chip power module is fabricated with the capability of varying Lmiddle, and extensive switching tests are conducted to evaluate the middle-point inductance's impact. Experiment result shows that the active MOSFET's turn-on loss decreases at higher values of Lmiddle, while its turn-off loss increases. Detailed analysis of this loss variation is presented. In addition to the switching loss variation, it is also observed that different peak voltage stresses are imposed on the active switch and antiparallel diode during the switching transients. Specifically, in the case of lower MOSFET's turn-off, the maximum voltage of the lower MOSFET increases as Lmiddle goes up; however, the peak voltage of the antiparallel diode decreases significantly. The induced voltage spikes during upper MOSFET turn-on process is also evaluated, and an opposite trend is observed experimentally. Analysis of the voltage overshoot variation is discussed. Based on the experimental evaluation and analysis, a multiple-chip power module package design guideline is summarized considering the middle-point inductance's effect.

Parasitic ringing is commonly observed during the high-speed switching of wide band-gap (WBG) devices. Additional loss contributed by parasitic ringing becomes a concern especially for high switching frequency applications. This paper investigates the effects of parasitic ringing on the switching loss of WBG devices in a phase-leg configuration. An analytical switching loss model considering parasitics in power devices and application circuit is derived. Two switching commutation modes, gate drive dominated mode and power loop dominated mode, are investigated, respectively, and the switching loss induced by damping ringing is identified. It is found that this portion of the loss is at most the energy stored in parasitics, which always exists regardless of the switching speed and parasitic ringing. Therefore, with the given WBG device in the specific application circuit, damping more severe parasitic ringing during faster switching transient would not introduce higher switching loss. Additionally, the extra switching loss induced by resonance among parasitics and crosstalk is investigated. It is observed that severe resonance and its resultant over-voltage during the turn-on transient worsen the crosstalk, causing large shoot-through current and excessive switching loss. The theoretical analysis has been verified by the double pulse test with a 1200-V/50-A SiC-based phase-leg power module.

To understand the limitation of maximizing the switching speed of SiC low current discrete devices and high current power modules in hard switching applications, double pulse tests are conducted and the testing results are analyzed. For power modules, the switching speed is generally limited by the parasitics rather than the gate drive capability. For discrete SiC devices, the conventional voltage source gate drive (VSG) is not sufficient to maximize the switching speed even if the external gate resistance is minimized. The limitation of existing current source gate drives (CSG) are analyzed, and a CSG dedicated for SiC discrete devices is proposed, which can provide constant current during the switching transient regardless of the high Miller voltage and large internal gate resistance. Compared with the conventional VSG, the proposed CSG achieves 67% faster turnon time and 50% turn-off time, and 68% reduction in switching loss at full load condition.

This paper identifies extra junction capacitances and switching commutation loops introduced by line-frequency devices (i.e., non-active every other half line cycle) in three-level ac/dc converters and investigates the corresponding effects. Junction capacitances and power loops are well known as the key factors that impact converter switching loss and device stress, thus influence device selection, power stage layout, and thermal design. By examining switching transients of the commonly used T-shaped and I-shaped three-level converters, the cause and mechanism of the extra junction capacitances and power loops are presented. The impacts on switching loss, device voltage stress, and ac-side voltage/current distortion are respectively reported and analyzed. A loss calculation scheme for the three-level converter to include that extra loss is proposed. A power layout scheme to mitigate the device voltage stress is provided. Compensation and modeling of the voltage and current distortion are also proposed. Experimental results conducted on several types of three-level converter prototypes including a gallium nitride based 115 Vac/650 Vdc/1.5-kW/450-kHz Vienna-type rectifier and a SiC MOSFET based 1-kV/10-kW/ 280-kHz three-level active neutral-point-clamped inverter confirm the presented effects and verify the associated analysis and solutions.

Junction temperature is an important design/operation parameter, as well as, a significant indicator of device's health condition for power electronics converters. Compared to its silicon (Si) counterparts, it is more critical for silicon carbide (SiC) devices due to the reliability concern introduced by the immaturity of new material and packaging. This paper proposes a practical implementation using an intelligent gate drive for online junction temperature monitoring of SiC devices based on turn-off delay time as the thermo-sensitive electrical parameter. First, the sensitivity of turn-off delay time on the junction temperature for fast switching SiC devices is analyzed. A gate impedance regulation assist circuit is proposed to enhance the sensitivity by a factor of 60 and approach 736 ps/°C tested in the case study with little penalty on the power conversion performance. Next, an online monitoring unit based on gate assist circuits is developed to monitor the turn-off delay time in real time with the resolution less than 104 ps. As a result, the micro-controller is capable of “reading” junction temperature during the converter operation. Finally, a SiC-based half-bridge inverter is constructed with an intelligent gate drive consisting of the gate impedance regulation circuit and online turn-off delay time monitoring unit. Experimental results demonstrate the feasibility and accuracy of the proposed approach.

As wide-bandgap (WBG) devices and applications move from niche to mainstream, a new generation of engineers trained in this area is critical to continue the development of the field. This paper introduces a new hands-on course in characterization of WBG devices, which is an emerging and fundamental topic in WBG-based techniques. First, the lecture-simulation-experiment format based course structure and design considerations, such as safety, are presented. Then, the necessary facilities to support this hands-on course are summarized, including classroom preparation, software tools, and laboratory equipment. Afterward, the detailed course implementation flow is presented to illustrate the approach of close interaction among lecture, simulation, and experiment to maximize students' learning outcomes. Finally, grading for students and course evaluation by students are discussed, highlighting the findings and potential improvements. Detailed course materials are provided via potenntial.eecs.utk.edu/WBGLab for educational use.

A systematic study on a gallium nitride (GaN) high-electron-mobility transistor (HEMT) based battery charger, consisting of a Vienna-type rectifier plus a dc-dc converter, reveals a common phenomenon. That is, the high switching frequency, and high di/dt and dv/dt noise inside GaN converters may induce a dc drift or low frequency distortion on sensing signals. The distortion mechanisms for different types of sensing errors are identified and practical minimization techniques are developed. Experimental results on the charger system have validated these mechanisms and corresponding approaches, showing an overall reduction of input current total harmonic distortion (THD) by up to 5 percentage points and improved dc-dc output voltage regulation accuracy. The knowledge helps engineers tackle the troublesome issues related to noise.

Wide bandgap semiconductors are gradually being adopted in high power-density high efficiency applications, providing faster switching and lower loss, and at the same time imposing new challenges in control and hardware design. In this paper, a gallium nitride-based Vienna-type rectifier with SiC diodes is proposed to serve as the power factor correction stage in a high-density battery charger system targeting for aircraft applications with 800 Hz ac system and 600 V level dc link, where power quality is required according to DO160E standard. To meet the current harmonic requirement, PWM voltage distortion during the turn-off transient, is studied as the main harmonics contributor. The distortion mechanism caused by different junction capacitances of the switching devices is presented. A mitigation scheme considering the nonlinear voltage-dependent characteristics of these capacitances is proposed and then simplified from a pulse-based turn-off compensation method to a general modulation scheme. Simulation and experimental results with a 450 kHz Vienna-type rectifier demonstrate the performance of the proposed approach, showing a THD reduction from 10% to 3% with a relatively low-speed controller.

This paper presents an intelligent gate drive for silicon carbide (SiC) devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control gate voltages and gate loop impedances of both devices in a phase-leg configuration during different switching transients. Compared to conventional gate drives, the proposed circuit has the capability of accelerating the switching speed of the phase-leg power devices and suppressing the crosstalk to below device limits. Based on Wolfspeed 1200-V SiC MOSFETs, the test results demonstrate the effectiveness of this intelligent gate drive under varying operating conditions. More importantly, the proposed intelligent gate assist circuitry is embedded into a gate drive integrated circuit, offering a simple, compact, and reliable solution for end-users to maximize benefits of SiC devices in actual power electronics applications.

Dead time significantly affects the reliability, power quality, and efficiency of voltage-source converters. For silicon carbide (SiC) devices, considering the high sensitivity of turn-off time to the operating conditions (> 5× difference between light load and full load) and characteristics of inductive loads (> 2× difference between motor load and inductor), as well as large additional energy loss induced by the freewheeling diode conduction during the superfluous dead time (~15% of the switching loss), then the traditional fixed dead time setting becomes inappropriate. This paper introduces an approach to adaptively regulate the dead time considering the current operating condition and load characteristics via synthesizing online monitored turn-off switching parameters in the microcontroller with an embedded preset optimization model. Based on a buck converter built with 1200-V SiC MOSFETs, the experimental results show that the proposed method is able to ensure reliability and reduce power loss by 12% at full load and 18.2% at light load (8% of the full load in this case study).

The double pulse test (DPT) is a widely accepted method to evaluate the dynamic behavior of power devices. Considering the high switching-speed capability of wide band-gap devices, the test results are very sensitive to the alignment of voltage and current (V-I) measurements. Also, because of the shoot-through current induced by Cdv/dt (i.e., cross-talk), the switching losses of the nonoperating switch device in a phase-leg must be considered in addition to the operating device. This paper summarizes the key issues of the DPT, including components and layout design, measurement considerations, grounding effects, and data processing. Additionally, a practical method is proposed for phase-leg switching loss evaluation by calculating the difference between the input energy supplied by a dc capacitor and the output energy stored in a load inductor. Based on a phase-leg power module built with 1200-V/50-A SiC MOSFETs, the test results show that this method can accurately evaluate the switching loss of both the upper and lower switches by detecting only one switching current and voltage, and it is immune to V-I timing misalignment errors.

Research on high voltage (HV) silicon carbide (SiC) power semiconductor devices has attracted much attention in recent years. This paper overviews the development and status of HV SiC devices. Meanwhile, benefits of HV SiC devices are presented. The technologies and challenges for HV SiC device application in converter design are discussed. The state-of-the-art applications of HV SiC devices are also reviewed.

Gallium nitride (GaN) heterojunction field-effect transistors are an enabling technology for high-density converter design. This paper proposes a three-level dc-dc converter with dual outputs based on enhancement-mode GaN devices, intended for use as a battery charger in aircraft applications. The charger can output either 28 or 270 V, selected with a jumper, to satisfy the two most common dc bus voltage requirements in airplanes. It operates as an LLC converter in the 28 V mode and as a buck converter in the 270 V mode. In both operation modes, the devices can realize zero voltage switching (ZVS). With the chosen modulation method, the converter can realize automatic voltage balancing of the flying capacitor and the frequency doubling function to act as an interleaved converter. For the LLC mode, the resonant frequency is twice the switching frequency of primary-side switches, and for the buck mode, the frequency of the output inductor current is also twice the switching frequency. This helps to reduce the size of magnetics while maintaining a low switching loss. Also, the converter utilizes a matrix transformer, with resonant parameters designed to reduce conduction loss and avoid ZVS failure. The operating principle of the converter is analyzed and then experimentally verified on a 1.5-kW prototype with 1 MHz resonant frequency.

High power density is a desirable feature of power electronics design, which prompts economic incentives for industrial applications. In this paper, a gallium nitride (GaN)-based 2-kVA single-phase inverter design was developed for the Google Little Box Challenge, which achieves a 102-W/in3 power density. First, the static and dynamic temperature-dependent characteristics of multiple SiC and enhancement-mode GaN FETs are investigated and compared. Based on the device testing results, several topologies of the inverter stage and different power decoupling solutions are compared with respect to the device volume, efficiency, and thermal requirements. Moreover, some design approaches for magnetic devices and the implementation of gate drives for GaN devices are discussed in this paper, which enable a compact and robust system. Finally, a dc notch filter and a hard switching full-bridge converter are combined as the proposed design for the prototype. A 2-kVA prototype is demonstrated, which meets the volume, efficiency, and thermal requirements. The performance of the prototype is verified by the experimental results.

This paper overviews the silicon carbide (SiC) technology. The focus is on the benefits of SiC based power electronics for converters and systems, as well as their ability in enabling new applications. The challenges and research trends on the design and application of SiC power electronics are also discussed.

Double pulse test (DPT) is a widely accepted method to evaluate the switching characteristics of semiconductor switches, including SiC devices. However, the observed switching performance of SiC devices in a PWM inverter for induction motor drives is almost always worse than the DPT characterization, with slower switching speed, more switching losses, and more serious parasitic ringing. This paper systematically investigates the factors that limit the SiC switching performance from both the motor side and inverter side, including the load characteristics of induction motor and power cable, two more phase legs for the three-phase PWM inverter in comparison with the DPT, and the parasitic capacitive coupling effect between power devices and heat sink. Based on a three-phase PWM inverter with 1200 V SiC MOSFETs, test results show that the induction motor, especially with a relatively long power cable, will significantly impact the switching performance, leading to a switching time increase by a factor of 2, switching loss increase up to 30% in comparison with that yielded from DPT, and serious parasitic ringing with 1.5 μs duration, which is more than 50 times of the corresponding switching time. In addition, the interactions among the three phase legs cannot be ignored unless the decoupling capacitors are mounted close to each phase leg to support the dc bus voltage during switching transients. Also, the coupling capacitance due to the heat sink equivalently increases the junction capacitance of power devices; however, its influence on the switching behavior in the motor drives is small considering the relatively large capacitance of the motor load.

In a phase-leg configuration, the high-switching-speed performance of silicon carbide (SiC) devices is limited by the interaction between the upper and lower devices during the switching transient (crosstalk), leading to additional switching losses and overstress of the power devices. To utilize the full potential of fast SiC devices, this paper proposes two gate assist circuits to actively suppress crosstalk on the basis of the intrinsic properties of SiC power devices. One gate assist circuit employs an auxiliary transistor in series with a capacitor to mitigate crosstalk by gate loop impedance reduction. The other gate assist circuit consists of two auxiliary transistors with a diode to actively control the gate voltage for crosstalk elimination. Based on CREE CMF20120D SiC MOSFETs, the experimental results show that both active gate drivers are effective to suppress crosstalk, enabling turn-on switching losses reduction by up to 17%, and negative spurious gate voltage minimization without the penalty of decreasing the switching speed. Furthermore, both gate assist circuits, even without a negative isolated power supply, are more effective in improving the switching behavior of SiC devices in comparison to the conventional gate driver with a -2 V turn-off gate voltage. Accordingly, the proposed active gate assist circuits are simple, efficient, and cost-effective solutions for crosstalk suppression.

As the enabler of the direct current (DC) power distribution system, DC solid-state circuit breaker (DC-SSCB) has been extensively studied at the breaker-level (e.g., topology, energy absorption circuit, gate driver, and control) with limited system-level considerations, which is also crucial. This paper provides an all-in-one solution with integrated circuitries as the fault detector, actuator for semiconductor’s operating status regulation, and coordinated control to seamlessly transition from one mode to another (e.g., normal mode, precaution mode, i2t mode, and interruption mode). This allows the developed SSCB to limit system fault current not exceeding short-circuit current rating (SCCR) and take different responses under different fault cases. First, two improved fault detection circuits are introduced to better serve the SSCB application. Second, four operation modes are proposed for SSCB to realize system-friendly functions. Third, by leveraging four different operation modes, a control strategy is demonstrated to take different actions based on different fault cases. Finally, the feasibility and the effectiveness of the proposed system-friendly 200V/10A SSCB is validated with experimental results.

Gallium Nitride (GaN) high electron mobility transistors (HEMTs) are superior for cryogenically cooled solid-state circuit breakers (SSCBs) in future aircraft applications owing to their low on-resistance and high saturation current. However, during the high current turn-off, it is found that potential voltage and current ringing could happen to damage the device. In this paper, the turn-off failure mechanism of 650V/ 150A GaN bare dies are analyzed, which could be due to the instability of paralleled switching cells in one GaN bare die. A solution is proposed to use an RC snubber to reduce the overlap of $v_{ds}$ and $i_{d}$ in the turn-off process to avoid the unstable region where the hard-switching trajectory goes through. Experiments are conducted to verify the effectiveness of the proposed solution. With the reduced overlap between $v_{ds}$ and $i_{d}$, the GaN HEMT successfully turns off the 550 A objective current.

Operating power converters at cryogenic temperature (<-153°C) can improve efficiency and power density. However, the reliable operation of power converters depends on satisfactory performance of all critical components at cryogenic temperature. While most of the critical components have been studied at cryogenic temperatures, some electronic components necessary for electrical isolation in signal circuits of a medium voltage power converter are yet to be evaluated extensively. This work studies the cryogenic performance of isolated auxiliary power supplies (APS), digital isolators, fiber optics, and isolation amplifiers to identify the well-performing candidates and to investigate the possible reason of failures at cryogenic temperatures. It is observed that some isolated APS with high isolation voltage and isolation amplifiers can work satisfactorily at cryogenic temperatures. The digital isolators are found to be more suitable for cryogenic operation than fiber optic links, even though the latter has better noise immunity.

To increase the current interrupting capability for the DC solid-state circuit breaker (DC-SSCB), power semiconductors need to possess a higher pulse current. Moreover, for the power electronics protection system, it is also important to enable the system with a fault current limitation capability. Accordingly, this paper aims to design an intelligent gate drive for DC-SSCB, which can operate in cryogenic conditions to increase interrupting capability of the SSCB. Meanwhile, the proposed intelligent gate drive also enables the SSCB to operate in the current limitation mode to limit the overcurrent in the aviation system. The current limitation mode can help the aviation system limit the inrush current during startup and realize fault ride-through for the healthy part when the fault occurs. Finally, test results based on a 200V/150A SSCB with the current limitation mode prototype verify the proposed intelligent gate drive design for SSCB with cryogenic cooling.

The significant on-resistance reduction, the faster switching speed, and the capability of being operated at a higher current at cryogenic temperature make Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) attractive to cryogenically cooled power electronics applications. Moreover, the positive temperature coefficient of on-resistance makes GaN HEMTs suitable for the parallel operation. In this article, the design of a solid-state circuit breaker (SSCB) with two 650V/150A GaN HEMTs in parallel is presented. The designed SSCB circuit is tested at cryogenic temperature (<-153°C). -The results demonstrate the capability of the SSCB module with paralleled GaN-HEMTs to interrupt high current (1000A) at cryogenic temperature.

A solid-state circuit breaker (SSCB) needs to have very high efficiency comparable to its mechanical counterpart, and GaN offers highest conduction loss reduction at cryogenic temperatures. So, cryogenic cooling of future EAP is leveraged to design a 750V/100A SSCB module with an efficiency target higher than 99.9% and high over-current capability. The cryogenically cooled SSCB module design is developed in this paper, including key components selection and module design considerations. Experimental results are provided to validate the capability of the designed SSCB module to interrupt 10x of rated current at cryogenic temperatures (<-153°C).

Solid state circuit breaker (SSCB) with high efficiency and high gravimetric power density is required for Electrified Aircraft Propulsion (EAP). A cryogenically cooled GaN device based SSCB module is developed for EAP system. The SSCB module is suitable for medium voltage direct current (MVDC) applications and is designed with low-weight modular cold plates. Each module is rated for 750V, 100A and achieves a power density of 329 kW/kg. The design of the SSCB module structure, thermal design, and insulation design are discussed. Experimental results of interrupting an over-current fault of ~10x of the rated current by the SSCB module is provided to validate its operation at cryogenic temperature.

Junction temperature is one of the most critical indicators not only for the converter design and operation but also for power devices’ reliability. Online monitoring of junction temperature can provide useful information for converter control, protection, and maintenance. In this paper, an intelligent gate driver with online Tj monitoring capability is developed for SiC MOSFETs. The turn-on delay time is selected as the thermal sensitive electrical parameter (TSEP) for online Tj estimation. Moreover, a gate resistance regulation unit is implemented with 10 times sensitivity improvement to increase the measurement accuracy. Then, an edge-detection-based online turn-on delay time measurement with 200 ps resolution is designed and integrated into the gate driver. In the end, a double pulse test (DPT) platform is applied to collect the calibration curves offline. A SiC-based half-bridge inverter is also built to demonstrate the functionality and performance of the online junction temperature monitoring system. Resultantly, this intelligent gate driver can accurately estimate devices junction temperature during inverter operation.

A fast and reliable overcurrent protection scheme is crucial for the converter reliability. It is also critical for double pulse test stations where newer devices or even engineering samples are tested, and device failures can be costly. A fast overcurrent protection scheme using the direct current measurement in the double pulse test is demonstrated and 7.55 ns fault response delay time is achieved. The total fault clearing time is determined by the fault signal propagation and device switching speed. Around 100 ns and 60 ns fault clearing time is achieved for SiC and GaN devices, respectively. The much faster protection can potentially simplify the gate driver design and reduce the energy rating of the coaxial shunt resistor. Since the overcurrent detection is directly attached to the current measurement, its impact on the measurement bandwidth is also discussed.

In this paper, a variable frequency soft-switching control for a three-level half bridge (TLHB) buck converter is proposed to achieve wide-range output battery charging function without losing zero voltage switching (ZVS) or high efficiency. The adopted variable frequency triangle-current-modulation (TCM) is based on dc measurement and average-model calculation, thus able to realize ZVS operation fully digitally without current zero-crossing-detection (ZCD) circuits. A top-level average current or output voltage feedback controller further ensures the desired power or output voltage regulation. Experimental results from a GaN based TLHB prototype have shown the reliable TCM control and smooth transition of ZVS operation through the charging procedure.

In paralleled voltage source inverters (VSI), circulating current has both high frequency and low frequency components, and its spectrum highly depends on the modulation scheme. Previous research has mostly focused on the circulating current suppression for paralleled two-level VSIs. Little literature exists on similar analysis for paralleled three-level VSIs using space vector modulation. A detailed circulating current spectrum on full frequency range has not been well developed. This paper presents an improved analytical model for three-level space vector modulation (SVM), considering the impacts of regularly sampled reference and dead time. Then, circulating harmonic currents are determined across the full frequency range for various interleaving angles of two three-level ANPC inverters. The calculated harmonics are also verified by experimental results.

With conventional voltage source gate drives (VSG), the switching speed of SiC MOSFETs is difficult to increase due to large internal gate resistance, high Miller voltage, and limited gate voltage rating. This paper analyzes the requirement of current source gate drive (CSG) for SiC MOSFETs and proposes a CSG that can improve the switching speed and reduce switching loss. With the introduction of bi-directional switches, the influence of the large internal gate resistance of the SiC MOSFET can be mitigated, and sufficient gate current can be guaranteed throughout the switching transient. Therefore, the switching time and loss is reduced. The CSG can be controlled to be a VSG during steady state so the current of the gate drive is discontinuous and the stored energy of the inductor can be returned to the power supply to reduce gate drive loss. Double pulse tests are conducted for a SiC MOSFET with both conventional VSG and the proposed CSG. Testing results show that the switching loss of the proposed CSG is less than one third of the conventional VSG at full load condition.

Paralleling power electronics inverters is an effective way to increase dc-ac system power level. Accurately synchronized switching action and independent closed-loop regulator are necessary to prevent circulating current in paralleled inverters. There are many challenges for the controller design, when the number of paralleled inverters is large, and control period gets short for high switching frequency applications. This paper presents a single controller design based on DSP + FPGA that is suitable for paralleling multiple inverters. A simple synchronization scheme between DSP and FPGA based on universal parallel port (UPP) is proposed to eliminate the synchronization delay among inverters, and independent control of each converter can also be implemented. The controller is built for a system consisting of 4 paralleled three-level, three-phase high frequency ANPC inverters using space vector modulation, and it can be easily adopted to other topologies and modulations. Experimental results have demonstrated the effectiveness of this controller.

The adoption of SiC devices in high power applications enables higher switching speed, which requires lower circuit parasitic inductance to reduce the voltage overshoot. This paper presents the design of a busbar for a 500 kVA three-level active neutral point clamped (ANPC) converter. The layout of the busbar is discussed in detail based on the analysis of the multiple commutation loops, magnetic canceling effect, and DC-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. The results match with each other, and the inductances of small and large loop are 6.5 nH and 17.5 nH respectively, which is significantly lower than the busbars of NPC type converters in other references.

The four-leg topology has been applied to two-level inverters for common-mode (CM) noise elimination. To achieve zero common-mode voltage (CMV), the zero vector typically used in the two-level inverter is not allowed. As a result, the reference cannot be synthesized by nearest three vectors, which introduces a penalty in dc voltage utilization and current THD. This paper applies the fourth-leg to three-level neutral point clamped (NPC) inverter fed motor drives. Unlike the case in the two-level inverter, the reference can be synthesized by the nearest three vectors while zero CMV can be achieved at the same time in a three-level inverter with the fourth-leg. The topology and modulation are presented. The fourth-leg filter structures are investigated, and a fourth-leg filter structure which decouples the fourth-leg from the main circuit power level is proposed for high power applications. The experiment results on a three-level NPC inverter show that with the fourth-leg and presented modulation applied, the CM noise has been significantly reduced, and around 25 dB attenuation can be observed at the first noise peak in the electromagnetic interference (EMI) frequency range.

This paper presents a comprehensive analytical analysis of the ac and dc side harmonics of the three-level active neutral point clamped (ANPC) inverter with space vector modulation (SVM) scheme. An analytical model to calculate the harmonics of a three-level converter with SVM is developed. The ac side output voltage harmonics and dc side current harmonics characteristics are calculated and analyzed. With the developed models, the impact of interleaving on both sides harmonics are studied which considers the modulation index, interleaving angle, and power factor. The analysis provides guideline for interleaving angle optimization to reduce the ac side power filter and dc side dc-link capacitor. The relationship between electromagnetic interference (EMI) filter corner frequency and switching frequency is also analytically derived which provides guideline for switching frequency and EMI filter design optimization. Two paralleled three-level ANPC inverters are constructed and experimental results are presented to verify the analytical analysis.

With the development of wide band-gap (WBG) technology, the switching speed of power semiconductor devices increases, which makes circuits more sensitive to parasitics. For three-level active neutral point clamped (3L-ANPC) converters, the over-voltage caused by additional non-active switch loop can be an issue. This paper analyzes the multiple commutation loops in 3L-ANPC converter and summarizes the impact factors of the device over-voltage. The nonlinearity of the output capacitance of the device can significantly influence the over-voltage. A simple control without introducing additional hardware circuit or complex software algorithm is proposed to attenuate the effect of the nonlinear output capacitance. Multi-pulse test is conducted for a 3L-ANPC converter built with silicon carbide (SiC) MOSFETs. With the proposed control, the testing results show that the peak drain-source voltage of both active and non-active switches is reduced by more than 20% compared to the conventional control.

This paper presents the coupled inductor design for interleaved three-level active neutral point clamped (ANPC) inverter considering electromagnetic interference (EMI) noise reduction. Compared to two-level case, the scenarios involved in the three-level space vector modulation (SVM) are more complicated when analyzing the volt-seconds of the coupled inductor for paralleled three-level inverter. At system level, the purpose of converter interleaving is to reduce EMI noise and ripple current in most applications, and coupled inductor design should consider the needs of EMI noise reduction and EMI filter design. These issues are discussed in this paper. The relationship between circulating current and EMI noise is illustrated. EMI filter corner frequency as a function of interleaving angle is analytically derived, and optimal interleaving angle for maximum common-mode (CM) filter and differential-mode (DM) filter corner frequencies is discussed. Coupled inductor design methodology for interleaved three-level inverters with SVM is then presented. Experiments on two interleaved ANPC inverters are conducted. The results verify the coupled inductor design. With the derived optimal interleaving angle, the CM and DM EMI noise are significantly reduced.

This paper presents harmonic analysis of common-mode reduction (CMR) modulation for three-level voltage source inverters. The analytical model to calculate the harmonics of CMR modulation with arbitrary PWM sequence is developed. The impact of alternative PWM sequences of CMR modulation on harmonics is investigated. New three-state and four-state PWM sequences of CMR are proposed which spread the energy centered in the carrier frequency in the conventional CMR, and thus reduce the voltage peaks in frequency domain. Experiments are conducted on a three-level neutral point clamped inverter. Experiment results verify the developed analytical model and harmonic analysis.

Coaxial shunt resistors are very useful for measuring the ultra-fast current in wide-bandgap device switching transients. One of their major drawbacks is the relatively large parasitic inductance. The traditional coaxial shunt resistors are reviewed and the relationship between energy rating and parasitic inductance is determined. The parasitic inductance can be greatly reduced with a lower energy rating. A measurement method for characterizing their up to GHz bandwidth is also reported. Lower than expected bandwidth was observed and a fix using measured transfer characteristics is therefore described.

Wide bandgap (WBG) semiconductor devices and cryogenic cooling are key enablers for highly-efficient ultra-dense power electronics converters, which are critical for future more electric aircraft applications. For the development and optimization of a cryogenically-cooled converter, an understanding of power semiconductor characteristics, especially for emerging WBG devices, is critical. This paper focuses on WBG device characterization at cryogenic temperatures. First, the testing setup for cryogenic temperature characterization is introduced. Then several WBG device candidates (e.g., 1200-V SiC MOSFETs and 650-V GaN HEMTs) are characterized from room to cryogenic temperatures. The test results are presented with trends summarized and analyzed, including on-state resistance, breakdown voltage, and switching performance.

Switching transient overvoltage is inevitable in hard switching applications, and the faster switching speed of SiC MOSFETs suggests even worse overvoltage. This paper focuses on the turn-on overvoltage. To understand its nature, the switching transient is analyzed, and it shows the turn-on overvoltage is largely independent of load current condition. This phenomenon is verified by characterizing the turn-on overvoltage of a SiC MOFET and a SiC Schottky diode. Finally, a SPICE-based model is also built to understand the switching transient more accurately, and the modeling method can accurately predict the turn-on overvoltage and help select device voltage rating.

Dead-time, device output capacitance, and other non-ideal characteristics cause voltage error for the midpoint PWM voltage of the semiconductor phase-leg employed in a voltage-source inverter (VSI). Voltage-second balancing is a well-known concept to mitigate this distortion and improve converter power quality. This paper proposes a unique voltage-second balancing scheme for a SiC based voltage source inverter using online condition monitoring of turn-off delay time and drain-source voltage rise/fall time. This data is sent to the micro-controller to be used in an algorithm to actively adjust the duty cycle of the input PWM gate signals to match the voltage-second of the non-ideal output voltage with an ideal output voltage-second. The monitoring system also allows for this implementation to eliminate the need for precise current sensing and allows for the implementation to be load independent. Dynamic current sensing is still a developing technology, and each load has a unique effect on the output voltage distortion. Test results for a 1 kW half-bridge inverter implementing this monitoring system and voltage-second balancing scheme show a 70% enhancement on the error against the ideal fundamental current value of the output current and a 2% THD improvement on the output current low frequency harmonics.

In this paper, an extra junction capacitance and its associated switching commutation path are identified in three-level ac/dc converters, which were previously overlooked due to the off-state of the related device in half line cycle. The impact of this effect on power loss is analyzed, showing an underestimated switching loss in the traditional loss calculation of three-level converters. Through a proposed loss re-evaluation approach based on energy data of conventional double pulse tester (DPT), the corrected loss matches experimental results obtained from a 450kHz 650 V Gallium Nitride (GaN) based Vienna-type rectifier, showing 17.4% additional switching loss due to this effect. And the dominant extra switching loss is found to be Coss loss instead of overlap loss in WBG converters. Thefore, the effect is severe in high swtiching frequency high-speed wideband gap (WBG) based three-level converters.

As wide bandgap (WBG) semiconductors are gradually adopted for high switching frequency high power-density power converter, new challenges arise from control to hardware design. In this paper, an improved input current sampling method is proposed for three-phase rectifiers to avoid sampling noises when rectifiers are operated at high speed and high switching frequency. Experimental results obtained from a 450-kHz enhancement-mode Gallium Nitride (GaN) high-electron-mobility transistor (HEMT) based three-phase three-level Vienna-type rectifier demonstrate the good performance of the sampling method.

Although SiC MOSFETs show superior switching performance compared to Si IGBTs, it is unknown whether SiC MOSFETs have the same advantage over Si super junction (SJ) MOSFETs such as CoolMOS. This paper analyzes the switching performance in different switching cell configurations and summarizes the impact factors that influence switching loss. A double pulse test is conducted for a SiC MOSFET and a CoolMOS with the same voltage and current rating. In the FET/diode cell structure, a SiC Schottky diode is used as the upper device to eliminate the reverse recovery, and the testing results show that the SiC MOSFET has 2.4 times higher switching loss than the Si CoolMOS. This can be explained by the smaller transconductance and the higher Miller voltage of the SiC MOSFET. On the other hand, the Si CooMOS has 10 times higher switching loss than the SiC MOSFET in the FET/FET cell structure because of the significant turn-on loss caused by the poor reverse recovery of its body diode.

Due to the low availability, high cost, and limited performance of high voltage power devices in high voltage high power applications, series-connection of low voltage switches is commonly considered. Practically, because of the dynamic voltage unbalance and the resultant reliability issue, switches in series-connection are not popular, especially for fast switching field-effect transistors such as silicon (Si) super junction MOSFETs, silicon carbide (SiC) JFETs, SiC MOSFETs, and gallium nitride (GaN) HEMTs, since their switching performance is highly sensitive to gate control, circuit parasitics, and device parameters. In the end, slight mismatch can introduce severe unbalanced voltage. This paper proposes an active voltage balancing scheme, including 1) tunable gate signal timing unit between series-connected switches with <; 1 ns precision resolution by utilizing a high resolution pulse-width modulator (HRPWM) which has existed in micro-controllers; and 2) online voltage unbalance monitor unit integrated with the gate drive as the feedback. Based on the latest generation 600-V Si CoolMOS, experimental results show that the dynamic voltage can be automatically well balanced in a wide range of operating conditions, and more importantly, the proposed scheme has no penalty for high-speed switching.

Understanding the CM inductor core saturation mechanism and reducing core flux density is critical for CM inductor design optimization. Instead of a time domain method, this paper introduces frequency domain spectrum concept for CM inductor core saturation analysis and design optimization, which will provide designers a better understanding of CM inductor design. First, both core permeability and converter modulation index's opposite influence on DM flux density and CM flux density are identified. Then, CM flux density is further investigated based on the spectrum concept. Three components in the CM inductor which may cause large CM flux density and core saturation are summarized: (1) switching frequency related components, (2) impedance resonance frequency related components, and (3) modulation frequency related components. Each component is investigated for CM flux density reduction and filter design optimization. A connecting AC and DC side midpoint with notch filter structure is proposed to reduce modulation frequency related components. Experiment results are presented to verify the proposed concept and method.

Attenuation performance of an EMI filter can be significantly degraded by coupling, parasitics, and frequency-dependent nonlinearity of magnetic cores. In this paper, the effect due to mutual capacitive coupling in filter structures with T-shape joint is identified and investigated. Its mechanism indicates that this coupling is the dominant cause of performance degradation in T-shape filters. PCB slits and grounded shielding are proposed as two effective mitigation solutions, respectively, and are further combined to improve filter transfer gain up to 40 dB along the high frequency range. Experimental results obtained from a three-phase LCL common-mode (CM) filter verify the significant impact of this coupling and the effectiveness of the proposed mitigation methods.

Superconducting technologies such as motors together with the supporting cryogenic power electronic system are growing in importance in aircraft applications. It is critical to understand the influence of low temperature on filters of the power converter system in these applications. Also, it is worthwhile to investigate whether the converter system can achieve higher efficiency and high power density by utilizing the provided low temperature cooling environment. This paper conducted a comprehensive magnetic core characterization at low temperature to understand the core properties and support filter design at low temperature. The ferrite and nanocrystalline material are characterized from room temperature to cryogenic temperature in a wide range of operating frequencies. The results show that the permeability of ferrite material decreases by a factor of 7~8 and the core loss increases more than 10 times when operating at very low temperature. The permeability of nanocrystalline material decreases to 60% and the core loss increases 1.5~2.5 times when operating at very low temperature. The saturation flux density of both materials has slight increase at low temperature. Based on tested data, a case study of inductor design considering the low temperature cooling environment is presented to illustrate the influence of low temperature on inductor design.

To operate a converter at cryogenic temperatures, understanding the characteristics of power semiconductor devices is critical. This paper presents the characterization of state-of-the-art 1.2 kV SiC MOSFETs from leading manufacturers at cryogenic temperatures. The testing setup consisting of a cryogenic chamber, and a liquid nitrogen Dewar is introduced. With a curve tracer and double pulse test, comprehensive characterization of the SiC MOSFETs including both static and switching performance is conducted and evaluated. Test results indicate the on-resistance increases while the breakdown voltage remains relatively constant at cryogenic temperatures. Other characteristics like threshold voltage and switching loss vary significantly at cryogenic temperatures among devices from different manufacturers.

Zero sequence circulating current (ZSCC) exists when paralleled inverters have common dc and ac sides without isolation. Most of the prior work on the ZSCC analysis and suppression depended on paralleled two-level inverters. The scenarios involved in the three-level converters are more complicated. This paper investigates the ZSCC in paralleled three-level active neutral point clamped (ANPC) inverters. The mechanisms causing potential ZSCC jump in three-level paralleled ANPC inverters are analyzed. The ZSCC patterns of different interleaved modulation schemes for three-level converters are illustrated. Then, the active vector dividing concept is extended to three-level converters, and a modulation scheme is proposed to reduce the high frequency ZSCC in three-level converters. Experiments have been conducted on two paralleled three-level inverters. The current jump in ZSCC is observed and mitigated. The ZSCC with proposed modulation scheme is reduced to less than half of the ZSCC with conventional continuous space vector modulation (CSVM) scheme.

Unlike conventional passive or active filters, an impedance balancing circuit reduces the common-mode (CM) electromagnetic interference (EMI) noise by establishing an impedance balancing bridge. The EMI noise can be significantly reduced when the impedance bridge is designed to be well balanced. This paper investigates impedance balancing circuits in Dc-fed motor drive systems where both DC input and AC output need to meet EMI standards and thus EMI filters are needed for both sides. An impedance balancing circuit is proposed to reduce both DC and AC side CM noise. Two auxiliary branches are added to the conventional passive filters to establish an impedance bridge and reduce CM noise. The design criteria are presented, and the impact of the proposed impedance balancing circuit on both sides CM noise are investigated. It shows that the proposed impedance balancing circuit can reduce DC side and AC side CM noise based on different mechanisms. The CM noise reduction performance of the proposed method does not depend on the motor and cable models. Experiment results are presented to demonstrate the feasibility and effectiveness of the proposed method.

One of the popular converter topologies applied in high power dc-ac applications is the three-level active neutral point clamped (ANPC). Owing to relatively low switching frequency and slow switching speed of these topologies in high power applications, the commutation loop analysis in these topologies has not been fully conducted, and the over-voltage issue of non-active switches has not been thoroughly analyzed. This paper reveals an over-voltage issue on non-active switches in three level inverters due to multi-commutation loop. The detailed mode analysis during the commutation and related over-voltage issue are given. Finally, Si-based ANPC with 140 kHz switching frequency and SiC-based ANPC converters with 280 kHz switching frequency and high switching speed are tested respectively to compare and verify the over-voltage issue for non-active switches.

In order to evaluate the feasibility of newly developed GaN devices in a cryogenic-cooled converter, this paper characterizes a 650 V enhancement-mode Gallium-Nitride heterojunction field-effect transistor (GaN HFET) at cryogenic temperatures. The characterization includes two parts: static and dynamic characterization. The results show that this GaN HEMT is an excellent device candidate to be applied in cryogenic-cooled applications. For example, transconductance at cryogenic temperature is 2.5 times of one at room temperature, and accordingly, peak di/dt during turn-on transients at cryogenic temperature is around 2 times of that at room temperature. Moreover, the on-resistance of the channel at cryogenic temperature is only one-fifth of that at room temperature.

This paper presents a new boundary condition for designing phase legs when using the decoupling capacitance method. New SiC MOSFETs have much higher short-circuit currents-over 14X datasheet rating-then comparable Si IGBT devices. The energy draw on the decoupling capacitance due to this can be a large step input that over-voltages the device if not accounted for. Decoupling capacitance requirements have previously been based on switching conditions during normal operation and may not be sufficient for high current devices or modules. Furthermore, fast protection work has focused on lower current discrete devices whereas this issue becomes more prevalent in higher current configurations. Analysis of device over-voltage during short-circuit events is presented along with new sizing guidelines for DC link decoupling capacitance.

This paper presents the occurrence of potentially destructive oscillation in paralleled power MOSFETs during short-circuit events. Paralleling discrete power devices is desirable in many designs in order to increase power output. Short circuits cause high voltages, saturation current and local temperatures creating unstable environments within devices. Current redistribution can occur between device gates in this environment which can excite oscillation in parallel circuitry if not properly accounted for. Analysis of the phenomenon including experimental results are presented along with mitigation steps.

Middle-point inductance Lmiddle can be introduced in power module designs with P-cell/N-cell concept. In this paper, the effect of middle-point inductance on switching transients is analyzed first using frequency domain analysis. Then a dedicated multiple-chip power module is fabricated with the capability of varying Lmiddle. Extensive switching tests are conducted to evaluate the device's switching performance at different values of Lmiddle. Experiment result shows that the active MOSFET's turn-on loss will decrease at higher values of Lmiddle while its turn-off loss will increase. Detailed analysis of this loss variation is presented. In addition to switching loss variation, it is also observed that different voltage stresses are imposed on the active switch and anti-parallel diode. Specifically, in the case of lower MOSFET's turn-off, the maximum voltage of lower MOSFET increases as Lmiddle goes up; however, the peak voltage of anti-parallel diode decreases significantly. The analysis and experiment results will provide design guidelines for multiple-chip power module package design with P-cell/N-cell concept.

This paper introduces a dead-time optimization technique for a 2-level voltage source converter (VSC) using turn-off transition monitoring. Dead-time in a VSC impacts power quality, reliability, and efficiency. Silicon carbide (SiC) based VSCs are more sensitive to dead-time from increased reverse conduction losses and turn-off time variability with operating conditions and load characteristics. An online condition monitoring system for SiC devices has been developed using gate drive assist circuits and a micro-controller. It can be leveraged to monitor turn-off time and indicate the optimal dead-time in each switching cycle of any converter operation. It can also be used to specify load current polarity, which is needed for dead-time optimization in an inverter. This is an important distinction from other inverter dead-time elimination/optimization schemes as current around the zero current crossing is hard to accurately detect. A 1kW half-bridge inverter was assembled to test the turn-off time monitoring and dead-time optimization scheme. Results show 91% reduction in reverse conduction power losses in the SiC devices compared to a set dead-time of 500ns switching at 50 kHz.

While fast switching brings many benefits, it also presents unwanted ringing during switching transient. In this paper, an increasing magnitude ringing phenomenon is observed during the MOSFET turn-off transient. The unusual phenomenon is replicated in simulation and it is found the MOSFET channel is turned on again after it is turned off. The major cause to this unexpected turn on is found to be common source inductance and a moderate 3 nH one in simulation replicates the severe self-turn-on ringing observed in experiment. This paper reveals the detrimental effect of common source inductance in fast switching. Therefore, Kelvin source connection in circuit and package design is strongly recommended.

Cooling a converter to low temperatures, e.g. using cryogenic cooling, can significantly improve the efficiency and density of a power conversion system. For the development and optimization of a cryogenically-cooled converter, an understanding of power semiconductor characteristics is critical. This paper focuses on the characterization of high-voltage, high-speed switching, power semiconductors at cryogenic temperature. First, the testing setup for cryogenic temperature characterization is introduced. Three testing setups are established for cryogenic switch characterization, including: 1) on-state resistance and forward voltage drop of the body diode, 2) leakage current and breakdown voltage, and 3) switching characteristics. For each testing set up, the corresponding testing configurations, hardware setups, and practical considerations are summarized. Additionally, the test results at cryogenic temperature are illustrated and analyzed for 650-V Si CoolMOS. It is then demonstrated that when the cryogenic temperature test results are compared to that of room temperature, the device performance varies significantly; for example: on-state resistance reduces by 63%, breakdown voltage drops by 31%, switching time decreases and switching energy loss decreases by 26%. Furthermore, the peak dv/dt during transient switching at cryogenic temperature exceeds 100 V/ns which is comparable to the emerging wide bandgap Gallium Nitride devices.

Silicon Carbine (SiC) based power semiconductor devices have increased voltage blocking capability, in the meantime, satisfactory switching performance as compared to conventional Silicon (Si) devices. This paper focuses on the latest generation 10 kV / 20 A SiC MOSFETs and investigates their protection schemes and temperature-dependent switching characteristics. A high voltage double pulse test platform is constructed including solid state circuit breaker, gate drive and hot plate under device under test (DPT) for temperature-dependent characterization. A behavioral model is established to analytically investigate switching performance of 10 kV SiC MOSFETs, and the temperature-dependent factors are studied in detail. The experimental results under various load currents and gate resistances from 25 C to 125 C at 7 kV dc-link voltage are presented.

The higher switching speed of wide bandgap devices requires new analysis to interpret voltage waveforms during turn-on and turn-off transients. Although the Miller effect remains a dominant feature, the conventional Miller plateau equations do not accurately model the dvds/dt for fast-switching devices such as GaN FETs. This paper derives equations for instantaneous dvds/dt based on static datasheet parameters, considering the Miller effect and the displacement of junction capacitance charges through the saturated channel. These equations will be verified with experimental results for an enhancement-mode GaN FET across a range of operating conditions. Furthermore, the peak dvds/dt is predicted using the derived equations, and shown to be more accurate than other models when compared to GaN experimental results.

Wide bandgap (WBG) semiconductors owing to their low loss and high switching capability, are gradually adopted in high power-density high efficiency applications, and impose new challenges from control to hardware design. In this paper, a Gallium Nitride (GaN) HEMT plus SiC diode based Vienna type rectifier is proposed to serve as the power factor correction stage for a high-density battery charger system. To meet low current harmonic requirement, PWM voltage distortion during turn-off transition, found as the main harmonics contributor, is studied. The distortion mechanism led by different parasitic capacitances of WBG devices is presented. A mitigation scheme is thereafter proposed considering their nonlinear voltage-dependent characteristics and eventually deduced from a pulse-based turn-off compensation to a generic modulation correction. Simulation and experimental results through a 450 kHz enhancement-mode GaN based Vienna type rectifier finally demonstrate the high performance of the proposed approach, showing a THD reduction up to 7% with a relatively low-speed control.

Due to the realization of zero voltage switching (ZVS) under the full load range, LLC resonant converter is widely adopted in the telecom, battery charger and several applications, characterized with high efficiency, high frequency and high power density, to realize DC conversion. Recently, by using Gallium Nitride (GaN) HFETS, switching frequency of LLC converters is further increased. However, ZVS failure cannot be predicted accurately in the high switching frequency condition by only considering traditional constraints generally applied in the low frequency design. The traditional constraints result in a too optimistic estimation of the dead time to obtain ZVS without considering the reverse resonance under the dead time and the design of resonant parameters at high resonant frequency and high load condition. The experiment shows the LLC converter loses ZVS even through the converter satisfies the ZVS constraints proposed by previous paper. In this paper, the failure mode will be investigated in detail and an accurate ZVS boundary is proposed for high frequency LLC converter design. The proposed theory was verified on a 1 MHz, 1500 W LLC prototype.

Junction temperature is a critical indicator for health condition monitoring of power devices. Concerning the reliability of emerging silicon carbide (SiC) power semiconductors due to immaturity of new material and packaging, junction temperature measurement becomes more significant and challenging, since SiC devices have low on-state resistance, fast switching speed, and high susceptibility to noise and parasitics in circuit implementations. This paper aims at developing a practical and cost-effective approach for online junction temperature monitoring of SiC devices using turn-off delay time as the thermo-sensitive electrical parameter (TSEP). The sensitivity is analyzed for fast switching SiC devices. A gate impedance regulation assist circuit is designed to improve the sensitivity by a factor of 60 and approach hundreds of ps/°C in the case study with little penalty of the power conversion performance. Also, an online monitoring system based on three gate assist circuits is developed to monitor the turn-off delay time in real time with the resolution within hundreds of ps. In the end, the micro-controller is capable of “reading” junction temperature during the converter operation with less than 0.5 °C measurement error. Two testing platforms for calibration and online junction temperature monitoring are constructed, and experimental results demonstrate the feasibility and accuracy of the proposed approach. Furthermore, the proposed gate assist circuits for sensitivity improvement and high resolution turn-off delay time measurement are transistor based and suitable for chip level integration.

High speed switching of WBG devices causes their switching behavior to be highly susceptible to the parasitics in the circuit, including inductive loads. An inductive load consisting of a motor and power cable significantly worsens the switching speed and losses of SiC MOSFETs in a PWM inverter. This paper focuses on the motor plus power cable based inductive load, and aims at mitigating its negative influence during the switching transient. An auxiliary filter is designed and inserted between the converter and inductive load so that the parasitics of the load will not be “seen” from the converter side during the switching transient. Test results with Cree 1200-V/20-A SiC MOSFETs show that the proposed auxiliary inductor enables the switching performance with a practical inductive load (e.g., motor plus cable based inductive load) to exhibit behavior close to that when the optimally-designed double pulse test load inductor is employed.

Enhancement-mode GaN HFETs enable efficient high-frequency converter design, but this technology is relatively new and exhibits different characteristics from Si or SiC MOSFETs. GaN performance at elevated temperature is especially unique. Turn-on time increases significantly with temperature, and turn-on losses increase as a result. This phenomenon can be explained based on the relationships between junction temperature and GaN device transconductance, and between transconductance and turn-on time. An analytical relationship between temperature and turn-on loss has been derived for the 650-V GS66508 from GaN Systems, and verified with experimental results. Based on this relationship, a detailed model is developed, and a simplified scaling factor is proposed for estimating turn-on loss in e-mode GaN HFETs, using room-temperature switching characterization and typically published datasheet parameters.

Gallium Nitride (GaN) HFETS are an enabling technology for high-density converter design. This paper proposes a three-level dc-dc converter with dual outputs based on enhancement-mode GaN devices, intended for use as a battery charger in aircraft applications. The charger can output either 28 V or 270 V, selected with a jumper, which meets the two most common dc bus voltages in airplanes. It operates as an LLC converter in the 28 V mode, and as a buck converter in the 270 V mode. In both operation modes, the devices can realize zero-voltage-switching (ZVS). With the chosen modulation method, the converter can realize the frequency doubling function to act as an interleaved converter. For the LLC mode, the resonant frequency is twice the switching frequency of primary-side switches, and for buck mode, the frequency of the output inductor current is also twice the switching frequency. This helps to reduce the size of magnetics while maintaining low switching loss. Also, the converter utilizes the matrix transformer with resonant parameters designed to avoid ZVS failure. The operation principle of the converter is analyzed and verified on a 1MHz resonant frequency prototype.

Many intelligent gate drivers being designed for new state-of-the-art WBG devices typically only focus on protection and driving capabilities of the devices. This paper introduces an intelligent gate driver that incorporates online condition monitoring of the WBG devices. For this specific case study, three timing conditions (turn-off delay time, turn-off time, and voltage commutation time) of a silicon carbide (SiC) device are online monitored. This online monitoring system is achieved through gate driver assist circuits and a micro-controller. These conditions are then utilized to develop converter-level benefits for the converter application the SiC devices are placed in. Junction temperature monitoring is realized through turn-off delay time monitoring. Dead-time optimization is achieved with turn-off time monitoring. Dead-time compensation is obtained with turn-off time and voltage commutation time monitoring. The case study converter assembled for testing purposes is a half-bridge inverter using two SiC devices in a phase-leg configuration. All timing conditions are correctly monitored within reasonable difference of the actual condition time. A calibration curve was created to give a direct relationship between turn-off delay time and junction temperature. The half-bridge inverter can operate at 600 Vdc input and successfully obtain a junction temperature measurement through monitored td_off and the calibration curve. Furthermore, the proposed online condition monitoring system is transistor based and suitable for the chip level integration, enabling this practical approach to be cost-effective for end users.

This paper presents a gate driver integrated circuit (IC) for Silicon Carbide (SiC) devices to fully utilize their high switching speed capabilities in a phase-leg configuration. Based upon the intrinsic properties prevalent in SiC devices, gate assist circuitry is integrated into a gate driver IC to control the gate voltages seen by both devices in a phase-leg during different switching transients. Compared to a traditional gate driver IC, the proposed circuit has the potential of suppressing the cross talk seen by both devices thus increasing the overall switching speed of the phase-leg. The replacement of the conventional gate driver with an IC effectively lowers the gate impedance loop by reducing the number of on-board traces and moving essential traces to inside the chip. Therefore, larger transient currents and higher slew rates can be achieved with an IC compared to nominal commercially available gate driver devices. Meanwhile, the added functionality of cross talk suppression, not normally available in other gate drive IC designs, minimizes the spurious gate voltages from cross talk to within the required operating ranges of SiC devices.

Cross conduction is a well-known issue in buck converters and phase-leg topologies, in which fast switching transients cause spurious gate voltages in the synchronous device and a subsequent increase in switching loss. Cross conduction can typically be mitigated with a well-designed gate drive, but this is challenging with WBG devices. Phase legs using SiC and GaN devices can experience heavy cross conduction loss due to their exceptionally fast switching transients. Enhancement-mode GaN heterojunction field-effect transistors (HFETs) in the 600-V class are now commercially available, with switching transients as fast as 200 kV/μs. A double pulse test setup was used to measure the switching loss of one such GaN HFET, with several gate drive circuits and resistances. The results were analyzed and compared to characterize the effects of cross conduction in the active and synchronous devices of a phase-leg topology with enhancementmode GaN HFETs.

Four factors impact high speed switching of silicon carbide (SiC) devices in voltage source converters, including limited gate driving capability, cross-talk, parasitics associated in switching loop, and parasitics of inductive load. This paper focuses on a solution to mitigate the adverse impact of the aforementioned factors. First, an intelligent gate drive is developed for gate driving capability enhancement and cross-talk suppression. Second, placement and layout design of power devices, gate drive, and power stage board are proposed to minimize parasitics for fast switching and over-voltage mitigation. Third, an auxiliary filter is designed to mitigate the negative impact of inductive load's parasitics during the switching transient. Finally, by utilizing all techniques developed above, a three-phase voltage source inverter with Cree 1200-V/20-A SiC MOSFETs is established. Test results show that the switching behavior of SiC devices in actual three-phase voltage source inverter fed motor drives can mostly repeat the switching performance tested by the optimally-designed double pulse test.

GaN heterojunction field-effect transistors (HFETs) in the 600-V class are relatively new in commercial power electronics. The GaN Systems GS66508 is the first commercially available 650-V enhancement-mode device. Static and dynamic testing has been performed across the full current, voltage, and temperature range to enable GaN-based converter design using this new device. A curve tracer was used to measure Rds-on across the full operating temperature range, as well as the self-commutated reverse conduction (i.e. diode-like) behavior. Other static parameters such as transconductance and gate current were also measured. A double pulse test setup was constructed and used to measure switching loss and time at the fastest achievable switching speed, and the subsequent over-voltages due to the fast switching were characterized. Based on these results and analysis, an accurate loss model has been developed for the GS66508 to allow for GaN-based converter design and comparison with other commercially available devices in the 600-V class.

This paper presents an active gate driver for Silicon Carbide (SiC) devices to fully utilize their potentials of high switching-speed capability in a phase-leg configuration. Based on the SiC device's intrinsic properties, a gate assist circuit consisting of two auxiliary transistors with two diodes is introduced to actively control the gate voltages and gate loop impedances of both devices in a phase-leg during different switching transients. Compared to a conventional gate driver, the proposed circuit has the capability of increasing the switching speed of the phase-leg power devices, suppressing the cross-talk to below device limits. Based on CREE's 2nd generation 1200-V SiC MOSFETs, the test results demonstrate the effectiveness of this active gate driver under various operating conditions. The switching time decreases by up to 28% during turn-on and 50% during turn-off in the prototype circuit, resulting in up to 31% reduction in switching energy loss. In addition, spurious gate voltages induced by cross-talk are limited within the required range.

Dead-time in the voltage source converter significantly affects the reliability, power quality and losses. For SiC devices, considering the high sensitivity of turn-off time to the operating conditions (> 5× difference between light load and full load), as well as large extra energy loss induced by reverse conduction during superfluous dead-time (~ 15% of the switching loss), traditional fixed dead-time setting becomes inappropriate. This paper introduces an approach to achieve optimum dead-time for SiC based voltage source converter. First, turn-off behaviors under various operating conditions are investigated, and the relation between optimal dead-times and load currents are established. Second, a practical method for adaptive dead-time regulation is proposed, which consists of a dead-time optimization model and two gate assist circuits to sense the voltage commutation time during turn-off transient. Via synthesizing the monitored switching condition together with the preset dead-time optimization model, the micro-controller is able to online adjust the dead-time. Finally, based on a buck converter with 1200-V SiC MOSFETs, the test results show that by means of the proposed method, the power loss decreases by 12% at full load and 18.2% at light load.

High reliability of semiconductor power devices is one of the key design objectives for power conversion systems. Fast switching SiC devices are susceptible to cross-talk, and these devices also have limited over-current capability. Both of these issues significantly threaten the reliable operation of SiC-based voltage source converters. This paper proposes two gate assist circuits capable of suppressing cross-talk and preventing shoot-through faults to promote the reliable use of SiC devices within a voltage source converter. Experimental results and detailed analysis are presented to verify the feasibility of the proposed approach.

Double pulse test (DPT) is a widely accepted method to evaluate the switching characteristics of semiconductor switches, including SiC devices. However, the observed switching performance of SiC devices in a PWM inverter for induction motor drives (IMD) is almost always worse than the DPT characterization, with slower switching speed, more switching losses, and more serious parasitic ringing. This paper systematically investigates the factors that limit the SiC switching performance from both the motor side and inverter side, including the load characteristics of induction motor/power cable, two more phase-legs for the three-phase PWM inverter as compared to the DPT, and the parasitic capacitive coupling effect between power devices and heat sink. Based on the three-phase PWM inverter with 1200 V SiC MOSFETs, the test results show that the induction motor, especially with a relatively long power cable, will significantly impact the switching performance, leading to switching time increase by a factor of 2, switching loss increase up to 30%, and serious parasitic ringing with 1.5 μs duration as compared to that tested by DPT. In addition, the interactions among the three phase-legs cannot be ignored unless the decoupling capacitors are mounted close to each phase-leg to support the dc bus voltage during switching transients. Also, the coupling capacitance induced by the heat sink equivalently increases the junction capacitance of power devices. However, its influence on the switching behavior in the motor drives is small considering the relatively large capacitance of the motor load.

This paper focuses on understanding the key impacting factors for switching speed of wide bandgap (WBG) devices in a voltage source converter. First, the constraints and challenges of WBG devices during fast switching transients are summarized. Special attention is given to the transient gate-source and drain-source voltages. Second, the impacts of major components in voltage source converter, including gate drivers, parasitics, inductive loads, and cooling systems, on the switching performance of power devices are systematically investigated. The critical parameters for each component are highlighted. Finally, design criteria are suggested to maximize switching speed of WBG devices.

This paper investigates the effects of ringing on the switching losses of wide band-gap (WBG) devices in a phase-leg configuration. An analytical switching loss model considering the parasitic inductance, stray resistance, devices' junction capacitances, and reverse recovery characteristics of the freewheeling diode is derived to identify the switching energy dissipation induced by damping ringing. This part of energy is found to be at most the reverse recovery energy and the energy stored in the parasitics, which is a small portion of the total switching energy. But the parasitic ringing causes interference between two devices in a phase-leg (i.e., cross talk). It is observed that during the turn-on transient of one device, the resonance among parasitics results in high overshoot voltage on the complementary device in a phase-leg. It worsens the cross talk, leading to large shoot-through current and excessive switching losses. The analysis results have been verified by double pulse test with a 1200 V SiC MOSFETs based phase-leg power module.

Double pulse tester (DPT) is a widely accepted method to evaluate the switching behavior of power devices. Considering the high switching-speed capability of wide band-gap (WBG) devices, the test results become significantly sensitive to the alignment of voltage and current (V-I) measurement. Also, because of the shoot-through current induced by Cdv/dt, during the switching transient of one device, the switching losses of its complementary device in the phase-leg is non-negligible. This paper summarizes the key issues of DPT, including layout design, measurement considerations, grounding effects and data processing. Among them, the latest probes for switching waveform measurement are compared, the methods of V-I alignment are discussed, and the impact of grounding effects induced by probes on switching waveforms are investigated. Also, for the WBG devices in a phase-leg configuration, a practical method is proposed for switching loss evaluation by calculating the difference between the input energy supplied by a dc capacitor and the output energy stored in a load inductor. Based on a phase-leg power module built with 1200 V SiC MOSFETs, the test results show that regardless of V-I timing alignment, this method can accurately indicate the switching losses of both the upper and lower switches by detecting only one switching current.

No power conversion without power semiconductors Power semiconductors is NOTHING without a gate driver! The gate driver will properly drive a power semiconductor and bring the maximum performance. For WBG devices, Driving capability of gate driver IC (rise/fall time, pull-up/pull-down resistance) & CM transient immunity of gate driver isolation are special requirements. The gate driver will protect a power semiconductor and entire converter if something goes wrong. For WBG devices, Cross-talk is easily induced, leading to potential hazard of shoot-through failure and gate terminal reliability issues. A gate assist circuit was introduced for cross-talk suppression. Short circuit capability is limited. The desaturation protection circuit with <; 200 ns response time was described for device reliability enhancement.

Silicon Carbide (SiC) power devices have inherent capability for fast switching. However, in a phase-leg configuration, high dv/dt will worsen the interference between the two devices during a switching transient (i.e., cross talk), leading to slower switching speed, excessive switching losses, and overstress of power devices. Unfortunately, due to intrinsic properties, such as low threshold voltage, low maximum allowable negative gate voltage, and large internal gate resistance, SiC power devices are easily affected by cross talk. This paper proposes a novel gate assist circuit using an auxiliary transistor in series with a capacitor to mitigate cross talk. Based on CMF20120D SiC MOSFETs, the experimental results show that the new gate assist circuit is capable of reducing the turn-on switching loss up to 19.3%, and suppress the negative spurious gate voltage within the maximum allowable negative gate voltage without the penalty of further decreasing the device switching speed. Moreover, in comparison to a conventional gate drive with -2 V turn-off gate voltage, this gate assist circuit without negative isolated power supply is more effective in improving the switching behavior of power devices in a phase-leg. The proposed gate assist circuit is a cost-effective solution for cross talk mitigation.

In a phase-leg configuration, the high switching-speed performance of silicon carbide (SiC) devices is limited by the interaction between the upper and lower devices during the switching transient (cross talk), leading to additional switching losses and overstress of the power devices. To utilize the full potential of fast SiC devices, this paper proposes a gate assist circuit using two auxiliary transistors and a diode to eliminate cross talk. Based on CMF20120D SiC MOSFETs, the experimental results show that this gate assist methodology is effective to suppress cross talk under different operating conditions, enabling turn-on switching losses reduction by up to 19.6%, and negative spurious gate voltage minimization within the maximum allowable negative gate voltage of the power devices without the penalty of reduced switching speed. Moreover, in comparison to the conventional gate driver with -2 V turn-off gate voltage, this gate assist circuit without a negative isolated power supply is more effective in enhancing the switching behavior of power devices in a phase-leg. Accordingly, the proposed gate assist circuit is a cost-effective solution for cross talk suppression.

An overlap time for two commutating switches is necessary to prevent current interruption in a three-phase buck rectifier, but it may cause input current distortion. In this paper, a modified pulse-based compensation method is proposed to compensate for the overlap time. In addition to the traditional method which places the overlap time based on the voltage polarity, this new method first minimizes the overlap time to reduce its effect and then compensates the pulse width according to the sampled voltage and current. It is verified by experiments that the proposed method has better performance than the traditional method, especially when the line-to-line voltage crosses zero. Another distortion comes from the irregular pulse distribution when two sectors change in a 12-sector space vector PWM. This paper proposes two compensation methods for that scenario as well, compensating the duty cycle and increasing switching frequency near the boundaries of two sectors. It is shown through experiments that both methods can reduce the input current distortion in the buck rectifier.

In recent years, Si power MOSFET is approaching its performance limits, and Gallium Nitride (GaN) HEMT is getting mature. This paper evaluates the 600 V cascode GaN HEMT performance, and compares it with the state-of-the-art Si CoolMOS in LLC resonant converter. First, the static characterization of 600 V cascode GaN HEMT is described in different temperatures. The switching performance is tested by a double pulse tester to provide the turn-off loss reference to the design of LLC resonant converter. Second, a 400 V-12 V/300 W/1 MHz all-GaN-based converter with the 600 V cascode GaN HEMT is compared with a Si-based converter with the 600 V Si CoolMOS. The device output capacitance is a key factor in the design and loss analysis of LLC resonant converter. The design results show that the total GaN device loss of the all-GaN-based converter can be improved by 42% compared with the total Si device loss. Finally, both 400 V-12 V/300 W/1 MHz Si-based and GaN-based LLC resonant converter prototypes are tested and compared with waveforms and efficiency curves.

Advanced power semiconductor devices, especially wide band-gap devices, have inherent capability for fast switching. However, due to the limitation of gate driver capability and the interaction between two devices in a phase-leg during switching transient (cross talk), the switching speed is slower than expected in practical use. This paper focuses on identifying the key limiting factors for switching speed. The results provide the basis for improving gate drivers, eliminating interference, and boosting switching speed. Based on the EPC2001 Gallium Nitride transistor, both simulation and experimental results verify that the limiting factors in the gate loop include the pull-up (-down) resistance of gate driver, rise (fall) time and amplitude of gate driver output voltage; among these the rise (fall) time plays the primary role. Another important limiting factor of device switching speed is the spurious gate voltage induced by cross talk between two switches in a phase-leg. This induced gate voltage is not only determined by the switch speed, but also depends on the gate loop impedance, junction capacitance, and operating conditions of the complementary device.

Silicon Power MOSFETs, with more than thirty years of development, are widely accepted and applied in power converters. Gallium Nitride (GaN) power devices are commercially available in recent years [1], but the device performance and application have not been fully developed. In this paper, GaN devices are compared with state-of-art Si devices to evaluate the device impact on soft-switching DC-DC converters, like LLC resonant converter. The analytical approach of device selection and comparison are conducted and loss related device parameters are derived. Total device losses are compared between Si and GaN based on these parameters. GaN shows less loss compared with Si, yielding approximately a 20% reduction of total device loss. Two 300 W, 500 kHz, 48 V-12 V GaN-based and Si-based converter prototypes are built and tested. Since the body diode forward voltage drop of GaN device is high, the dead time is adjusted to minimize the body diode conduction period. The peak efficiency of the GaN-based converter is 97.5%, and the full load efficiency is 96.1%, which is around 0.3% higher than the Si-based converter at full load. The test results shows that, although GaN device has lower loss, the improvement of converter efficiency is not much. The reason is that the transformer loss accounts for more than 60% of total loss. Therefore, a transformer which fits the GaN device characteristic need to be further investigated.